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#vlsi — Public Fediverse posts

Live and recent posts from across the Fediverse tagged #vlsi, aggregated by home.social.

  1. All the conference papers I want to read are pay-walled at $33 per article (thanks IEEE). That actually gets expensive quickly. Frustrating.
    #AsyncLogic #VLSI #ASIC #Circuits

  2. Fun! I wonder if Valve's Portal took inspiration from the Real World Potato computer (300 kHz @ 0.75 V) described in researchgate.net/publication/2
    KW: #AsyncLogic #VLSI

  3. Shoot, I should probably have decorated with #asynclogic #tinytapeout #vlsi #verilog etc. Oh well, I'm new here. (I wonder if @mrg have made progress on async support in OpenRAM)