#vlsi — Public Fediverse posts

I wonder if I could get someone to sponsor getting these transistors made. #GF180mcu #BJT #NPN #ASIC #MagicVLSI #Magic #VLSI #Silicon #Semiconductor

I wonder if I could get someone to sponsor getting these transistors made. #GF180mcu #BJT #NPN #ASIC #MagicVLSI #Magic #VLSI #Silicon #Semiconductor

Just remember, your laptops and phones wouldn't exist without the separate works of a gay man and two trans women: Turing, Conway and Wilson. These are just the best known names too, there were likely many more.

#transrightsarehumanrights #lgbtqrights #vlsi #arm #computers

Just remember, your laptops and phones wouldn't exist without the separate works of a gay man and two trans women: Turing, Conway and Wilson. These are just the best known names too, there were likely many more.

#transrightsarehumanrights #lgbtqrights #vlsi #arm #computers

🚀 Meet 2cli: Empower your AI agents to seamlessly manipulate ANY commercial EDA tool's interactive shell—just like a real engineer!🛠️
🆓 Free on PyPI: pip3 install 2cli
See the magic after installing 2cli with the attached skill:
#AI #AIAgent #eda #tcl #ASICdesign #vlsi

🚀 Meet 2cli: Empower your AI agents to seamlessly manipulate ANY commercial EDA tool's interactive shell—just like a real engineer!🛠️
🆓 Free on PyPI: pip3 install 2cli
See the magic after installing 2cli with the attached skill:
#AI #AIAgent #eda #tcl #ASICdesign #vlsi

SystemLisp - an HDL simulator written in Common Lisp

https://github.com/systemlisp

#lisp #commonlisp #hdl #rtl #verilog #design #verification #vhdl #systemverilog #vlsi #programming #fpga

SystemLisp - an HDL simulator written in Common Lisp

https://github.com/systemlisp

#lisp #commonlisp #hdl #rtl #verilog #design #verification #vhdl #systemverilog #vlsi #programming #fpga

Get an insider look at open-source PDKs from the perspective of Japanese foundries! Jun-Ichi Okamura (AIST) explains how foundries see PDK openness and what it means for semiconductor design. A must-watch for EDA, VLSI and open hardware fans—insightful and practical! #OpenSource #PDK #Foundries #Semiconductors #VLSI #EDA #AIST #Japan #OpenHardware #English
https://peertube6.f-si.org/videos/watch/b5e9f42e-80af-4e98-8a5c-55227902dfdc

Somebody should do a cleanroom implementation of the Open Access interface #vlsi #asic

Somebody should do a cleanroom implementation of the Open Access interface #vlsi #asic

DashRTL v2025.12 is now available for free trial:
https://dashthru.com/freetrial

#systemverilog #vlsi #rtl

DashRTL v2025.12 is now available for free trial:
https://dashthru.com/freetrial

#systemverilog #vlsi #rtl

🚀 AI for hardware design is here.
Intel Sr. PE Desmond Kirkpatrick shows how LLMs and the ROHD framework enable agile, test-driven hardware development — for real synthesizable designs.
🎥 https://youtu.be/SAPAi8Y4Z68

#AI #Hardware #ROHD #OpenSourceHardware #EDA #VLSI #FPGA #Semiconductors

Образовательные технологии опробованные в России — работают и в США

Провели мероприятие в Калифорнийском политехническом государственном университете в Сан-Луис-Обиспо. Докладчиками были: ваш покорный слуга Юрий Панчул, два американских инженера проектирующие чип по ускорению ИИ, и китайский студент из Университета Калифорнии в Санта-Барбаре. Идея мероприятия возникла, когда я встретился с выпускником Cal Poly Стенли на конференции самоделкиных OpenSause, и он поведал мне то, что я уже знал из собеседований американских студентов: они изучают в вузе карты Карно, доходят до конечного автомата светофора, отдельно постигают классический 5-стадийный конвейер MIPS (ныне RISC-V), а потом идут на собеседование на работу, и - хоба! - выясняется что их карты Карно никого в индустрии не интересуют, а вопросы идут про сопряжение конвейера обработки данных (не процессорного!) и FIFO, чего они не проходили. Привожу ниже мой отчет на английском.

https://habr.com/ru/articles/961364/

#SystemVerilog #Gowin #Xilinx #Altera #ASIC #FPGA #TinyTapeout #Cal_Poly #Verilog #vlsi

Another highlight from the #Ubuntu booth at #IndiaFOSS2025 ✨

An attendee tried out Magic (Open Sourve VLSI layout tool) — running smoothly inside an #Ubuntu 25.10 VM created with LXD ⚡

Needless to say, LXD was buzzing at the booth! 🚀

#OpenSource #Linux #LXD #VLSI #FOSS

As RTL shifts from Verilog to SystemVerilog, unexpected compatibility issues often appear late in the flow—during synthesis, FV, LEC, or FPGA compilation. Code may compile fine in sim or lint but later fail due to certain syntax.

We tested 10 examples from the SV 2012 LRM and checked support in major EDA tools (●=supported, ○=not). Full list:
👉 https://github.com/DashThru/SV_compatibility_cases_from_LRM

DashRTL will have full SV 2023 LRM syntax coverage, to flag any syntax that may cause cross-tool issues.

#systemverilog #vlsi

Combine Tcl and Python in a single EDA Shell: tclpysh playground is now online.
https://dashthru.com/playground
( Use 'py' or 'tcl()' command to switch between languages )
#eda #tcl #python #vlsi #ASICdesign

Combine Tcl and Python in a single EDA Shell: tclpysh playground is now online.
https://dashthru.com/playground
( Use 'py' or 'tcl()' command to switch between languages )
#eda #tcl #python #vlsi #ASICdesign

It's finally the time for open source semiconductor manufacturing. https://www.brickstackr.com/posts/how-to-make-your-own-computer-chip-part-3 #vlsi #semiconductors #hackerfab #opensauce2025

It's finally the time for open source semiconductor manufacturing. https://www.brickstackr.com/posts/how-to-make-your-own-computer-chip-part-3 #vlsi #semiconductors #hackerfab #opensauce2025

Today I will be mostly looking at C++ plugin architectures. #LunaPnR #VLSI #ASIC

Today I will be mostly looking at C++ plugin architectures. #LunaPnR #VLSI #ASIC

Today #VLSI chips are uually CMOS, with a single phase clock, and often contain static circuitry. Early #MOS LSI and VLSI chips were PMOS or NMOS, and usually used two-phase or four-phase dynamic logic. I recently wondered why the four-phase techniques couldn't have been used with only three phases, obtaining most of the benefit of four-plase, but increasing circuit density and speed.
Well, I'm late to the party. It's not well-known, but NCR invented that in 1967:
https://patents.google.com/patent/US3497715A

Today #VLSI chips are uually CMOS, with a single phase clock, and often contain static circuitry. Early #MOS LSI and VLSI chips were PMOS or NMOS, and usually used two-phase or four-phase dynamic logic. I recently wondered why the four-phase techniques couldn't have been used with only three phases, obtaining most of the benefit of four-plase, but increasing circuit density and speed.
Well, I'm late to the party. It's not well-known, but NCR invented that in 1967:
https://patents.google.com/patent/US3497715A

Switching topics to I/O and game controller support, this week we look briefly at the PIA for Project Ember

The Ember PIA — Initial Design Part 1: Peripheral Interface Adapter
https://skicat.medium.com/21f7f4abb2e8

#cpudesign #retrodev #8bit #16bit #100DaysRTL #DigitalDesign #ElectronicsEngineering #TechInnovation #hardwaredesign #PCBDesign #RetroDev #KiCad #DIYProjects #retrocomputern #Verilog #ALU #8BitALU #VLSI #RTLDesign #FPGA #ASIC #ProcessorDesign

Boards look great! Starting the slow bring up with just the CPU, RAM, and ROM...and, of course, clock circuit and logic analyzer...

#cpudesign #retrodev #8bit #16bit #100DaysRTL #Verilog #ALU #8BitALU #VLSI #RTLDesign #FPGA #ASIC #DigitalDesign #ElectronicsEngineering #TechInnovation #ProcessorDesign #hardwaredesign #PCBDesign #RetroDev #KiCad #DIYProjects #retrocomputer

Next, we'll explore the details of the GPU and the initial design of the first simple text mode display!

The Flame GPU — Initial Design Part 2: Tilesheets, Tilemaps, and Graphics Registers
https://medium.com/the-ember-project/the-flame-gpu-initial-design-part-2-tilesheets-tilemaps-and-graphics-registers-8c638a19ec4f

#cpudesign #retrodev #8bit #16bit #100DaysRTL #Verilog #ALU #8BitALU #VLSI #RTLDesign #FPGA #ASIC #DigitalDesign #ElectronicsEngineering #TechInnovation #ProcessorDesign #hardwaredesign #PCBDesign #RetroDev #KiCad #DIYProjects #retrocomputer

The Ember Console — System Architecture Design: Basic Requirements
https://medium.com/the-ember-project/the-ember-console-system-architecture-design-basic-requirements-97de358a952a
Moving on to the system design, this is an overview of the remaining parts we need to design in order to create a working system capable of playing 80s and 90s-era homebrew video games.

#cpudesign #retrodev #8bit #16bit #100DaysRTL #Verilog #ALU #8BitALU #VLSI #RTLDesign #FPGA #ASIC #DigitalDesign #ElectronicsEngineering #TechInnovation #ProcessorDesign

"Tiny Tapeout is an educational project that makes it easier and cheaper than ever to get your designs manufactured on a real chip!"

https://tinytapeout.com

#opensource #asic #vlsi #chip #tinytapeout

Not every gate is symmetrical w.r.t its inputs. In order to allow asymmetrical gates to be mapped in all cases, all unique permutated AND-INVERTER graphs representing the gate must be present in the pattern matching set. This is obviously a problem for tomorrow..

#VLSI #ASIC #TechnologyMapping

Not every gate is symmetrical w.r.t its inputs. In order to allow asymmetrical gates to be mapped in all cases, all unique permutated AND-INVERTER graphs representing the gate must be present in the pattern matching set. This is obviously a problem for tomorrow..

#VLSI #ASIC #TechnologyMapping

Wanted to play around with #VLSI technology mapping using AND-INVERTER graphs. I got as far as reading a cell library in GENLIB format. Now I need to convert the boolean logic expressions into A-I graphs using DeMorgan substitutions. Running out of steam though.

Wanted to play around with #VLSI technology mapping using AND-INVERTER graphs. I got as far as reading a cell library in GENLIB format. Now I need to convert the boolean logic expressions into A-I graphs using DeMorgan substitutions. Running out of steam though.

The #Python/Scipy sparse linalg solver couldn't solve the quadratic placement problem for the industry standard 'adaptec1' benchmark. It ran out of memory (16 GB of RAM). This isn't even a large problem by today's standards. #vlsi #algebra

The #Python/Scipy sparse linalg solver couldn't solve the quadratic placement problem for the industry standard 'adaptec1' benchmark. It ran out of memory (16 GB of RAM). This isn't even a large problem by today's standards. #vlsi #algebra

@rafetoots This thread made me think: besides learning a programming language in depth, I wonder about your knowledge of version control (#git, #github), editors/IDE's (#codium), operating systems (#windows, #linux, #wsl), embedded (#arduino, #pi), hardware (#kicad, #freecad), processor design (#fpga, #vlsi, https://www.nand2tetris.org/ maybe), sub-atomic-physics (joking), and so much more!

It's often the ancillary stuff, or foundational stuff that gets in the way of learning programming.

@rafetoots This thread made me think: besides learning a programming language in depth, I wonder about your knowledge of version control (#git, #github), editors/IDE's (#codium), operating systems (#windows, #linux, #wsl), embedded (#arduino, #pi), hardware (#kicad, #freecad), processor design (#fpga, #vlsi, https://www.nand2tetris.org/ maybe), sub-atomic-physics (joking), and so much more!

It's often the ancillary stuff, or foundational stuff that gets in the way of learning programming.

Writing a small TCL interpreter to enable TCL in #LunaPnR

Currently it can do fizz-buzz :)

```
set x 1;
while {$x < 100} {
set txt "";
if {$x % 3 == 0} { set txt "FIZZ "; };
if {$x % 5 == 0} { set txt "${txt}BUZZ "; };
puts "$x $txt";
incr x;
}
```

https://www.asicsforthemasses.com #VLSI

Writing a small TCL interpreter to enable TCL in #LunaPnR

Currently it can do fizz-buzz :)

```
set x 1;
while {$x < 100} {
set txt "";
if {$x % 3 == 0} { set txt "FIZZ "; };
if {$x % 5 == 0} { set txt "${txt}BUZZ "; };
puts "$x $txt";
incr x;
}
```

https://www.asicsforthemasses.com #VLSI

This is so much fun
https://tommythorn.github.io/tt08-maxbw/
#ASIC #tinytapeout #AsyncLogic #VLSI #tokenflow

This is so much fun
https://tommythorn.github.io/tt08-maxbw/
#ASIC #tinytapeout #AsyncLogic #VLSI #tokenflow

If you peer into a microscope at a certain #VLSI microprocessor designed and fabricated recently by faculty and graduate students at the #UniversityOfCalifornia at #Berkeley, you will see something quite startling. There, inscribed in tiny detail next to the initials of the microprocessor designers, is a #Porsche racing car. (j m) #RISC #RiscII #Sun #Sparc #Byte #ByteMagazine #Anno1984

You’re using … checks notes … any electronic device? Then you should know Lynn Conway.

#LynnConway #VLSI #RIP

https://www.invent.org/inductees/lynn-conway

Remembering Lynn Conway for her pioneering work leading to VLSI and her personal fight against transgender discrimination

https://hackaday.com/2024/06/14/rip-lynn-conway-whose-work-gave-us-vlsi-and-much-more

https://ai.eecs.umich.edu/people/conway/LynnsStory.html

#VLSI #computerhistory #conway #transgender #ibm #xeroxparc #womenincomputing

RIP Lynn Conway, Whose Work Gave Us VLSI And Much More - Lynn Conway, American engineer and computer scientist, passed away at the age of 8... - https://hackaday.com/2024/06/14/rip-lynn-conway-whose-work-gave-us-vlsi-and-much-more/ #currentevents #originalart #lynnconway #biography #obituary #news #vlsi

RIP Lynn Conway, Whose Work Gave Us VLSI And Much More https://hackaday.com/2024/06/14/rip-lynn-conway-whose-work-gave-us-vlsi-and-much-more/ #CurrentEvents #OriginalArt #LynnConway #Biography #obituary #News #vlsi

Lynn developed "generalized dynamic instruction dispatch" for IBM in 1966. 2 years later she was kicked out, just after Robert Tomasulo published the "Tomasulo Algorithm" for out-of-order execution of floating point instructions, utilizing Lynn's work. Everyone knows Tomasulo (and he did great work, mind you!), but no-one knows Lynn.

Later, in technical compsci, you may stumble upon highly integrated circuits, everyone there knows #VLSI, but not the inventor, our dear Dr. Conway.

Her story, her struggle against IBM who took decades to apologize to her for her mistreatment. She transitioned in darker times and pioneered not "only" in compsci. She was what many would call "greater than life". She died a few days ago.

Today, let's remember Lynn 🏳️‍⚧️, tomorrow we'll fight on ✊

2/2

Without Lynn Conway, there would have been no #VLSI revolution, and maybe ultimately no #semiconductor chip industry at all, in the modern sense in which we understand it.