#cpudesign — Public Fediverse posts
Live and recent posts from across the Fediverse tagged #cpudesign, aggregated by home.social.
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👾 Oh, you designed a CPU in #Verilog for a calculator? How groundbreaking! 🚀 Next, maybe try inventing the wheel in Python while you're at it. 🛞🔄 Spoiler alert: the world already solved this in the 80s. 📟💾
https://github.com/gdevic/FPGA-Calculator #CPUdesign #sarcasm #techhumor #innovation #80sretro #HackerNews #ngated -
RISC-V: Kiến trúc bộ lệnh RISC mở, đơn giản hóa đe dọa ARM/x86 bằng cách:
• Sử dụng nền tảng modun (RV32I/RV64I) + mở rộng tùy chọn (M,A,F,D,C)
• Linh hoạt cho chip nhỏ đến hệ thống Linux đầy đủ
• Hỗ trợ Linux native, lý tưởng cho IoT & phần cứng tùy chỉnh
• Thành công nhờ tiếp cận từng bước & thiết kế bền vững#RISC_V #KiếnTrúcCPU #PhầnCứngMãNguồnMở #OpenSourceHardware #EmbeddedSystems #Linux #IoT #ARM #CPUDesign
https://dev.to/viz-x/risc-v-architecture-how-a-clean-instruction-set-became-a-se
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Designing a CPU with only Memory Chips - Building a simple 8-bit computer is a great way to understand computing fundament... - https://hackaday.com/2025/07/11/designing-a-cpu-with-only-memory-chips/ #retrocomputing #8-bitcomputers #cpudesign #8-bitcpu #eeprom #eprom #cpu
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🐢💻 "Look at us, we built a CPU from scratch and ran a Unix-like OS on it using our homemade C compiler, because apparently reinventing the wheel is the new hipster thing. ☕️🚀 Meanwhile, real software engineers are busy building things that people actually use." 🙄
https://fuel.edby.coffee/posts/how-we-ported-xv6-os-to-a-home-built-cpu-with-a-home-built-c-compiler/ #CPUdesign #UnixlikeOS #homemadeCompiler #hipsterEngineering #softwareDevelopment #HackerNews #ngated -
🐢🎉 Behold! A blog about building a CPU as slow as molasses in January! They’ve successfully made two programs work (cue applause): a pixelated petri dish and a psychedelic mess. But wait, there's more: 🎇The display explodes into random junk if you dare to send data faster than a snail's pace! Clearly, the future of computing is in very safe, albeit very slow, hands. 🐌💻
https://pj5cpu.wordpress.com/ #slowcomputing #CPUdesign #quirkytech #retrocomputing #pixelart #HackerNews #ngated -
After getting a basic ALU design done yesterday & starting a **very** rough start at a microcodeish thing, today the first design of the controlunit & overall cpu design comes together, so it can actually calculate an addition from two arbitary registers and store the result back into a register of choice! :3
Still a lot to go but excited it works already somewhat! #hardware #fantasyconsole #diy #verilog #systemverilog #software #cpudesign #hardwaredesign #fpga #fpgadev
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Baby steps in getting my Apple I reproduction PCB up and running. 6502 CPU booting with just RAM and ROM attached. It grabs the reset address from ROM and starts executing code...until it tries to do something with IO, which is not attached yet...
I'm monitoring the bus with an Arduino MEGA attached to my MacBook Pro.
#cpudesign #retrodev #8bit #16bit #100DaysRTL #DigitalDesign #ElectronicsEngineering #TechInnovation #hardwaredesign #PCBDesign #RetroDev #KiCad #DIYProjects #retrocomputer
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The Ember CPU — Initial Design Part 6: Jumps and Conditional Branches
https://medium.com/the-ember-project/the-ember-cpu-initial-design-part-6-jumps-and-conditional-branches-bfbf7911c80f#homebrew #homebrewconsole #CPU #CPUDesign #FPGA #Emulation #hardware #hardwaredesign #assembly #assembly_language #API #programming #ram #programming #optimization #custom
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Does anyone know if little-endian has any technical advantages? Big-endian machines are all but extinct these days (outside of IBM mainframes).
Or is is just a case of having to pick one and stick with it, like how all life on Earth is made out of L-chiral amino acids and D-chiral carbohydrates?
#bigendian #endianness #chirality #cpu #cpudesign -
Register Renaming: The Art of Parallel Processing https://hackaday.com/2024/11/16/register-renaming-the-art-of-parallel-processing/ #registerrenaming #CPUarchitecture #SoftwareHacks #efficiency #cpudesign #register #task #cpu
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Register Renaming: The Art of Parallel Processing - In the quest for faster computing, modern CPUs have turned to innovative technique... - https://hackaday.com/2024/11/16/register-renaming-the-art-of-parallel-processing/ #registerrenaming #cpuarchitecture #softwarehacks #efficiency #cpudesign #register #task #cpu
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Anyone want to get paid to make a RISC-V course?
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Can someone explain AI coprocessors to me? Like what is the difference to something like AVX over such extra components in the SOCs? #CPUdesign
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Welcome to the world, little one.
Meet the very first Sprout24 CPU, fully assembled tonight for the first time.
25 circuit boards, 2600+ components, 730 LEDs, 1000+ integrated circuits, 9700+ logic gates, and over 29,000 transistors.
She's going to be a thing of poetry when she starts executing code.
I've tested each board individually, but have yet to apply power to the entire thing. I'm not sure I'm ready yet to dare try.
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The ALU hardware tests perfectly against the emulated ALU. The constant register board works too. Next is to test the register controller, and then the complete register file as one unit. #cpudesign #sprout24
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My circuit board order is in!
There's plenty of testing and assembly to do, but if all goes well, these are the 25 boards that are going to make up the complete CPU.
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The last of the circuit boards for my 24-bit CPU are finally in production. Now we wait. There will be a lot of testing to be done once these show up.
Final tally: 25 PCBs. 20" × 9" × 7" total footprint. Very approximately 1000 ICs consisting of 10000 logic gates and 30000 transistors.
That gives a similar transistor count to an Intel 8086 or an early ARM processor. Or around triple the transistor count of an 8-bit Z80 or six times that of a 6502.
There are going to be *so* many blinkenlights.
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I thought I had the bugs with hardware interrupts fixed, but it turns out the fix just hid the problem and it reared its head again with a different set of test programs.
I haven't totally tracked it down, but it's looking like if it's a jump instruction that's interrupted, sometimes the INTRET instruction goes back to the wrong address.
The combination of pipelining and interrupts makes it really hard to trace. I wonder if just masking out IRQs during jump instructions and effectively making them uninterruptible would solve this.
Not the most satisfying solution if it works, but it would save a whole lot of hardware redesign time.
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The simple incrementer/decrementer for the stack pointer looks like it would have been the critical path for the entire CPU, limiting the clock to a theoretical max of about 5Mhz. So I converted it to a carry-lookahead design to make it much more efficient.
I have no idea yet how fast I'll be able to push this CPU in the real world, given the large physical size. But at least I know this part won't be the chokepoint anymore.
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NandGame – Build a Computer from Scratch
Discussions: https://discu.eu/q/https://nandgame.com
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AMD triples Zen 3 CPU cache using 3D stacking technology - This exploded diagram shows a... - https://arstechnica.com/?p=1769062 #3dstacking #cpudesign #l3cache #tech #tsmc #zen3 #zen4 #amd
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IBM creates the world’s first 2 nm chip - This slide from IBM's preview... - https://arstechnica.com/?p=1763407 #cpudesign #tech #ibm
