#tinytapeout — Public Fediverse posts
Live and recent posts from across the Fediverse tagged #tinytapeout, aggregated by home.social.
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Diseño de un transistor MOSFET-N en Magic, con tecnología Sky130 de Skywater. Practicando lo aprendido en el curso #TinyTapeout de @matthewvenn
https://github.com/Obijuan/Learn-open-silicon/wiki/Log -
Bad Apple is back! This time on #TinyTapeout.
I had a video only player on TT07, this version adds audio!
The first minute of Bad Apple fits in the 16MB flash on the QSPI Pmod. -
I say, you should expect more images coming from the #TinyTapeout folks -- I received a whole bunch of dies from them.
Until then, stay safe, stay healthy, and I'll see you next week~
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The shuttle includes various RISC-V SoCs, a "3D" ray caster, a 100Mbps 4-port Ethernet switch and beacon, a dual Core BIO from #Baochip1x, three different #TinyTapeout chips, and much more!
There are also a number of designs that use the new community-created standard cell library, which is both faster and uses less power: a Linux-capable RISC-V SoC with MMU and FABulous FPGA.
Finally, there are new SRAM macros and inductors for validation and characterization, to be used in future runs. -
I received the #TinyTapeout sky25a chip, that has the RISC-V peripheral competition versions of my TinyQV SoC on it.
There’s lots to play with here, and it’s great to see things are working well. Micropython launches at up to 90MHz, which is faster than expected - it’s great to know the default 64MHz clock shouldn’t be pushing the limits.
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I'm doing a beginner TinyTapeout for learning and I'm still struggling to come up with a good idea for my tile. I'm trying to use the Wokwi tool, but I am finding it rather clunky. I might be better off with Verilog, but I haven't used it in years. Some ideas I have had are a digital timer, a quadrature decoder or, as a retro project, a generic C64 DMA controller (I can make this work with the I/O available). So many ideas!
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Por fin he encontrado tiempo para apuntarme al taller de #tinytapeout organizado por Matt Ven. Es el momento de practicar con el diseño de chips reales. ¡Vamos a por el hola mundo en silicio! 😀
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Last week I got some chips backs containing a SKY130 Register File macro I designed from scratch. Basically a 2R1W SRAM macro 32x32.
And so far all the testing I did has been good 🎉
This is far from fully tested, _lots_ to do but still it's very cool to see.
That #tinytapeout chip included several designs using it. One designed for caracterization , but also several "show cases" ones.
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Just listening to The Amp Hour featuring Julia Desmazes.
https://theamphour.com/721-chip-design-for-fun-and-waffles-with-julia-desmazes/
Lots on #hardware / #FPGA / chip design, #tinytapeout, and how to get started.
https://essenceia.github.io/ 👈🧐
So much good stuff to discover!
She uses @archlinux btw. ^^
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Just for fun I've been sort of abusing the differential receiver ( clk + data + deserializer ) project that I had in TT08. It occured to me it should work fine for MIPI-CSI. So I wired a RPi v1 camera to it, and capture the deserialized output with a logic analyzer and I can extract image data out of it 🎉
The RPi camera is 2 lanes and I can only capture one, so I'm missing half the data and there are a lot of hacks to compensate for that but ... it's possible to RX MIPI in #tinytapeout !
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A Tiny FABulous FPGA on Tiny Tapeout? It's more likely than you think!
Yesterday the TTIHP26a shuttle (https://app.tinytapeout.com/shuttles/ttihp26a) from #TinyTapeout has closed. In it, hundreds of incredible projects.
You can view the full shuttle and its designs here: https://app.tinytapeout.com/projects/3744I had the opportunity to submit an FPGA, which I created using my FABulous LibreLane plugin. For this fabric, I developed a "tiny" tile library that better fits the constraints of Tiny Tapeout.
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We now have working #tinytapeout templates for Spade!
For IHP: https://github.com/spade-lang/ttihp-spade-template
For Sky130: https://github.com/spade-lang/ttsky-spade-templateThe IHP shuttle closing in 5 days is full, But! if you are a Swiss resident you can still get on there and get the chip manufactured for free 🇨🇭
This also came with the nice benefit of me finally making swim download the compiler binaries instead of rebuilding for every project, so initial builds of other Spade projects are much faster
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Thank you @tnt for bringing up my TinyQV RISC-V SoC on the most recent #TinyTapeout chips to come back from the fab.
These particular IHP chips are funded by the EU, so sadly due to Brexit they can't be shipped to me - but we were able to get Micropython running, and therefore confirm the design is working pretty well.
Primarily due to better IO pads on the IHP chips, this version runs significantly faster than the previous sky130 tapeout - tnt had it running at 100MHz on one version. The other didn't quite make that, but ran OK at 98MHz - that's quite a bit faster than the 64MHz design frequency!
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4/5 So congratulations to everyone and thanks to #TinyTapeout for making all of this possible!! I would never have imagined doing a (winning) demoscene entry in 2026 on actual ASIC. This is beyond wild. Last I was involved in the demoscene was (iirc) 1999, and I dearly miss these days, TT makes all the fun come back!
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1/5 My two demos, Warp and WhyNot? won 1st place in 'Graphics' (Warp) and 1st place in 'Best for size' and 'Single tile' (WhyNot?) at the #TinyTapeout tt08 demo competition. Huge thanks to the jury for the recognition. This means a lot to me, I started hardware design from scratch in 2018, and this turned into a big adventure.
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Stoked to interview @mithro about https://wafer.space this Tuesday – kicking off a new season of #HacksterCafe ! Learning a bunch about custom, low-cost, #OpenSource #silicon fab... Excited for the updates on last Nov's @crowdsupply campaign, and to see what questions people drop in the chat 👀
We're scheduled later than usual due to time zones. Hope to see you there!
3:30pm Pacific / 6:30pm Eastern / 11:30pm UTC
➡️ https://www.youtube.com/watch?v=HpBEOXHUzHE
➡️ https://www.linkedin.com/events/7426800975115493376 -
How can you fit a retro tunnel effect with a sound track in 161x225 μm of silicon? Checkout my detailed write up on making a demo entry to the #TinyTapeout tt08 competition: https://github.com/sylefeb/tt08-compo-entry/blob/main/docs/info.md
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3/3) You too can make it, it is not easy, but not as hard as you might think,
checkout #TinyTapeout here: -
1/3) Wow, TT08 #TinyTapeout including all demoscene entries landed and I had no clue, imagine my surprise discovering all the fantastic demos (see below, thx bitluni!) on actual hardware. Kudos to all contributors and the team!!
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Finally got the #TinyTapeout 8 ASIC with a couple of my designs on it. When Efabless shut down we thought these chips were lost, but Tiny Tapeout managed to get hold of them and ship them out! This design calculates the Mandelbrot fractal, racing the beam style. It’s clocked at 100MHz.
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It's wild that that is even remotely possible, #tinytapeout is so cool :BlobhajHeart: