#fpga — Public Fediverse posts

Une excellente série de Vidéos par Denis Bodor (rédac-chef de GNU Linux Mag et Hackable) pour découvrir le développement de FPGA sur Linux avec l'environnement open-source LiteX #Hardware #FPGA #Video https://www.youtube.com/playlist?list=PL_rYpDn8wno66GnotlVmF_5i6mNjp3hXh

Zeitlos #FPGA SOC/OS v0.0.1 is released. Now with real screenshots, DHCP, many bug fixes, and an easier installation process. https://github.com/machdyne/zeitlos/

https://youtu.be/0F3pyxdG0kU?is=HVwFPTWQYa615HeB

#OutRunners su mister #fpga una cosa fantastica e gira molto bene . Split screen configurabile. Magari 🤔 uscirà una versione #twin ?
@giochi
Link per scaricare il core e i relativi file : https://www.patreon.com/Meathax/posts/outrunners-1993-167420740#comment-222526597

RE: https://peoplemaking.games/@glairedaggers/117141772040184560

I've also added programming guides which describe the capabilities of the APU and VDP, and how the CPU is intended to operate with them:

https://codeberg.org/GlaireDaggers/GameJimmy-FPGA/src/branch/main/guides

#fpga #retro #misterfpga #fantasyconsole #programming

What a time to be alive :0330: #retro #retrogaming #game #gameing #misterfpga #mister #fpga #outrun #outrunners #splitscreen #sega

Decided to put up a public repository of my WIP new fantasy console, the "GameJimmy" - except it's not just a software emulator, it's a low level FPGA implementation that runs as a MiSTer core! :)

https://codeberg.org/GlaireDaggers/GameJimmy-FPGA

#fpga #retro #misterfpga #retrogaming #fantasyconsole

I haven't had an FPGA build time blow up to times like this since the early 2000's.

I'm going to let it run to see how long it goes.

#FPGA #buildinpublic #electronics

Zeitlos #FPGA SOC/OS development continues.

https://github.com/machdyne/zeitlos

With scroll hardware registers fixed, here’s a demo of draw and display scrolling hardware. #ULX3S #FPGA

Does anyone happen to know anything about the ECP5's undocumented SPI commands?

I've scanned through all possible bytes and found a few commands the system apparently (based on the Invalid Command bit in the device status register) recognizes, but that are not documented in the sysCONFIG User Guide.

• 02, no interesting direct output, probably LSC_WRITE_COMP_DIC?
• 0a, no interesting direct output
• 11, outputs 0a00d0dd on my device
• 16, outputs 41111043 on my device (which is the IDCODE of my device lul, this is also returned by the documented e0 command)
• 19, outputs 00044c61 on my device
• 24, no interesting direct output
• 3a, no interesting direct output
• 42, no interesting direct output
• 47, no interesting direct output
• 67, no interesting direct output
• 70, no interesting direct output
• 72, no interesting direct output
• 72, no interesting direct output
• 73, outputs 00000000 on my device
• 7d, no interesting direct output
• 80, outputs 00000000 on my device
• 9c, no interesting direct output
• 9d, no interesting direct output
• 9e, outputs 00ffffff on my device
• 9e, outputs 20ffffff on my device
• b0, outputs 00000000 on my device
• b2, no interesting direct output, maybe LSC_EBR_WRITE???
• c9, no interesting direct output
• ca, no interesting direct output
• cb, no interesting direct output
• cf, no interesting direct output
• e2, no interesting direct output, but sets the ID Error bit in the device status register, so it is just undocumented for SPI, but is actually the VERIFY_ID command
• e8, outputs 00000000 on my device
• f6, no interesting direct output, maybe LSC_EBR_ADDRESS???
• f7, outputs 00ffffff on my device
• f8, no interesting direct output

If anyone knows what any of these commands do or might do, please please please let me know :3

Alrighty, soooooo:

It's actually possible to "talk" directly to the configuration engine using Slave SPI Mode (set MASTER_SPI_PORT=DISABLE SLAVE_SPI_PORT=ENABLE in your constraints) and simply using D0/MOSI/IO0 as MOSI, D1/MISO/IO1 as MISO, and SN/CSN as CS. The clock is a bit more difficult, since you cannot directly use it as an I/O port. However, it is possible to instantiate the USRMCLK primitive, feed your clock into USRMCLKI and set USRMCLKTS to 0.

This basically allows communicating with the config engine using the SPI commands specified in section 6.2.3 of ECP5 and ECP5-5G sysCONFIG User Guide.

Sadly, when the device is in user mode (i.e. actually running your logic), the config engine only allows read commands (except for LSC_PROG_CTRL0 for some odd reason) and you cannot use this to partially reconfigure the device :(

The configuration bitstream contains optional Slave SPI persistence bits. When the device completes configuration and wakes up, it checks the persistent bits to determine if the Slave SPI port is to remain operational once in user mode. This selection is independent of the CFGMDN pin setting. A port enabled by persistence is capable of reading commands only. Thus, the port is a Background Mode port and is not a configuration port, and can only be used for read back operations.

This is really, really sad.

My next idea is to try the Slave Serial Configuration Mode or Slave Parallel Mode, which does not have a restriction depending on the FPGA mode documented, but might still have one.

New #Atari2600 FPGA core for MISTer with ARM ROMs support https://github.com/lroby74/Atari2600_ARM_MiSTer/releases/tag/RBF #atari #fpga

Homebrew 68K Machine Has A PCI Bus

https://fed.brid.gy/r/https://hackaday.com/2026/08/20/homebrew-68k-machine-has-a-pci-bus/

Busy week. The Zeitlos #FPGA SOC/OS can now telnet to https://bbs.machdyne.com.

https://github.com/machdyne/zeitlos

The Retro Shack Asks About the Future of Retro Computing
#RetroComputing #VintageComputing #TheRetroShack #Commodore64 #Amiga #ZXSpectrum #FPGA #Emulation #VintageComputers #ComputerHistory
https://theoasisbbs.com/the-retro-shack-asks-about-the-future-of-retro-computing/?fsp_sid=12000

SPI-контроллер на FPGA: переносим на Zynq 7000. Часть 2

Продолжаем разработку SPI IP Core на Verilog. В первой части мы перенесли SPI-контроллер с Altera Cyclone IV на Zynq-7020, сохранили исходный регистровый интерфейс и добавили AXI4-Lite. Теперь задача меняется: нужно превратить работающий RTL в полноценное устройство под Linux. Во второй части соберем Block Design с PS, настроим карту адресов и прерывания, подготовим загрузочную цепочку и Device Tree, а затем подключим контроллер к стандартной SPI subsystem Linux. Здесь уже недостаточно рабочего bitstream: ошибка в ps7_init , адресах или Device Tree может сделать исправное ядро недоступным для ОС. После обычного PIO-доступа добавим потоковый тракт для больших объемов данных. Для этого появятся AXI-Stream адаптер, глубокий FIFO, backpressure и режим TX-only. По ходу разберем ошибки, которые проявляются только под нагрузкой: потерю байтов на границе FIFO, проблемы запуска DMA и устаревший результат синтеза. Финал этой части - плата самостоятельно загружает Linux, SPI работает через драйвер, а большие буферы передаются из DDR в PL через AXI DMA без побайтового участия Cortex-A9. Всем, кому интересно продолжение - добро пожаловать под кат! =)

https://habr.com/ru/companies/beget/articles/1069720/

#fpga #spi_controller #linux #buildroot #driver #dts #lcd #dma #verilog #axi

@lethalbit protocompiler for haps 80 is no longer available or even maintained for paid support so you'll have issues finding it.

#electronics #fpga

New Zeitlos #FPGA SOC/OS features:

- Window manager
- Object-based interprocess messaging/streaming
- Networking (IP/ICMP/ARP/UDP/TFTP)

https://github.com/machdyne/zeitlos