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#vhdl — Public Fediverse posts

Live and recent posts from across the Fediverse tagged #vhdl, aggregated by home.social.

  1. Klaus Frank @[email protected] ·

    What do you think, how well will trying to #vibecode #VHDL go?

    It sounds so dumb that I kinda want to try it out now*...

    * and maybe I will once I find some AI company claiming they can do it which probably doesn't take long AND where I don't have to pay anything.

    #vibecode #vhdl
  2. Klaus Frank @[email protected] ·

    What do you think, how well will trying to #vibecode #VHDL go?

    It sounds so dumb that I kinda want to try it out now*...

    * and maybe I will once I find some AI company claiming they can do it which probably doesn't take long AND where I don't have to pay anything.

    #vibecode #vhdl
  3. Klaus Frank @[email protected] ·

    What do you think, how well will trying to #vibecode #VHDL go?

    It sounds so dumb that I kinda want to try it out now*...

    * and maybe I will once I find some AI company claiming they can do it which probably doesn't take long AND where I don't have to pay anything.

    #vibecode #vhdl
  4. Klaus Frank @[email protected] ·

    What do you think, how well will trying to #vibecode #VHDL go?

    It sounds so dumb that I kinda want to try it out now*...

    * and maybe I will once I find some AI company claiming they can do it which probably doesn't take long AND where I don't have to pay anything.

    #vibecode #vhdl
  5. JCM @[email protected] ·

    Fully initialized!!! :D

    (the screenshot only shows the responses from the SD card, because I am too lazy to write proper UART)


    #FPGA #VHDL #HDL #Icepi-Zero #these-two-additional-steps-were-surpringly-light-on-my-state-machine
    #fpga #vhdl #hdl #icepizero #thesetwoadditionalstepsweresurpringlylightonmystatemachine
  6. JCM @[email protected] ·

    Fully initialized!!! :D

    (the screenshot only shows the responses from the SD card, because I am too lazy to write proper UART)


    #FPGA #VHDL #HDL #Icepi-Zero #these-two-additional-steps-were-surpringly-light-on-my-state-machine
    #fpga #vhdl #hdl #icepizero #thesetwoadditionalstepsweresurpringlylightonmystatemachine
  7. JCM @[email protected] ·

    OMGGGG, first few steps of SD card initalization work!!!


    #this-one-probably-wins-the-price-of-the-worst-ever-state-machine-I-wrote #it's-basically-two-different-state-machines-frankensteined-together #VHDL #HDL #Icepi-Zero #FPGA
    #thisoneprobablywinsthepriceoftheworsteverstatemachineiwrote #itsbasicallytwodifferentstatemachinesfrankensteinedtogether #vhdl #hdl #icepizero #fpga
  8. JCM @[email protected] ·

    OMGGGG, first few steps of SD card initalization work!!!


    #this-one-probably-wins-the-price-of-the-worst-ever-state-machine-I-wrote #it's-basically-two-different-state-machines-frankensteined-together #VHDL #HDL #Icepi-Zero #FPGA
    #thisoneprobablywinsthepriceoftheworsteverstatemachineiwrote #itsbasicallytwodifferentstatemachinesfrankensteinedtogether #vhdl #hdl #icepizero #fpga
  9. Paul Förster :verified_blue: @[email protected] ·

    I found this #VIC20 project repository on #GitHub for the #MEGA65. The xpr files in the CORE directory of the repository seem to be #Xilinx project files. Lacking know how and resources, I can’t turn these into core files for the MEGA 65.

    Could some kind soul please do that and upload the core files? I’d love to have a VIC-20 core for the MEGA 65. 🙏

    github.com/MJoergen/VIC20MEGA65

    #Commodore #Emulation #VHDL

    #vic20 #github #mega65 #xilinx #commodore #emulation
  10. Paul Förster :verified_blue: @[email protected] ·

    I found this #VIC20 project repository on #GitHub for the #MEGA65. The xpr files in the CORE directory of the repository seem to be #Xilinx project files. Lacking know how and resources, I can’t turn these into core files for the MEGA 65.

    Could some kind soul please do that and upload the core files? I’d love to have a VIC-20 core for the MEGA 65. 🙏

    github.com/MJoergen/VIC20MEGA65

    #Commodore #Emulation #VHDL

    #vic20 #github #mega65 #xilinx #commodore #emulation
  11. Paul Förster :verified_blue: @[email protected] ·

    I found this #VIC20 project repository on #GitHub for the #MEGA65. The xpr files in the CORE directory of the repository seem to be #Xilinx project files. Lacking know how and resources, I can’t turn these into core files for the MEGA 65.

    Could some kind soul please do that and upload the core files? I’d love to have a VIC-20 core for the MEGA 65. 🙏

    github.com/MJoergen/VIC20MEGA65

    #Commodore #Emulation #VHDL

    #vic20 #github #mega65 #xilinx #commodore #emulation
  12. Paul Förster :verified_blue: @[email protected] ·

    I found this #VIC20 project repository on #GitHub for the #MEGA65. The xpr files in the CORE directory of the repository seem to be #Xilinx project files. Lacking know how and resources, I can’t turn these into core files for the MEGA 65.

    Could some kind soul please do that and upload the core files? I’d love to have a VIC-20 core for the MEGA 65. 🙏

    github.com/MJoergen/VIC20MEGA65

    #Commodore #Emulation #VHDL

    #vhdl #emulation #commodore #xilinx #mega65 #github
  13. Paul Förster :verified_blue: @[email protected] ·

    I found this #VIC20 project repository on #GitHub for the #MEGA65. The xpr files in the CORE directory of the repository seem to be #Xilinx project files. Lacking know how and resources, I can’t turn these into core files for the MEGA 65.

    Could some kind soul please do that and upload the core files? I’d love to have a VIC-20 core for the MEGA 65. 🙏

    github.com/MJoergen/VIC20MEGA65

    #Commodore #Emulation #VHDL

    #vic20 #github #mega65 #xilinx #commodore #emulation
  14. JCM @[email protected] ·

    God, it's so difficult for me to start working on a new component (SD card interface) for my FPGA project, because either I need to:

    a) write tons of test benches to test everything in simulation (and then still have no guarantee it will work in real life)
    b) write a top level module that allows me to (partially) debug it in hardware, which will also be a pain
    c) hope and pray that everything will magically work first try

    I always struggle so much when the first difficulty I need to overcome is such a big/annoying one. It makes me not wanna even start working on it.

    I've had the same with software (looking at you, Vulkan), but hardware makes it even more difficult for me…


    #FPGA #hardware #VHDL #HDL
    #fpga #hardware #vhdl #hdl
  15. JCM @[email protected] ·

    God, it's so difficult for me to start working on a new component (SD card interface) for my FPGA project, because either I need to:

    a) write tons of test benches to test everything in simulation (and then still have no guarantee it will work in real life)
    b) write a top level module that allows me to (partially) debug it in hardware, which will also be a pain
    c) hope and pray that everything will magically work first try

    I always struggle so much when the first difficulty I need to overcome is such a big/annoying one. It makes me not wanna even start working on it.

    I've had the same with software (looking at you, Vulkan), but hardware makes it even more difficult for me…


    #FPGA #hardware #VHDL #HDL
    #fpga #hardware #vhdl #hdl
  16. Samuel Torres @[email protected] ·

    I thought I could skip the Vivado simulation and just flash my VHDL code onto the board.

    Lesson learned: when doing an FPGA project, a quick simulation catches bugs that hardware implementation will otherwise scream at you. Run the simulation, save hours, keep the client smiling. ⚙️
    avallancer.com/services/vhdl-f

    #FPGA #VHDL #Simulation #HardwareDebug

    #hardwaredebug #simulation #vhdl #fpga
  17. Vladimir Vargas Cordero 🇨🇷 🙏🪷 @vladimirvc ·

    ELM11-Feather Is a Feather-Compatible Board That Speaks Lua Natively

    itsfoss.com/news/elm11-feather

    #fpga #lua #vhdl
  18. Vladimir Vargas Cordero 🇨🇷 🙏🪷 @[email protected] ·

    ELM11-Feather Is a Feather-Compatible Board That Speaks Lua Natively
    #fpga #lua #vhdl
    itsfoss.com/news/elm11-feather

    #fpga #lua #vhdl
  19. Vladimir Vargas Cordero 🇨🇷 🙏🪷 @[email protected] ·

    ELM11-Feather Is a Feather-Compatible Board That Speaks Lua Natively
    #fpga #lua #vhdl
    itsfoss.com/news/elm11-feather

    #fpga #lua #vhdl
  20. Pawel @wozniakpawel ·

    I built a browser IDE that runs real open-source EDA tools. Write VHDL or SystemVerilog, hit run: GHDL/Icarus simulates it, Yosys synthesizes it, and you see the waveform and the netlist cell by cell. No install.

    Free fundamentals curriculum + engineering-flavored challenges, and a playground.

    risingedge.pro/

    #fpga #vhdl #verilog
  21. cnx-software.com [Unofficial] @[email protected] ·

    Lua-programmable ELM11-Feather board puts Gowin GW1NR FPGA into Feather form factor (Crowdfunding)

    fed.brid.gy/r/https://www.cnx-

    #bouffalolab #gowinsemiconductor #hardware #video #cc #crowdsupply
  22. JCM @[email protected] ·

    Managed to go from

    Info:                   DP16KD:       0/     56     0%
Info:               MULT18X18D:       1/     28     3%
Info:               TRELLIS_FF:    1612/  24288     6%
Info:             TRELLIS_COMB:    5705/  24288    23%
Info: Max frequency for clock '$glbnet$main_clk': 25.20 MHz (PASS at 25.00 MHz)

    to

    Info:                   DP16KD:       1/     56     1%
Info:               MULT18X18D:       1/     28     3%
Info:               TRELLIS_FF:     515/  24288     2%
Info:             TRELLIS_COMB:    2480/  24288    10%
Info: Max frequency for clock '$glbnet$main_clk': 57.34 MHz (PASS at 25.00 MHz)

    by replacing my hacky register-based string templating solution with a (still hacky) RAM-based one and by setting ranges on all my integer.

    Feels good~



    RE: https://wafrn.jcm.re/fediverse/post/627f72e6-73a3-415e-b5a7-88dbeb959b1a
    #vhdl #icepi-zero #fpga #hdl #hardware-development #this-is-gonna-be-so-incredibly-cursed-in-the-end-xD
    #vhdl #icepizero #fpga #hdl #hardwaredevelopment #thisisgonnabesoincrediblycursedintheendxd
  23. JCM @[email protected] ·

    Managed to go from

    Info:                   DP16KD:       0/     56     0%
Info:               MULT18X18D:       1/     28     3%
Info:               TRELLIS_FF:    1612/  24288     6%
Info:             TRELLIS_COMB:    5705/  24288    23%
Info: Max frequency for clock '$glbnet$main_clk': 25.20 MHz (PASS at 25.00 MHz)

    to

    Info:                   DP16KD:       1/     56     1%
Info:               MULT18X18D:       1/     28     3%
Info:               TRELLIS_FF:     515/  24288     2%
Info:             TRELLIS_COMB:    2480/  24288    10%
Info: Max frequency for clock '$glbnet$main_clk': 57.34 MHz (PASS at 25.00 MHz)

    by replacing my hacky register-based string templating solution with a (still hacky) RAM-based one and by setting ranges on all my integer.

    Feels good~



    RE: https://wafrn.jcm.re/fediverse/post/627f72e6-73a3-415e-b5a7-88dbeb959b1a
    #vhdl #icepi-zero #fpga #hdl #hardware-development #this-is-gonna-be-so-incredibly-cursed-in-the-end-xD
    #vhdl #icepizero #fpga #hdl #hardwaredevelopment #thisisgonnabesoincrediblycursedintheendxd
  24. Open Source Electronics Wiki @[email protected] ·

    Which Verilog TMDS encoding library do you recommend that I use on the Ice Pi Zero? Here is my review of the options.

    wiki.pythonlinks.info/dvi-rtl-

    #Verilog #VHDL #tMDS #IcePiZero

    #verilog #vhdl #tmds #icepizero
  25. Open Source Electronics Wiki @[email protected] ·

    Which Verilog TMDS encoding library do you recommend that I use on the Ice Pi Zero? Here is my review of the options.

    wiki.pythonlinks.info/dvi-rtl-

    #Verilog #VHDL #tMDS #IcePiZero

    #verilog #vhdl #tmds #icepizero
  26. Open Source Electronics Wiki @[email protected] ·

    Which Verilog TMDS encoding library do you recommend that I use on the Ice Pi Zero? Here is my review of the options.

    wiki.pythonlinks.info/dvi-rtl-

    #Verilog #VHDL #tMDS #IcePiZero

    #icepizero #tmds #vhdl #verilog
  27. Icepi Zero Bot @[email protected] ·

    @[email protected] asked

    library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1'); uart_data : out std_logic_vector(7 downto 0) := (others => '0'); uart_ready : in std_logic; uart_valid : out std_logic := '0' ); end my_code; architecture rtl of my_code is alias red : std_logic_vector(7 downto 0) is background_color(23 downto 16); alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8); alias blue : std_logic_vector(7 downto 0) is background_color(7 downto 0); signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant example_text : string := "Hello Fediverse! <3"; constant example_text_row : integer := 15; constant example_text_col : integer := 15; constant uart_text : string := "Hello Fediverse on UART!" & LF; begin char <= character'pos(example_text(col + 1 - example_text_col)) when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0; red <= std_logic_vector(to_unsigned(col*4, 8)) xor std_logic_vector(resize(frame_counter, 8)); green <= std_logic_vector(to_unsigned(py, 8)) xor std_logic_vector(to_unsigned(px, 8)); blue <= std_logic_vector(resize(frame_counter, 8)); foreground_color <= (others => '1'); process(clk) variable old_vsync : std_logic := '0'; variable uart_counter : integer range uart_text'range := 1; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then frame_counter <= frame_counter + 1; end if; old_vsync := vsync; uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8)); uart_valid <= '1'; if uart_ready = '1' and uart_valid = '1' then if uart_counter < uart_text'length then uart_counter := uart_counter + 1; else uart_counter := 1; end if; end if; end if; end process; end architecture;

    Success!

    UART Output

    ... [TRUNCATED] ...
llo Fediverse on UART!
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Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
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Hello Fediverse on UART!
Hello Fediverse on UART!
He


    UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1178242884.9%TRELLIS_FF176242880.7%TRELLIS_IO111975.6%
    TimingClockAchievedConstraint$glbnet$clkp40.37 MHz25 MHz$glbnet$clkt285.63 MHz250 MHz
    Code

    library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1');

        uart_data : out std_logic_vector(7 downto 0) := (others => '0');
        uart_ready : in std_logic;
        uart_valid : out std_logic := '0'
    );
end my_code;

architecture rtl of my_code is
    alias red   : std_logic_vector(7 downto 0) is background_color(23 downto 16);
    alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8);
    alias blue  : std_logic_vector(7 downto 0) is background_color(7 downto 0);

    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant example_text : string := "Hello Fediverse! <3";
    constant example_text_row : integer := 15;
    constant example_text_col : integer := 15;

    constant uart_text : string := "Hello Fediverse on UART!" & LF;
begin
    char <= character'pos(example_text(col + 1 - example_text_col))
        when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0;

    red   <= std_logic_vector(to_unsigned(col*4, 8)) xor std_logic_vector(resize(frame_counter, 8));
    green <= std_logic_vector(to_unsigned(py, 8)) xor std_logic_vector(to_unsigned(px, 8));
    blue  <= std_logic_vector(resize(frame_counter, 8));

    foreground_color <= (others => '1');

    process(clk)
        variable old_vsync : std_logic := '0';

        variable uart_counter : integer range uart_text'range := 1;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                frame_counter <= frame_counter + 1;
            end if;
            old_vsync := vsync;

            uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8));
            uart_valid <= '1';
            if uart_ready = '1' and uart_valid = '1' then
                if uart_counter < uart_text'length then
                    uart_counter := uart_counter + 1;
                else
                    uart_counter := 1;
                end if;
            end if;
        end if;
    end process;
end architecture;


    #FPGA #Icepi-Zero #HDL #VHDL
    #fpga #icepizero #hdl #vhdl
  28. Icepi Zero Bot @[email protected] ·

    @[email protected] asked

    library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1'); uart_data : out std_logic_vector(7 downto 0) := (others => '0'); uart_ready : in std_logic; uart_valid : out std_logic := '0' ); end my_code; architecture rtl of my_code is alias red : std_logic_vector(7 downto 0) is background_color(23 downto 16); alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8); alias blue : std_logic_vector(7 downto 0) is background_color(7 downto 0); signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant example_text : string := "Hello Fediverse! <3"; constant example_text_row : integer := 15; constant example_text_col : integer := 15; constant uart_text : string := "Hello Fediverse on UART!" & LF; begin char <= character'pos(example_text(col + 1 - example_text_col)) when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0; red <= std_logic_vector(to_unsigned(col*4, 8)) xor std_logic_vector(resize(frame_counter, 8)); green <= std_logic_vector(to_unsigned(py, 8)) xor std_logic_vector(to_unsigned(px, 8)); blue <= std_logic_vector(resize(frame_counter, 8)); foreground_color <= (others => '1'); process(clk) variable old_vsync : std_logic := '0'; variable uart_counter : integer range uart_text'range := 1; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then frame_counter <= frame_counter + 1; end if; old_vsync := vsync; uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8)); uart_valid <= '1'; if uart_ready = '1' and uart_valid = '1' then if uart_counter < uart_text'length then uart_counter := uart_counter + 1; else uart_counter := 1; end if; end if; end if; end process; end architecture;

    Success!

    UART Output

    ... [TRUNCATED] ...
llo Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
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He


    UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1178242884.9%TRELLIS_FF176242880.7%TRELLIS_IO111975.6%
    TimingClockAchievedConstraint$glbnet$clkp40.37 MHz25 MHz$glbnet$clkt285.63 MHz250 MHz
    Code

    library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1');

        uart_data : out std_logic_vector(7 downto 0) := (others => '0');
        uart_ready : in std_logic;
        uart_valid : out std_logic := '0'
    );
end my_code;

architecture rtl of my_code is
    alias red   : std_logic_vector(7 downto 0) is background_color(23 downto 16);
    alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8);
    alias blue  : std_logic_vector(7 downto 0) is background_color(7 downto 0);

    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant example_text : string := "Hello Fediverse! <3";
    constant example_text_row : integer := 15;
    constant example_text_col : integer := 15;

    constant uart_text : string := "Hello Fediverse on UART!" & LF;
begin
    char <= character'pos(example_text(col + 1 - example_text_col))
        when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0;

    red   <= std_logic_vector(to_unsigned(col*4, 8)) xor std_logic_vector(resize(frame_counter, 8));
    green <= std_logic_vector(to_unsigned(py, 8)) xor std_logic_vector(to_unsigned(px, 8));
    blue  <= std_logic_vector(resize(frame_counter, 8));

    foreground_color <= (others => '1');

    process(clk)
        variable old_vsync : std_logic := '0';

        variable uart_counter : integer range uart_text'range := 1;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                frame_counter <= frame_counter + 1;
            end if;
            old_vsync := vsync;

            uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8));
            uart_valid <= '1';
            if uart_ready = '1' and uart_valid = '1' then
                if uart_counter < uart_text'length then
                    uart_counter := uart_counter + 1;
                else
                    uart_counter := 1;
                end if;
            end if;
        end if;
    end process;
end architecture;


    #FPGA #Icepi-Zero #HDL #VHDL
    #fpga #icepizero #hdl #vhdl
  29. Icepi Zero Bot @[email protected] ·

    @[email protected] asked

    library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1'); uart_data : out std_logic_vector(7 downto 0) := (others => '0'); uart_ready : in std_logic; uart_valid : out std_logic := '0' ); end my_code; architecture rtl of my_code is alias red : std_logic_vector(7 downto 0) is background_color(23 downto 16); alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8); alias blue : std_logic_vector(7 downto 0) is background_color(7 downto 0); signal frame_counter : unsigned(31 downto 0) := (others => '0'); signal example_text : string(1 to 13) := "temp = ???? C"; constant example_text_row : integer := 15; constant example_text_col : integer := 15; type temperature_map_t is array (0 to 63) of string(1 to 4); constant temperature_map : temperature_map_t := ( 0 => " -58", 1 => " -56", 2 => " -54", 3 => " -52", 4 => " -45", 5 => " -44", 6 => " -43", 7 => " -42", 8 => " -41", 9 => " -40", 10 => "- 39", 11 => "- 38", 12 => "- 37", 13 => "- 36", 14 => "- 30", 15 => "- 20", 16 => "- 10", 17 => "- 4", 18 => " 0", 19 => "+ 4", 20 => "+ 10", 21 => "+ 21", 22 => "+ 22", 23 => "+ 23", 24 => "+ 24", 25 => "+ 25", 26 => "+ 26", 27 => "+ 27", 28 => "+ 28", 29 => "+ 29", 30 => "+ 40", 31 => "+ 50", 32 => "+ 60", 33 => "+ 70", 34 => "+ 76", 35 => "+ 80", 36 => "+ 81", 37 => "+ 82", 38 => "+ 83", 39 => "+ 84", 40 => "+ 85", 41 => "+ 86", 42 => "+ 87", 43 => "+ 88", 44 => "+ 89", 45 => "+ 95", 46 => "+ 96", 47 => "+ 97", 48 => "+ 98", 49 => "+ 99", 50 => "+100", 51 => "+101", 52 => "+102", 53 => "+103", 54 => "+104", 55 => "+105", 56 => "+106", 57 => "+107", 58 => "+108", 59 => "+116", 60 => "+120", 61 => "+124", 62 => "+128", 63 => "+132" ); component DTR is port ( STARTPULSE : in std_logic; DTROUT7 : out std_logic; DTROUT6 : out std_logic; DTROUT5 : out std_logic; DTROUT4 : out std_logic; DTROUT3 : out std_logic; DTROUT2 : out std_logic; DTROUT1 : out std_logic; DTROUT0 : out std_logic ); end component; signal temp : unsigned(5 downto 0) := (others => '0'); signal startpulse : std_logic := '0'; begin char <= character'pos(example_text(col + 1 - example_text_col)) when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0; red <= std_logic_vector(to_unsigned(col*4, 8)); green <= std_logic_vector(to_unsigned(py, 8)); blue <= std_logic_vector(resize(frame_counter, 8)); foreground_color <= (others => '1'); dtr_inst: DTR port map ( STARTPULSE => startpulse, DTROUT7 => open, DTROUT6 => open, DTROUT5 => temp(5), DTROUT4 => temp(4), DTROUT3 => temp(3), DTROUT2 => temp(2), DTROUT1 => temp(1), DTROUT0 => temp(0) ); example_text(8 to 11) <= temperature_map(to_integer(temp)); process(clk) variable old_vsync : std_logic := '0'; begin if rising_edge(clk) then startpulse <= '0'; if vsync = '0' and old_vsync = '1' then frame_counter <= frame_counter + 1; startpulse <= '1'; end if; old_vsync := vsync; end if; end process; end architecture;

    Success!

    UART Output


    UtilizationCellUsedAvailableUsageDCCA2563.6%DTR11100.0%EHXPLLL1250.0%TRELLIS_COMB1238242885.1%TRELLIS_FF158242880.7%TRELLIS_IO111975.6%
    TimingClockAchievedConstraint$glbnet$clkp40.71 MHz25 MHz$glbnet$clkt319.69 MHz250 MHz
    Code

    library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1');

        uart_data : out std_logic_vector(7 downto 0) := (others => '0');
        uart_ready : in std_logic;
        uart_valid : out std_logic := '0'
    );
end my_code;

architecture rtl of my_code is
    alias red   : std_logic_vector(7 downto 0) is background_color(23 downto 16);
    alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8);
    alias blue  : std_logic_vector(7 downto 0) is background_color(7 downto 0);

    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    signal example_text : string(1 to 13) := "temp = ???? C";
    constant example_text_row : integer := 15;
    constant example_text_col : integer := 15;

    type temperature_map_t is array (0 to 63) of string(1 to 4);
    constant temperature_map : temperature_map_t := (
        0 =>  " -58",
        1 =>  " -56",
        2 =>  " -54",
        3 =>  " -52",
        4 =>  " -45",
        5 =>  " -44",
        6 =>  " -43",
        7 =>  " -42",
        8 =>  " -41",
        9 =>  " -40",
        10 => "- 39",
        11 => "- 38",
        12 => "- 37",
        13 => "- 36",
        14 => "- 30",
        15 => "- 20",
        16 => "- 10",
        17 => "-  4",
        18 => "   0",
        19 => "+  4",
        20 => "+ 10",
        21 => "+ 21",
        22 => "+ 22",
        23 => "+ 23",
        24 => "+ 24",
        25 => "+ 25",
        26 => "+ 26",
        27 => "+ 27",
        28 => "+ 28",
        29 => "+ 29",
        30 => "+ 40",
        31 => "+ 50",
        32 => "+ 60",
        33 => "+ 70",
        34 => "+ 76",
        35 => "+ 80",
        36 => "+ 81",
        37 => "+ 82",
        38 => "+ 83",
        39 => "+ 84",
        40 => "+ 85",
        41 => "+ 86",
        42 => "+ 87",
        43 => "+ 88",
        44 => "+ 89",
        45 => "+ 95",
        46 => "+ 96",
        47 => "+ 97",
        48 => "+ 98",
        49 => "+ 99",
        50 => "+100",
        51 => "+101",
        52 => "+102",
        53 => "+103",
        54 => "+104",
        55 => "+105",
        56 => "+106",
        57 => "+107",
        58 => "+108",
        59 => "+116",
        60 => "+120",
        61 => "+124",
        62 => "+128",
        63 => "+132"
    );

    component DTR is
        port (
            STARTPULSE : in std_logic;
            DTROUT7 : out std_logic;
            DTROUT6 : out std_logic;
            DTROUT5 : out std_logic;
            DTROUT4 : out std_logic;
            DTROUT3 : out std_logic;
            DTROUT2 : out std_logic;
            DTROUT1 : out std_logic;
            DTROUT0 : out std_logic
        );
    end component;
    signal temp : unsigned(5 downto 0) := (others => '0');
    signal startpulse : std_logic := '0';
begin
    char <= character'pos(example_text(col + 1 - example_text_col))
        when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0;

    red   <= std_logic_vector(to_unsigned(col*4, 8));
    green <= std_logic_vector(to_unsigned(py, 8));
    blue  <= std_logic_vector(resize(frame_counter, 8));

    foreground_color <= (others => '1');

    dtr_inst: DTR
        port map (
            STARTPULSE => startpulse,
            DTROUT7 => open,
            DTROUT6 => open,
            DTROUT5 => temp(5),
            DTROUT4 => temp(4),
            DTROUT3 => temp(3),
            DTROUT2 => temp(2),
            DTROUT1 => temp(1),
            DTROUT0 => temp(0)
        );
    example_text(8 to 11) <= temperature_map(to_integer(temp));

    process(clk)
        variable old_vsync : std_logic := '0';
    begin
        if rising_edge(clk) then
            startpulse <= '0';
            if vsync = '0' and old_vsync = '1' then
                frame_counter <= frame_counter + 1;
                startpulse <= '1';
            end if;
            old_vsync := vsync;
        end if;
    end process;
end architecture;


    #FPGA #Icepi-Zero #HDL #VHDL
    #fpga #icepizero #hdl #vhdl
  30. Icepi Zero Bot @[email protected] ·

    @[email protected] asked

    library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1'); uart_data : out std_logic_vector(7 downto 0) := (others => '0'); uart_ready : in std_logic; uart_valid : out std_logic := '0' ); end my_code; architecture rtl of my_code is alias red : std_logic_vector(7 downto 0) is background_color(23 downto 16); alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8); alias blue : std_logic_vector(7 downto 0) is background_color(7 downto 0); signal frame_counter : unsigned(31 downto 0) := (others => '0'); signal example_text : string(1 to 13) := "temp = ???? C"; constant example_text_row : integer := 15; constant example_text_col : integer := 15; type temperature_map_t is array (0 to 63) of string(1 to 4); constant temperature_map : temperature_map_t := ( 0 => " -58", 1 => " -56", 2 => " -54", 3 => " -52", 4 => " -45", 5 => " -44", 6 => " -43", 7 => " -42", 8 => " -41", 9 => " -40", 10 => "- 39", 11 => "- 38", 12 => "- 37", 13 => "- 36", 14 => "- 30", 15 => "- 20", 16 => "- 10", 17 => "- 4", 18 => " 0", 19 => "+ 4", 20 => "+ 10", 21 => "+ 21", 22 => "+ 22", 23 => "+ 23", 24 => "+ 24", 25 => "+ 25", 26 => "+ 26", 27 => "+ 27", 28 => "+ 28", 29 => "+ 29", 30 => "+ 40", 31 => "+ 50", 32 => "+ 60", 33 => "+ 70", 34 => "+ 76", 35 => "+ 80", 36 => "+ 81", 37 => "+ 82", 38 => "+ 83", 39 => "+ 84", 40 => "+ 85", 41 => "+ 86", 42 => "+ 87", 43 => "+ 88", 44 => "+ 89", 45 => "+ 95", 46 => "+ 96", 47 => "+ 97", 48 => "+ 98", 49 => "+ 99", 50 => "+100", 51 => "+101", 52 => "+102", 53 => "+103", 54 => "+104", 55 => "+105", 56 => "+106", 57 => "+107", 58 => "+108", 59 => "+116", 60 => "+120", 61 => "+124", 62 => "+128", 63 => "+132" ); component DTR is port ( STARTPULSE : in std_logic; DTROUT7 : out std_logic; DTROUT6 : out std_logic; DTROUT5 : out std_logic; DTROUT4 : out std_logic; DTROUT3 : out std_logic; DTROUT2 : out std_logic; DTROUT1 : out std_logic; DTROUT0 : out std_logic ); end component; signal temp : unsigned(5 downto 0) := (others => '0'); signal startpulse : std_logic := '0'; begin char <= character'pos(example_text(col + 1 - example_text_col)) when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0; red <= std_logic_vector(to_unsigned(col*4, 8)); green <= std_logic_vector(to_unsigned(py, 8)); blue <= std_logic_vector(resize(frame_counter, 8)); foreground_color <= (others => '1'); dtr_inst: DTR port map ( STARTPULSE => startpulse, DTROUT7 => open, DTROUT6 => open, DTROUT5 => temp(5), DTROUT4 => temp(4), DTROUT3 => temp(3), DTROUT2 => temp(2), DTROUT1 => temp(1), DTROUT0 => temp(0) ); example_text(8 to 11) <= temperature_map(to_integer(temp)); process(clk) variable old_vsync : std_logic := '0'; begin if rising_edge(clk) then startpulse <= '0'; if vsync = '0' and old_vsync = '1' then frame_counter <= frame_counter + 1; startpulse <= '1'; end if; old_vsync := vsync; end if; end process; end architecture;

    Success!

    UART Output


    UtilizationCellUsedAvailableUsageDCCA2563.6%DTR11100.0%EHXPLLL1250.0%TRELLIS_COMB1238242885.1%TRELLIS_FF158242880.7%TRELLIS_IO111975.6%
    TimingClockAchievedConstraint$glbnet$clkp40.71 MHz25 MHz$glbnet$clkt319.69 MHz250 MHz
    Code

    library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1');

        uart_data : out std_logic_vector(7 downto 0) := (others => '0');
        uart_ready : in std_logic;
        uart_valid : out std_logic := '0'
    );
end my_code;

architecture rtl of my_code is
    alias red   : std_logic_vector(7 downto 0) is background_color(23 downto 16);
    alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8);
    alias blue  : std_logic_vector(7 downto 0) is background_color(7 downto 0);

    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    signal example_text : string(1 to 13) := "temp = ???? C";
    constant example_text_row : integer := 15;
    constant example_text_col : integer := 15;

    type temperature_map_t is array (0 to 63) of string(1 to 4);
    constant temperature_map : temperature_map_t := (
        0 =>  " -58",
        1 =>  " -56",
        2 =>  " -54",
        3 =>  " -52",
        4 =>  " -45",
        5 =>  " -44",
        6 =>  " -43",
        7 =>  " -42",
        8 =>  " -41",
        9 =>  " -40",
        10 => "- 39",
        11 => "- 38",
        12 => "- 37",
        13 => "- 36",
        14 => "- 30",
        15 => "- 20",
        16 => "- 10",
        17 => "-  4",
        18 => "   0",
        19 => "+  4",
        20 => "+ 10",
        21 => "+ 21",
        22 => "+ 22",
        23 => "+ 23",
        24 => "+ 24",
        25 => "+ 25",
        26 => "+ 26",
        27 => "+ 27",
        28 => "+ 28",
        29 => "+ 29",
        30 => "+ 40",
        31 => "+ 50",
        32 => "+ 60",
        33 => "+ 70",
        34 => "+ 76",
        35 => "+ 80",
        36 => "+ 81",
        37 => "+ 82",
        38 => "+ 83",
        39 => "+ 84",
        40 => "+ 85",
        41 => "+ 86",
        42 => "+ 87",
        43 => "+ 88",
        44 => "+ 89",
        45 => "+ 95",
        46 => "+ 96",
        47 => "+ 97",
        48 => "+ 98",
        49 => "+ 99",
        50 => "+100",
        51 => "+101",
        52 => "+102",
        53 => "+103",
        54 => "+104",
        55 => "+105",
        56 => "+106",
        57 => "+107",
        58 => "+108",
        59 => "+116",
        60 => "+120",
        61 => "+124",
        62 => "+128",
        63 => "+132"
    );

    component DTR is
        port (
            STARTPULSE : in std_logic;
            DTROUT7 : out std_logic;
            DTROUT6 : out std_logic;
            DTROUT5 : out std_logic;
            DTROUT4 : out std_logic;
            DTROUT3 : out std_logic;
            DTROUT2 : out std_logic;
            DTROUT1 : out std_logic;
            DTROUT0 : out std_logic
        );
    end component;
    signal temp : unsigned(5 downto 0) := (others => '0');
    signal startpulse : std_logic := '0';
begin
    char <= character'pos(example_text(col + 1 - example_text_col))
        when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0;

    red   <= std_logic_vector(to_unsigned(col*4, 8));
    green <= std_logic_vector(to_unsigned(py, 8));
    blue  <= std_logic_vector(resize(frame_counter, 8));

    foreground_color <= (others => '1');

    dtr_inst: DTR
        port map (
            STARTPULSE => startpulse,
            DTROUT7 => open,
            DTROUT6 => open,
            DTROUT5 => temp(5),
            DTROUT4 => temp(4),
            DTROUT3 => temp(3),
            DTROUT2 => temp(2),
            DTROUT1 => temp(1),
            DTROUT0 => temp(0)
        );
    example_text(8 to 11) <= temperature_map(to_integer(temp));

    process(clk)
        variable old_vsync : std_logic := '0';
    begin
        if rising_edge(clk) then
            startpulse <= '0';
            if vsync = '0' and old_vsync = '1' then
                frame_counter <= frame_counter + 1;
                startpulse <= '1';
            end if;
            old_vsync := vsync;
        end if;
    end process;
end architecture;


    #FPGA #Icepi-Zero #HDL #VHDL
    #fpga #icepizero #hdl #vhdl
  31. Icepi Zero Bot @[email protected] ·

    @[email protected] asked

    library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1'); uart_data : out std_logic_vector(7 downto 0) := (others => '0'); uart_ready : in std_logic; uart_valid : out std_logic := '0' ); end my_code; architecture rtl of my_code is constant IMAGE_WIDTH : integer := 32; constant IMAGE_HEIGHT : integer := 25; type image_type is array (IMAGE_HEIGHT*IMAGE_WIDTH*12-1 downto 0) of std_logic; constant image : image_type := x"00000000000000000000000000000000000000000000000123400000000000111200000000000000000000000000000000000000000000000000000000000000000000000000044645700000000022344700000000000000000000000000000000000000000000000000000000000000000000000000056845700100000033556800100000000000000000000000000000000000000000000000000000000000000000000000145744611100000034555800000000000000000000000000000000000000000000000000000000000000000000000000033533522423422444633500011075364300000000000000000000000000000000000000000000000000000000000000012334568979b457345123000964eb7da73211100000000000000000000000000000000000000000000000000000000003448abaddadd8ab79a578211c86fa7fa7c86c867430000000000000000000000000000000000000000000000000000005788bcaddadd8ab8ab689777eddebae96f96f9696400000000000000000000000000000000000000000000000011122289a89a9cdadd9aaabb79a777cccca9d85d85b643100000000000000000000000000000000000000000000002217657659aaabcacdaddbcdbcd7ab456888866754532210000000000000000000000000000000000000000000000000332765765789acdadeaddadd9cd58923444522200000011133333300000000000000000000000000000000000000000011154377688978a9bcacd9cc7ac7ad347000000433999bbbddcaaa0000000000000000000000000000000000000000001223443452235679bcabc9bc9ab68b46a124444bbbeddeedddd7770000000000000000000000000000000000000005679bd7ac78b769678cdddeecddacc7ae47a567888cccdddccc8881110000000000001110000000000003333331111115668ab69b89c88a668bcddeecee9bc67b56a99bcccaaa999555111111000000555aaacccbbb333222777eeeeeeccccdddddbbb445abceefeffeeeeeeeeedeedeeddebbcbbcdddeeebbbbbbcccbbb666dddeffdeffffdddccceeedefbdfeffdefbeffff999cccdefadfbefcefdefcefbefbefdeeeefadfbefffffffcefeffcccfffadf4cfdeffffdefeffbdf4cfadf3cf3cfbefeeedddbdf3bf3cf4cf6cf3cf5cf4cf7cfcef4cf4cfdefdff5cfbefdddcccdef3cf9dfdef4cfbdf9df4cf7cf3cf4cf6cfefffffadf4cfadfcef9df4cfdefadf2bf9df4cf3cf8cfdef4cfcefccd888fff9df3bf9cf3af7bf6af5af5af7bfadf3afadffff8cf2bf3bfcefadf3bfadf8cf3bfbdf4bf9cf5bf7bf3afdefbbb444ddddef48f37f47f37f26f58f37f57fbcf89f47fcdf79f79fbdfeffbcf38f6af49f38fabf48fbcf9af27f37feefaaa000aaafff79f37fbcf57f37f8af37f68fccfddf57f89f58f9bfffffffbcf37fddfddf47f57f47fbcfddf37f47ffff999000344eeeddfbcfeffddfcdfdefabfeefffffffdefeefddfeefddeccdddf9afeeffffddfddfddfeeffffbcfbcffff77800000099aeeeeeeddeddeddeeeeeefdee89abbcddeccdddddde99a99aeeffffeefdddeeeddeddeccdcddeeefffddd45600000022456866845745745755767956822423544723534645723433477978a679446567457446346346568679558112"; constant SPEED : integer := 8; signal position_x : integer range -SPEED to WIDTH + SPEED := 0; signal position_y : integer range -SPEED to HEIGHT + SPEED := 0; signal random_bit : std_logic := '0'; signal color : std_logic_vector(23 downto 0) := x"FFFFFF"; component OSCG is generic ( DIV : integer := 128 ); port ( OSC : out std_logic ); end component; signal pos : integer range 0 to IMAGE_HEIGHT*IMAGE_WIDTH*12; signal r, g, b : std_logic_vector(3 downto 0); begin char <= 0; pos <= IMAGE_HEIGHT*IMAGE_WIDTH*12 - 1 - 12*(py - position_y)*(px - position_x); r <= image(pos) & image(pos - 1) & image(pos - 2) & image(pos - 3); g <= image(pos - 4) & image(pos - 5) & image(pos - 6) & image(pos - 7); b <= image(pos - 8) & image(pos - 9) & image(pos - 10) & image(pos - 11); background_color <= r & r & g & g & b & b when px >= position_x and px < position_x + IMAGE_WIDTH and py >= position_y and py < position_y + IMAGE_HEIGHT else x"000000"; foreground_color <= (others => '1'); rng : OSCG port map ( OSC => random_bit ); process(clk) variable old_vsync : std_logic := '0'; variable speed_x : integer range -SPEED to SPEED := SPEED; variable speed_y : integer range -SPEED to SPEED := SPEED; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then if position_x + speed_x + IMAGE_WIDTH >= WIDTH then speed_x := -SPEED; position_x <= WIDTH - IMAGE_WIDTH - 1; color <= color(22 downto 0) & random_bit; elsif position_x + speed_x < 0 then speed_x := SPEED; position_x <= 0; color <= color(22 downto 0) & random_bit; else position_x <= position_x + speed_x; end if; if position_y + speed_y + IMAGE_HEIGHT >= HEIGHT then speed_y := -SPEED; position_y <= HEIGHT - IMAGE_HEIGHT - 1; color <= color(22 downto 0) & random_bit; elsif position_y + speed_y < 0 then speed_y := SPEED; position_y <= 0; color <= color(22 downto 0) & random_bit; else position_y <= position_y + speed_y; end if; end if; old_vsync := vsync; end if; end process; end architecture;

    Success!

    UART Output


    UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%MULT18X18D2287.1%TRELLIS_COMB29372428812.1%TRELLIS_FF160242880.7%TRELLIS_IO111975.6%
    TimingClockAchievedConstraint$glbnet$clkp30.03 MHz25 MHz$glbnet$clkt341.41 MHz250 MHz
    Code

    library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1');

        uart_data : out std_logic_vector(7 downto 0) := (others => '0');
        uart_ready : in std_logic;
        uart_valid : out std_logic := '0'
    );
end my_code;

architecture rtl of my_code is
    constant IMAGE_WIDTH : integer := 32;
    constant IMAGE_HEIGHT : integer := 25;

    type image_type is array (IMAGE_HEIGHT*IMAGE_WIDTH*12-1 downto 0) of std_logic;
    constant image : image_type := x"00000000000000000000000000000000000000000000000123400000000000111200000000000000000000000000000000000000000000000000000000000000000000000000044645700000000022344700000000000000000000000000000000000000000000000000000000000000000000000000056845700100000033556800100000000000000000000000000000000000000000000000000000000000000000000000145744611100000034555800000000000000000000000000000000000000000000000000000000000000000000000000033533522423422444633500011075364300000000000000000000000000000000000000000000000000000000000000012334568979b457345123000964eb7da73211100000000000000000000000000000000000000000000000000000000003448abaddadd8ab79a578211c86fa7fa7c86c867430000000000000000000000000000000000000000000000000000005788bcaddadd8ab8ab689777eddebae96f96f9696400000000000000000000000000000000000000000000000011122289a89a9cdadd9aaabb79a777cccca9d85d85b643100000000000000000000000000000000000000000000002217657659aaabcacdaddbcdbcd7ab456888866754532210000000000000000000000000000000000000000000000000332765765789acdadeaddadd9cd58923444522200000011133333300000000000000000000000000000000000000000011154377688978a9bcacd9cc7ac7ad347000000433999bbbddcaaa0000000000000000000000000000000000000000001223443452235679bcabc9bc9ab68b46a124444bbbeddeedddd7770000000000000000000000000000000000000005679bd7ac78b769678cdddeecddacc7ae47a567888cccdddccc8881110000000000001110000000000003333331111115668ab69b89c88a668bcddeecee9bc67b56a99bcccaaa999555111111000000555aaacccbbb333222777eeeeeeccccdddddbbb445abceefeffeeeeeeeeedeedeeddebbcbbcdddeeebbbbbbcccbbb666dddeffdeffffdddccceeedefbdfeffdefbeffff999cccdefadfbefcefdefcefbefbefdeeeefadfbefffffffcefeffcccfffadf4cfdeffffdefeffbdf4cfadf3cf3cfbefeeedddbdf3bf3cf4cf6cf3cf5cf4cf7cfcef4cf4cfdefdff5cfbefdddcccdef3cf9dfdef4cfbdf9df4cf7cf3cf4cf6cfefffffadf4cfadfcef9df4cfdefadf2bf9df4cf3cf8cfdef4cfcefccd888fff9df3bf9cf3af7bf6af5af5af7bfadf3afadffff8cf2bf3bfcefadf3bfadf8cf3bfbdf4bf9cf5bf7bf3afdefbbb444ddddef48f37f47f37f26f58f37f57fbcf89f47fcdf79f79fbdfeffbcf38f6af49f38fabf48fbcf9af27f37feefaaa000aaafff79f37fbcf57f37f8af37f68fccfddf57f89f58f9bfffffffbcf37fddfddf47f57f47fbcfddf37f47ffff999000344eeeddfbcfeffddfcdfdefabfeefffffffdefeefddfeefddeccdddf9afeeffffddfddfddfeeffffbcfbcffff77800000099aeeeeeeddeddeddeeeeeefdee89abbcddeccdddddde99a99aeeffffeefdddeeeddeddeccdcddeeefffddd45600000022456866845745745755767956822423544723534645723433477978a679446567457446346346568679558112";

    constant SPEED : integer := 8;

    signal position_x : integer range -SPEED to WIDTH + SPEED := 0;
    signal position_y : integer range -SPEED to HEIGHT + SPEED := 0;

    signal random_bit : std_logic := '0';
    signal color : std_logic_vector(23 downto 0) := x"FFFFFF";

    component OSCG is
        generic (
            DIV : integer := 128
        );
        port (
            OSC : out std_logic
        );
    end component;

    signal pos : integer range 0 to IMAGE_HEIGHT*IMAGE_WIDTH*12;
    signal r, g, b : std_logic_vector(3 downto 0);
begin
    char <= 0;

    pos <= IMAGE_HEIGHT*IMAGE_WIDTH*12 - 1 - 12*(py - position_y)*(px - position_x);
    r <= image(pos) & image(pos - 1) & image(pos - 2) & image(pos - 3);
    g <= image(pos - 4) & image(pos - 5) & image(pos - 6) & image(pos - 7);
    b <= image(pos - 8) & image(pos - 9) & image(pos - 10) & image(pos - 11);

    background_color <= r & r & g & g & b & b
        when
            px >= position_x and px < position_x + IMAGE_WIDTH and
            py >= position_y and py < position_y + IMAGE_HEIGHT
        else x"000000";
    foreground_color <= (others => '1');

    rng : OSCG port map (
        OSC => random_bit
    );

    process(clk)
        variable old_vsync : std_logic := '0';
        variable speed_x : integer range -SPEED to SPEED := SPEED;
        variable speed_y : integer range -SPEED to SPEED := SPEED;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                if position_x + speed_x + IMAGE_WIDTH >= WIDTH then
                    speed_x := -SPEED;
                    position_x <= WIDTH - IMAGE_WIDTH - 1;

                    color <= color(22 downto 0) & random_bit;
                elsif position_x + speed_x < 0 then
                    speed_x := SPEED;
                    position_x <= 0;

                    color <= color(22 downto 0) & random_bit;
                else
                    position_x <= position_x + speed_x;
                end if;

                if position_y + speed_y + IMAGE_HEIGHT >= HEIGHT then
                    speed_y := -SPEED;
                    position_y <= HEIGHT - IMAGE_HEIGHT - 1;

                    color <= color(22 downto 0) & random_bit;
                elsif position_y + speed_y < 0 then
                    speed_y := SPEED;
                    position_y <= 0;

                    color <= color(22 downto 0) & random_bit;
                else
                    position_y <= position_y + speed_y;
                end if;
            end if;
            old_vsync := vsync;
        end if;
    end process;
end architecture;


    #FPGA #Icepi-Zero #HDL #VHDL
    #fpga #icepizero #hdl #vhdl
  32. Icepi Zero Bot @[email protected] ·

    @[email protected] asked

    library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1'); uart_data : out std_logic_vector(7 downto 0) := (others => '0'); uart_ready : in std_logic; uart_valid : out std_logic := '0' ); end my_code; architecture rtl of my_code is constant IMAGE_WIDTH : integer := 32; constant IMAGE_HEIGHT : integer := 25; type image_type is array (IMAGE_HEIGHT*IMAGE_WIDTH*12-1 downto 0) of std_logic; constant image : image_type := x"00000000000000000000000000000000000000000000000123400000000000111200000000000000000000000000000000000000000000000000000000000000000000000000044645700000000022344700000000000000000000000000000000000000000000000000000000000000000000000000056845700100000033556800100000000000000000000000000000000000000000000000000000000000000000000000145744611100000034555800000000000000000000000000000000000000000000000000000000000000000000000000033533522423422444633500011075364300000000000000000000000000000000000000000000000000000000000000012334568979b457345123000964eb7da73211100000000000000000000000000000000000000000000000000000000003448abaddadd8ab79a578211c86fa7fa7c86c867430000000000000000000000000000000000000000000000000000005788bcaddadd8ab8ab689777eddebae96f96f9696400000000000000000000000000000000000000000000000011122289a89a9cdadd9aaabb79a777cccca9d85d85b643100000000000000000000000000000000000000000000002217657659aaabcacdaddbcdbcd7ab456888866754532210000000000000000000000000000000000000000000000000332765765789acdadeaddadd9cd58923444522200000011133333300000000000000000000000000000000000000000011154377688978a9bcacd9cc7ac7ad347000000433999bbbddcaaa0000000000000000000000000000000000000000001223443452235679bcabc9bc9ab68b46a124444bbbeddeedddd7770000000000000000000000000000000000000005679bd7ac78b769678cdddeecddacc7ae47a567888cccdddccc8881110000000000001110000000000003333331111115668ab69b89c88a668bcddeecee9bc67b56a99bcccaaa999555111111000000555aaacccbbb333222777eeeeeeccccdddddbbb445abceefeffeeeeeeeeedeedeeddebbcbbcdddeeebbbbbbcccbbb666dddeffdeffffdddccceeedefbdfeffdefbeffff999cccdefadfbefcefdefcefbefbefdeeeefadfbefffffffcefeffcccfffadf4cfdeffffdefeffbdf4cfadf3cf3cfbefeeedddbdf3bf3cf4cf6cf3cf5cf4cf7cfcef4cf4cfdefdff5cfbefdddcccdef3cf9dfdef4cfbdf9df4cf7cf3cf4cf6cfefffffadf4cfadfcef9df4cfdefadf2bf9df4cf3cf8cfdef4cfcefccd888fff9df3bf9cf3af7bf6af5af5af7bfadf3afadffff8cf2bf3bfcefadf3bfadf8cf3bfbdf4bf9cf5bf7bf3afdefbbb444ddddef48f37f47f37f26f58f37f57fbcf89f47fcdf79f79fbdfeffbcf38f6af49f38fabf48fbcf9af27f37feefaaa000aaafff79f37fbcf57f37f8af37f68fccfddf57f89f58f9bfffffffbcf37fddfddf47f57f47fbcfddf37f47ffff999000344eeeddfbcfeffddfcdfdefabfeefffffffdefeefddfeefddeccdddf9afeeffffddfddfddfeeffffbcfbcffff77800000099aeeeeeeddeddeddeeeeeefdee89abbcddeccdddddde99a99aeeffffeefdddeeeddeddeccdcddeeefffddd45600000022456866845745745755767956822423544723534645723433477978a679446567457446346346568679558112"; constant SPEED : integer := 8; signal position_x : integer range -SPEED to WIDTH + SPEED := 0; signal position_y : integer range -SPEED to HEIGHT + SPEED := 0; signal random_bit : std_logic := '0'; signal color : std_logic_vector(23 downto 0) := x"FFFFFF"; component OSCG is generic ( DIV : integer := 128 ); port ( OSC : out std_logic ); end component; signal pos : integer range 0 to IMAGE_HEIGHT*IMAGE_WIDTH*12; signal r, g, b : std_logic_vector(3 downto 0); begin char <= 0; pos <= IMAGE_HEIGHT*IMAGE_WIDTH*12 - 1 - 12*(py - position_y)*(px - position_x); r <= image(pos) & image(pos - 1) & image(pos - 2) & image(pos - 3); g <= image(pos - 4) & image(pos - 5) & image(pos - 6) & image(pos - 7); b <= image(pos - 8) & image(pos - 9) & image(pos - 10) & image(pos - 11); background_color <= r & r & g & g & b & b when px >= position_x and px < position_x + IMAGE_WIDTH and py >= position_y and py < position_y + IMAGE_HEIGHT else x"000000"; foreground_color <= (others => '1'); rng : OSCG port map ( OSC => random_bit ); process(clk) variable old_vsync : std_logic := '0'; variable speed_x : integer range -SPEED to SPEED := SPEED; variable speed_y : integer range -SPEED to SPEED := SPEED; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then if position_x + speed_x + IMAGE_WIDTH >= WIDTH then speed_x := -SPEED; position_x <= WIDTH - IMAGE_WIDTH - 1; color <= color(22 downto 0) & random_bit; elsif position_x + speed_x < 0 then speed_x := SPEED; position_x <= 0; color <= color(22 downto 0) & random_bit; else position_x <= position_x + speed_x; end if; if position_y + speed_y + IMAGE_HEIGHT >= HEIGHT then speed_y := -SPEED; position_y <= HEIGHT - IMAGE_HEIGHT - 1; color <= color(22 downto 0) & random_bit; elsif position_y + speed_y < 0 then speed_y := SPEED; position_y <= 0; color <= color(22 downto 0) & random_bit; else position_y <= position_y + speed_y; end if; end if; old_vsync := vsync; end if; end process; end architecture;

    Success!

    UART Output


    UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%MULT18X18D2287.1%TRELLIS_COMB29372428812.1%TRELLIS_FF160242880.7%TRELLIS_IO111975.6%
    TimingClockAchievedConstraint$glbnet$clkp30.03 MHz25 MHz$glbnet$clkt341.41 MHz250 MHz
    Code

    library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1');

        uart_data : out std_logic_vector(7 downto 0) := (others => '0');
        uart_ready : in std_logic;
        uart_valid : out std_logic := '0'
    );
end my_code;

architecture rtl of my_code is
    constant IMAGE_WIDTH : integer := 32;
    constant IMAGE_HEIGHT : integer := 25;

    type image_type is array (IMAGE_HEIGHT*IMAGE_WIDTH*12-1 downto 0) of std_logic;
    constant image : image_type := x"00000000000000000000000000000000000000000000000123400000000000111200000000000000000000000000000000000000000000000000000000000000000000000000044645700000000022344700000000000000000000000000000000000000000000000000000000000000000000000000056845700100000033556800100000000000000000000000000000000000000000000000000000000000000000000000145744611100000034555800000000000000000000000000000000000000000000000000000000000000000000000000033533522423422444633500011075364300000000000000000000000000000000000000000000000000000000000000012334568979b457345123000964eb7da73211100000000000000000000000000000000000000000000000000000000003448abaddadd8ab79a578211c86fa7fa7c86c867430000000000000000000000000000000000000000000000000000005788bcaddadd8ab8ab689777eddebae96f96f9696400000000000000000000000000000000000000000000000011122289a89a9cdadd9aaabb79a777cccca9d85d85b643100000000000000000000000000000000000000000000002217657659aaabcacdaddbcdbcd7ab456888866754532210000000000000000000000000000000000000000000000000332765765789acdadeaddadd9cd58923444522200000011133333300000000000000000000000000000000000000000011154377688978a9bcacd9cc7ac7ad347000000433999bbbddcaaa0000000000000000000000000000000000000000001223443452235679bcabc9bc9ab68b46a124444bbbeddeedddd7770000000000000000000000000000000000000005679bd7ac78b769678cdddeecddacc7ae47a567888cccdddccc8881110000000000001110000000000003333331111115668ab69b89c88a668bcddeecee9bc67b56a99bcccaaa999555111111000000555aaacccbbb333222777eeeeeeccccdddddbbb445abceefeffeeeeeeeeedeedeeddebbcbbcdddeeebbbbbbcccbbb666dddeffdeffffdddccceeedefbdfeffdefbeffff999cccdefadfbefcefdefcefbefbefdeeeefadfbefffffffcefeffcccfffadf4cfdeffffdefeffbdf4cfadf3cf3cfbefeeedddbdf3bf3cf4cf6cf3cf5cf4cf7cfcef4cf4cfdefdff5cfbefdddcccdef3cf9dfdef4cfbdf9df4cf7cf3cf4cf6cfefffffadf4cfadfcef9df4cfdefadf2bf9df4cf3cf8cfdef4cfcefccd888fff9df3bf9cf3af7bf6af5af5af7bfadf3afadffff8cf2bf3bfcefadf3bfadf8cf3bfbdf4bf9cf5bf7bf3afdefbbb444ddddef48f37f47f37f26f58f37f57fbcf89f47fcdf79f79fbdfeffbcf38f6af49f38fabf48fbcf9af27f37feefaaa000aaafff79f37fbcf57f37f8af37f68fccfddf57f89f58f9bfffffffbcf37fddfddf47f57f47fbcfddf37f47ffff999000344eeeddfbcfeffddfcdfdefabfeefffffffdefeefddfeefddeccdddf9afeeffffddfddfddfeeffffbcfbcffff77800000099aeeeeeeddeddeddeeeeeefdee89abbcddeccdddddde99a99aeeffffeefdddeeeddeddeccdcddeeefffddd45600000022456866845745745755767956822423544723534645723433477978a679446567457446346346568679558112";

    constant SPEED : integer := 8;

    signal position_x : integer range -SPEED to WIDTH + SPEED := 0;
    signal position_y : integer range -SPEED to HEIGHT + SPEED := 0;

    signal random_bit : std_logic := '0';
    signal color : std_logic_vector(23 downto 0) := x"FFFFFF";

    component OSCG is
        generic (
            DIV : integer := 128
        );
        port (
            OSC : out std_logic
        );
    end component;

    signal pos : integer range 0 to IMAGE_HEIGHT*IMAGE_WIDTH*12;
    signal r, g, b : std_logic_vector(3 downto 0);
begin
    char <= 0;

    pos <= IMAGE_HEIGHT*IMAGE_WIDTH*12 - 1 - 12*(py - position_y)*(px - position_x);
    r <= image(pos) & image(pos - 1) & image(pos - 2) & image(pos - 3);
    g <= image(pos - 4) & image(pos - 5) & image(pos - 6) & image(pos - 7);
    b <= image(pos - 8) & image(pos - 9) & image(pos - 10) & image(pos - 11);

    background_color <= r & r & g & g & b & b
        when
            px >= position_x and px < position_x + IMAGE_WIDTH and
            py >= position_y and py < position_y + IMAGE_HEIGHT
        else x"000000";
    foreground_color <= (others => '1');

    rng : OSCG port map (
        OSC => random_bit
    );

    process(clk)
        variable old_vsync : std_logic := '0';
        variable speed_x : integer range -SPEED to SPEED := SPEED;
        variable speed_y : integer range -SPEED to SPEED := SPEED;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                if position_x + speed_x + IMAGE_WIDTH >= WIDTH then
                    speed_x := -SPEED;
                    position_x <= WIDTH - IMAGE_WIDTH - 1;

                    color <= color(22 downto 0) & random_bit;
                elsif position_x + speed_x < 0 then
                    speed_x := SPEED;
                    position_x <= 0;

                    color <= color(22 downto 0) & random_bit;
                else
                    position_x <= position_x + speed_x;
                end if;

                if position_y + speed_y + IMAGE_HEIGHT >= HEIGHT then
                    speed_y := -SPEED;
                    position_y <= HEIGHT - IMAGE_HEIGHT - 1;

                    color <= color(22 downto 0) & random_bit;
                elsif position_y + speed_y < 0 then
                    speed_y := SPEED;
                    position_y <= 0;

                    color <= color(22 downto 0) & random_bit;
                else
                    position_y <= position_y + speed_y;
                end if;
            end if;
            old_vsync := vsync;
        end if;
    end process;
end architecture;


    #FPGA #Icepi-Zero #HDL #VHDL
    #fpga #icepizero #hdl #vhdl
  33. Icepi Zero Bot @[email protected] ·

    @[email protected] asked

    library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1'); uart_data : out std_logic_vector(7 downto 0) := (others => '0'); uart_ready : in std_logic; uart_valid : out std_logic := '0' ); end my_code; architecture rtl of my_code is constant IMAGE_WIDTH : integer := 32; constant IMAGE_HEIGHT : integer := 25; type image_type is array (IMAGE_HEIGHT*IMAGE_WIDTH*12-1 downto 0) of std_logic; constant image : image_type := x"00000000000000000000000000000000000000000000000123400000000000111200000000000000000000000000000000000000000000000000000000000000000000000000044645700000000022344700000000000000000000000000000000000000000000000000000000000000000000000000056845700100000033556800100000000000000000000000000000000000000000000000000000000000000000000000145744611100000034555800000000000000000000000000000000000000000000000000000000000000000000000000033533522423422444633500011075364300000000000000000000000000000000000000000000000000000000000000012334568979b457345123000964eb7da73211100000000000000000000000000000000000000000000000000000000003448abaddadd8ab79a578211c86fa7fa7c86c867430000000000000000000000000000000000000000000000000000005788bcaddadd8ab8ab689777eddebae96f96f9696400000000000000000000000000000000000000000000000011122289a89a9cdadd9aaabb79a777cccca9d85d85b643100000000000000000000000000000000000000000000002217657659aaabcacdaddbcdbcd7ab456888866754532210000000000000000000000000000000000000000000000000332765765789acdadeaddadd9cd58923444522200000011133333300000000000000000000000000000000000000000011154377688978a9bcacd9cc7ac7ad347000000433999bbbddcaaa0000000000000000000000000000000000000000001223443452235679bcabc9bc9ab68b46a124444bbbeddeedddd7770000000000000000000000000000000000000005679bd7ac78b769678cdddeecddacc7ae47a567888cccdddccc8881110000000000001110000000000003333331111115668ab69b89c88a668bcddeecee9bc67b56a99bcccaaa999555111111000000555aaacccbbb333222777eeeeeeccccdddddbbb445abceefeffeeeeeeeeedeedeeddebbcbbcdddeeebbbbbbcccbbb666dddeffdeffffdddccceeedefbdfeffdefbeffff999cccdefadfbefcefdefcefbefbefdeeeefadfbefffffffcefeffcccfffadf4cfdeffffdefeffbdf4cfadf3cf3cfbefeeedddbdf3bf3cf4cf6cf3cf5cf4cf7cfcef4cf4cfdefdff5cfbefdddcccdef3cf9dfdef4cfbdf9df4cf7cf3cf4cf6cfefffffadf4cfadfcef9df4cfdefadf2bf9df4cf3cf8cfdef4cfcefccd888fff9df3bf9cf3af7bf6af5af5af7bfadf3afadffff8cf2bf3bfcefadf3bfadf8cf3bfbdf4bf9cf5bf7bf3afdefbbb444ddddef48f37f47f37f26f58f37f57fbcf89f47fcdf79f79fbdfeffbcf38f6af49f38fabf48fbcf9af27f37feefaaa000aaafff79f37fbcf57f37f8af37f68fccfddf57f89f58f9bfffffffbcf37fddfddf47f57f47fbcfddf37f47ffff999000344eeeddfbcfeffddfcdfdefabfeefffffffdefeefddfeefddeccdddf9afeeffffddfddfddfeeffffbcfbcffff77800000099aeeeeeeddeddeddeeeeeefdee89abbcddeccdddddde99a99aeeffffeefdddeeeddeddeccdcddeeefffddd45600000022456866845745745755767956822423544723534645723433477978a679446567457446346346568679558112"; constant SPEED : integer := 8; signal position_x : integer range -SPEED to WIDTH + SPEED := 0; signal position_y : integer range -SPEED to HEIGHT + SPEED := 0; signal random_bit : std_logic := '0'; signal color : std_logic_vector(23 downto 0) := x"FFFFFF"; component OSCG is generic ( DIV : integer := 128 ); port ( OSC : out std_logic ); end component; signal pos : integer range 0 to IMAGE_HEIGHT*IMAGE_WIDTH*12; signal r, g, b : std_logic_vector(3 downto 0); begin char <= 0; pos <= IMAGE_HEIGHT*IMAGE_WIDTH*12 - 1 - 12*(py - position_y)*(px - position_x); r <= image(pos) & image(pos - 1) & image(pos - 2) & image(pos - 3); g <= image(pos - 4) & image(pos - 5) & image(pos - 6) & image(pos - 7); b <= image(pos - 8) & image(pos - 9) & image(pos - 10) & image(pos - 11); background_color <= r & r & g & g & b & b when px >= position_x and px < position_x + IMAGE_WIDTH and py >= position_y and py < position_y + IMAGE_HEIGHT else x"000000"; foreground_color <= (others => '1'); rng : OSCG port map ( OSC => random_bit ); process(clk) variable old_vsync : std_logic := '0'; variable speed_x : integer range -SPEED to SPEED := SPEED; variable speed_y : integer range -SPEED to SPEED := SPEED; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then if position_x + speed_x + IMAGE_WIDTH >= WIDTH then speed_x := -SPEED; position_x <= WIDTH - IMAGE_WIDTH - 1; color <= color(22 downto 0) & random_bit; elsif position_x + speed_x < 0 then speed_x := SPEED; position_x <= 0; color <= color(22 downto 0) & random_bit; else position_x <= position_x + speed_x; end if; if position_y + speed_y + IMAGE_HEIGHT >= HEIGHT then speed_y := -SPEED; position_y <= HEIGHT - IMAGE_HEIGHT - 1; color <= color(22 downto 0) & random_bit; elsif position_y + speed_y < 0 then speed_y := SPEED; position_y <= 0; color <= color(22 downto 0) & random_bit; else position_y <= position_y + speed_y; end if; end if; old_vsync := vsync; end if; end process; end architecture;

    Success!

    UART Output


    UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%MULT18X18D2287.1%TRELLIS_COMB29372428812.1%TRELLIS_FF160242880.7%TRELLIS_IO111975.6%
    TimingClockAchievedConstraint$glbnet$clkp30.03 MHz25 MHz$glbnet$clkt341.41 MHz250 MHz
    Code

    library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1');

        uart_data : out std_logic_vector(7 downto 0) := (others => '0');
        uart_ready : in std_logic;
        uart_valid : out std_logic := '0'
    );
end my_code;

architecture rtl of my_code is
    constant IMAGE_WIDTH : integer := 32;
    constant IMAGE_HEIGHT : integer := 25;

    type image_type is array (IMAGE_HEIGHT*IMAGE_WIDTH*12-1 downto 0) of std_logic;
    constant image : image_type := x"00000000000000000000000000000000000000000000000123400000000000111200000000000000000000000000000000000000000000000000000000000000000000000000044645700000000022344700000000000000000000000000000000000000000000000000000000000000000000000000056845700100000033556800100000000000000000000000000000000000000000000000000000000000000000000000145744611100000034555800000000000000000000000000000000000000000000000000000000000000000000000000033533522423422444633500011075364300000000000000000000000000000000000000000000000000000000000000012334568979b457345123000964eb7da73211100000000000000000000000000000000000000000000000000000000003448abaddadd8ab79a578211c86fa7fa7c86c867430000000000000000000000000000000000000000000000000000005788bcaddadd8ab8ab689777eddebae96f96f9696400000000000000000000000000000000000000000000000011122289a89a9cdadd9aaabb79a777cccca9d85d85b643100000000000000000000000000000000000000000000002217657659aaabcacdaddbcdbcd7ab456888866754532210000000000000000000000000000000000000000000000000332765765789acdadeaddadd9cd58923444522200000011133333300000000000000000000000000000000000000000011154377688978a9bcacd9cc7ac7ad347000000433999bbbddcaaa0000000000000000000000000000000000000000001223443452235679bcabc9bc9ab68b46a124444bbbeddeedddd7770000000000000000000000000000000000000005679bd7ac78b769678cdddeecddacc7ae47a567888cccdddccc8881110000000000001110000000000003333331111115668ab69b89c88a668bcddeecee9bc67b56a99bcccaaa999555111111000000555aaacccbbb333222777eeeeeeccccdddddbbb445abceefeffeeeeeeeeedeedeeddebbcbbcdddeeebbbbbbcccbbb666dddeffdeffffdddccceeedefbdfeffdefbeffff999cccdefadfbefcefdefcefbefbefdeeeefadfbefffffffcefeffcccfffadf4cfdeffffdefeffbdf4cfadf3cf3cfbefeeedddbdf3bf3cf4cf6cf3cf5cf4cf7cfcef4cf4cfdefdff5cfbefdddcccdef3cf9dfdef4cfbdf9df4cf7cf3cf4cf6cfefffffadf4cfadfcef9df4cfdefadf2bf9df4cf3cf8cfdef4cfcefccd888fff9df3bf9cf3af7bf6af5af5af7bfadf3afadffff8cf2bf3bfcefadf3bfadf8cf3bfbdf4bf9cf5bf7bf3afdefbbb444ddddef48f37f47f37f26f58f37f57fbcf89f47fcdf79f79fbdfeffbcf38f6af49f38fabf48fbcf9af27f37feefaaa000aaafff79f37fbcf57f37f8af37f68fccfddf57f89f58f9bfffffffbcf37fddfddf47f57f47fbcfddf37f47ffff999000344eeeddfbcfeffddfcdfdefabfeefffffffdefeefddfeefddeccdddf9afeeffffddfddfddfeeffffbcfbcffff77800000099aeeeeeeddeddeddeeeeeefdee89abbcddeccdddddde99a99aeeffffeefdddeeeddeddeccdcddeeefffddd45600000022456866845745745755767956822423544723534645723433477978a679446567457446346346568679558112";

    constant SPEED : integer := 8;

    signal position_x : integer range -SPEED to WIDTH + SPEED := 0;
    signal position_y : integer range -SPEED to HEIGHT + SPEED := 0;

    signal random_bit : std_logic := '0';
    signal color : std_logic_vector(23 downto 0) := x"FFFFFF";

    component OSCG is
        generic (
            DIV : integer := 128
        );
        port (
            OSC : out std_logic
        );
    end component;

    signal pos : integer range 0 to IMAGE_HEIGHT*IMAGE_WIDTH*12;
    signal r, g, b : std_logic_vector(3 downto 0);
begin
    char <= 0;

    pos <= IMAGE_HEIGHT*IMAGE_WIDTH*12 - 1 - 12*(py - position_y)*(px - position_x);
    r <= image(pos) & image(pos - 1) & image(pos - 2) & image(pos - 3);
    g <= image(pos - 4) & image(pos - 5) & image(pos - 6) & image(pos - 7);
    b <= image(pos - 8) & image(pos - 9) & image(pos - 10) & image(pos - 11);

    background_color <= r & r & g & g & b & b
        when
            px >= position_x and px < position_x + IMAGE_WIDTH and
            py >= position_y and py < position_y + IMAGE_HEIGHT
        else x"000000";
    foreground_color <= (others => '1');

    rng : OSCG port map (
        OSC => random_bit
    );

    process(clk)
        variable old_vsync : std_logic := '0';
        variable speed_x : integer range -SPEED to SPEED := SPEED;
        variable speed_y : integer range -SPEED to SPEED := SPEED;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                if position_x + speed_x + IMAGE_WIDTH >= WIDTH then
                    speed_x := -SPEED;
                    position_x <= WIDTH - IMAGE_WIDTH - 1;

                    color <= color(22 downto 0) & random_bit;
                elsif position_x + speed_x < 0 then
                    speed_x := SPEED;
                    position_x <= 0;

                    color <= color(22 downto 0) & random_bit;
                else
                    position_x <= position_x + speed_x;
                end if;

                if position_y + speed_y + IMAGE_HEIGHT >= HEIGHT then
                    speed_y := -SPEED;
                    position_y <= HEIGHT - IMAGE_HEIGHT - 1;

                    color <= color(22 downto 0) & random_bit;
                elsif position_y + speed_y < 0 then
                    speed_y := SPEED;
                    position_y <= 0;

                    color <= color(22 downto 0) & random_bit;
                else
                    position_y <= position_y + speed_y;
                end if;
            end if;
            old_vsync := vsync;
        end if;
    end process;
end architecture;


    #FPGA #Icepi-Zero #HDL #VHDL
    #fpga #icepizero #hdl #vhdl
  34. Icepi Zero Bot @[email protected] ·

    @[email protected]

    @[email protected] asked

    library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1'); uart_data : out std_logic_vector(7 downto 0) := (others => '0'); uart_ready : in std_logic; uart_valid : out std_logic := '0' ); end my_code; architecture rtl of my_code is alias red : std_logic_vector(7 downto 0) is background_color(23 downto 16); alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8); alias blue : std_logic_vector(7 downto 0) is background_color(7 downto 0); signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant example_text : string := "Hello Fediverse! <3"; constant example_text_row : integer := 15; constant example_text_col : integer := 15; constant uart_text : string := "Hello Fediverse on UART!" & LF; begin char <= character'pos(example_text(col + 1 - example_text_col)) when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0; red <= std_logic_vector(to_unsigned(col*4, 8)); green <= std_logic_vector(to_unsigned(py, 8)); blue <= std_logic_vector(resize(frame_counter, 8)); foreground_color <= (others => '1'); process(clk) variable old_vsync : std_logic := '0'; variable uart_counter : integer range uart_text'range := 1; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then frame_counter <= frame_counter + 1; end if; old_vsync := vsync; uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8)); uart_valid <= '1'; if uart_ready = '1' and uart_valid = '1' then if uart_counter < uart_text'length then uart_counter := uart_counter + 1; else uart_counter := 1; end if; end if; end if; end process; end architecture;

    Success!

    UART Output

    ... [TRUNCATED] ...
T!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
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Hello Fediverse on UAR


    UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1171242884.8%TRELLIS_FF177242880.7%TRELLIS_IO111975.6%
    TimingClockAchievedConstraint$glbnet$clkp39.04 MHz25 MHz$glbnet$clkt345.18 MHz250 MHz
    Code

    library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1');

        uart_data : out std_logic_vector(7 downto 0) := (others => '0');
        uart_ready : in std_logic;
        uart_valid : out std_logic := '0'
    );
end my_code;

architecture rtl of my_code is
    alias red   : std_logic_vector(7 downto 0) is background_color(23 downto 16);
    alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8);
    alias blue  : std_logic_vector(7 downto 0) is background_color(7 downto 0);

    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant example_text : string := "Hello Fediverse! <3";
    constant example_text_row : integer := 15;
    constant example_text_col : integer := 15;

    constant uart_text : string := "Hello Fediverse on UART!" & LF;
begin
    char <= character'pos(example_text(col + 1 - example_text_col))
        when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0;

    red   <= std_logic_vector(to_unsigned(col*4, 8));
    green <= std_logic_vector(to_unsigned(py, 8));
    blue  <= std_logic_vector(resize(frame_counter, 8));

    foreground_color <= (others => '1');

    process(clk)
        variable old_vsync : std_logic := '0';

        variable uart_counter : integer range uart_text'range := 1;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                frame_counter <= frame_counter + 1;
            end if;
            old_vsync := vsync;

            uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8));
            uart_valid <= '1';
            if uart_ready = '1' and uart_valid = '1' then
                if uart_counter < uart_text'length then
                    uart_counter := uart_counter + 1;
                else
                    uart_counter := 1;
                end if;
            end if;
        end if;
    end process;
end architecture;


    #FPGA #Icepi-Zero #HDL #VHDL
    #fpga #icepizero #hdl #vhdl
  35. Icepi Zero Bot @[email protected] ·

    @[email protected]

    @[email protected] asked

    library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1'); uart_data : out std_logic_vector(7 downto 0) := (others => '0'); uart_ready : in std_logic; uart_valid : out std_logic := '0' ); end my_code; architecture rtl of my_code is alias red : std_logic_vector(7 downto 0) is background_color(23 downto 16); alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8); alias blue : std_logic_vector(7 downto 0) is background_color(7 downto 0); signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant example_text : string := "Hello Fediverse! <3"; constant example_text_row : integer := 15; constant example_text_col : integer := 15; constant uart_text : string := "Hello Fediverse on UART!" & LF; begin char <= character'pos(example_text(col + 1 - example_text_col)) when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0; red <= std_logic_vector(to_unsigned(col*4, 8)); green <= std_logic_vector(to_unsigned(py, 8)); blue <= std_logic_vector(resize(frame_counter, 8)); foreground_color <= (others => '1'); process(clk) variable old_vsync : std_logic := '0'; variable uart_counter : integer range uart_text'range := 1; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then frame_counter <= frame_counter + 1; end if; old_vsync := vsync; uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8)); uart_valid <= '1'; if uart_ready = '1' and uart_valid = '1' then if uart_counter < uart_text'length then uart_counter := uart_counter + 1; else uart_counter := 1; end if; end if; end if; end process; end architecture;

    Success!

    UART Output

    ... [TRUNCATED] ...
T!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
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Hello Fediverse on UART!
Hello Fediverse on UART!
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Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
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    UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1171242884.8%TRELLIS_FF177242880.7%TRELLIS_IO111975.6%
    TimingClockAchievedConstraint$glbnet$clkp39.04 MHz25 MHz$glbnet$clkt345.18 MHz250 MHz
    Code

    library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1');

        uart_data : out std_logic_vector(7 downto 0) := (others => '0');
        uart_ready : in std_logic;
        uart_valid : out std_logic := '0'
    );
end my_code;

architecture rtl of my_code is
    alias red   : std_logic_vector(7 downto 0) is background_color(23 downto 16);
    alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8);
    alias blue  : std_logic_vector(7 downto 0) is background_color(7 downto 0);

    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant example_text : string := "Hello Fediverse! <3";
    constant example_text_row : integer := 15;
    constant example_text_col : integer := 15;

    constant uart_text : string := "Hello Fediverse on UART!" & LF;
begin
    char <= character'pos(example_text(col + 1 - example_text_col))
        when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0;

    red   <= std_logic_vector(to_unsigned(col*4, 8));
    green <= std_logic_vector(to_unsigned(py, 8));
    blue  <= std_logic_vector(resize(frame_counter, 8));

    foreground_color <= (others => '1');

    process(clk)
        variable old_vsync : std_logic := '0';

        variable uart_counter : integer range uart_text'range := 1;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                frame_counter <= frame_counter + 1;
            end if;
            old_vsync := vsync;

            uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8));
            uart_valid <= '1';
            if uart_ready = '1' and uart_valid = '1' then
                if uart_counter < uart_text'length then
                    uart_counter := uart_counter + 1;
                else
                    uart_counter := 1;
                end if;
            end if;
        end if;
    end process;
end architecture;


    #FPGA #Icepi-Zero #HDL #VHDL
    #fpga #icepizero #hdl #vhdl
  36. Icepi Zero Bot @[email protected] ·

    @[email protected]

    @[email protected] asked

    library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1'); uart_data : out std_logic_vector(7 downto 0) := (others => '0'); uart_ready : in std_logic; uart_valid : out std_logic := '0' ); end my_code; architecture rtl of my_code is alias red : std_logic_vector(7 downto 0) is background_color(23 downto 16); alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8); alias blue : std_logic_vector(7 downto 0) is background_color(7 downto 0); signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant example_text : string := "Hello Fediverse! <3"; constant example_text_row : integer := 15; constant example_text_col : integer := 15; constant uart_text : string := "Hello Fediverse on UART!" & LF; begin char <= character'pos(example_text(col + 1 - example_text_col)) when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0; red <= std_logic_vector(to_unsigned(col*4, 8)); green <= std_logic_vector(to_unsigned(py, 8)); blue <= std_logic_vector(resize(frame_counter, 8)); foreground_color <= (others => '1'); process(clk) variable old_vsync : std_logic := '0'; variable uart_counter : integer range uart_text'range := 1; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then frame_counter <= frame_counter + 1; end if; old_vsync := vsync; uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8)); uart_valid <= '1'; if uart_ready = '1' and uart_valid = '1' then if uart_counter < uart_text'length then uart_counter := uart_counter + 1; else uart_counter := 1; end if; end if; end if; end process; end architecture;

    Success!

    UART Output

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    UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1171242884.8%TRELLIS_FF177242880.7%TRELLIS_IO111975.6%
    TimingClockAchievedConstraint$glbnet$clkp39.04 MHz25 MHz$glbnet$clkt345.18 MHz250 MHz
    Code

    library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1');

        uart_data : out std_logic_vector(7 downto 0) := (others => '0');
        uart_ready : in std_logic;
        uart_valid : out std_logic := '0'
    );
end my_code;

architecture rtl of my_code is
    alias red   : std_logic_vector(7 downto 0) is background_color(23 downto 16);
    alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8);
    alias blue  : std_logic_vector(7 downto 0) is background_color(7 downto 0);

    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant example_text : string := "Hello Fediverse! <3";
    constant example_text_row : integer := 15;
    constant example_text_col : integer := 15;

    constant uart_text : string := "Hello Fediverse on UART!" & LF;
begin
    char <= character'pos(example_text(col + 1 - example_text_col))
        when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0;

    red   <= std_logic_vector(to_unsigned(col*4, 8));
    green <= std_logic_vector(to_unsigned(py, 8));
    blue  <= std_logic_vector(resize(frame_counter, 8));

    foreground_color <= (others => '1');

    process(clk)
        variable old_vsync : std_logic := '0';

        variable uart_counter : integer range uart_text'range := 1;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                frame_counter <= frame_counter + 1;
            end if;
            old_vsync := vsync;

            uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8));
            uart_valid <= '1';
            if uart_ready = '1' and uart_valid = '1' then
                if uart_counter < uart_text'length then
                    uart_counter := uart_counter + 1;
                else
                    uart_counter := 1;
                end if;
            end if;
        end if;
    end process;
end architecture;


    #FPGA #Icepi-Zero #HDL #VHDL
    #fpga #icepizero #hdl #vhdl
  37. Icepi Zero Bot @[email protected] ·

    @[email protected]

    @[email protected] asked

    library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1'); uart_data : out std_logic_vector(7 downto 0) := (others => '0'); uart_ready : in std_logic; uart_valid : out std_logic := '0' ); end my_code; architecture rtl of my_code is alias red : std_logic_vector(7 downto 0) is background_color(23 downto 16); alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8); alias blue : std_logic_vector(7 downto 0) is background_color(7 downto 0); signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant example_text : string := "Hello Fediverse! <3"; constant example_text_row : integer := 15; constant example_text_col : integer := 15; constant uart_text : string := "Hello Fediverse on UART!" & LF; begin char <= character'pos(example_text(col + 1 - example_text_col)) when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0; red <= std_logic_vector(to_unsigned(col*4, 8)); green <= std_logic_vector(to_unsigned(py, 8)); blue <= std_logic_vector(resize(frame_counter, 8)); foreground_color <= (others => '1'); process(clk) variable old_vsync : std_logic := '0'; variable uart_counter : integer range uart_text'range := 1; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then frame_counter <= frame_counter + 1; end if; old_vsync := vsync; uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8)); uart_valid <= '1'; if uart_ready = '1' and uart_valid = '1' then if uart_counter < uart_text'length then uart_counter := uart_counter + 1; else uart_counter := 1; end if; end if; end if; end process; end architecture;

    Success!

    UART Output

    ... [TRUNCATED] ...
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    UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1171242884.8%TRELLIS_FF177242880.7%TRELLIS_IO111975.6%
    TimingClockAchievedConstraint$glbnet$clkp39.04 MHz25 MHz$glbnet$clkt345.18 MHz250 MHz
    Code

    library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1');

        uart_data : out std_logic_vector(7 downto 0) := (others => '0');
        uart_ready : in std_logic;
        uart_valid : out std_logic := '0'
    );
end my_code;

architecture rtl of my_code is
    alias red   : std_logic_vector(7 downto 0) is background_color(23 downto 16);
    alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8);
    alias blue  : std_logic_vector(7 downto 0) is background_color(7 downto 0);

    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant example_text : string := "Hello Fediverse! <3";
    constant example_text_row : integer := 15;
    constant example_text_col : integer := 15;

    constant uart_text : string := "Hello Fediverse on UART!" & LF;
begin
    char <= character'pos(example_text(col + 1 - example_text_col))
        when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0;

    red   <= std_logic_vector(to_unsigned(col*4, 8));
    green <= std_logic_vector(to_unsigned(py, 8));
    blue  <= std_logic_vector(resize(frame_counter, 8));

    foreground_color <= (others => '1');

    process(clk)
        variable old_vsync : std_logic := '0';

        variable uart_counter : integer range uart_text'range := 1;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                frame_counter <= frame_counter + 1;
            end if;
            old_vsync := vsync;

            uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8));
            uart_valid <= '1';
            if uart_ready = '1' and uart_valid = '1' then
                if uart_counter < uart_text'length then
                    uart_counter := uart_counter + 1;
                else
                    uart_counter := 1;
                end if;
            end if;
        end if;
    end process;
end architecture;


    #FPGA #Icepi-Zero #HDL #VHDL
    #fpga #icepizero #hdl #vhdl
  38. Icepi Zero Bot @[email protected] ·

    @[email protected]

    @[email protected] asked

    library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1'); uart_data : out std_logic_vector(7 downto 0) := (others => '0'); uart_ready : in std_logic; uart_valid : out std_logic := '0' ); end my_code; architecture rtl of my_code is alias red : std_logic_vector(7 downto 0) is background_color(23 downto 16); alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8); alias blue : std_logic_vector(7 downto 0) is background_color(7 downto 0); signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant example_text : string := "Hello Fediverse! <3"; constant example_text_row : integer := 15; constant example_text_col : integer := 15; constant uart_text : string := "Hello Fediverse on UART!" & LF; begin char <= character'pos(example_text(col + 1 - example_text_col)) when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0; red <= std_logic_vector(to_unsigned(col*4, 8)); green <= std_logic_vector(to_unsigned(py, 8)); blue <= std_logic_vector(resize(frame_counter, 8)); foreground_color <= (others => '1'); process(clk) variable old_vsync : std_logic := '0'; variable uart_counter : integer range uart_text'range := 1; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then frame_counter <= frame_counter + 1; end if; old_vsync := vsync; uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8)); uart_valid <= '1'; if uart_ready = '1' and uart_valid = '1' then if uart_counter < uart_text'length then uart_counter := uart_counter + 1; else uart_counter := 1; end if; end if; end if; end process; end architecture;

    Success!

    UART Output

    ... [TRUNCATED] ...
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    UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1171242884.8%TRELLIS_FF177242880.7%TRELLIS_IO111975.6%
    TimingClockAchievedConstraint$glbnet$clkp39.04 MHz25 MHz$glbnet$clkt345.18 MHz250 MHz
    Code

    library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1');

        uart_data : out std_logic_vector(7 downto 0) := (others => '0');
        uart_ready : in std_logic;
        uart_valid : out std_logic := '0'
    );
end my_code;

architecture rtl of my_code is
    alias red   : std_logic_vector(7 downto 0) is background_color(23 downto 16);
    alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8);
    alias blue  : std_logic_vector(7 downto 0) is background_color(7 downto 0);

    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant example_text : string := "Hello Fediverse! <3";
    constant example_text_row : integer := 15;
    constant example_text_col : integer := 15;

    constant uart_text : string := "Hello Fediverse on UART!" & LF;
begin
    char <= character'pos(example_text(col + 1 - example_text_col))
        when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0;

    red   <= std_logic_vector(to_unsigned(col*4, 8));
    green <= std_logic_vector(to_unsigned(py, 8));
    blue  <= std_logic_vector(resize(frame_counter, 8));

    foreground_color <= (others => '1');

    process(clk)
        variable old_vsync : std_logic := '0';

        variable uart_counter : integer range uart_text'range := 1;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                frame_counter <= frame_counter + 1;
            end if;
            old_vsync := vsync;

            uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8));
            uart_valid <= '1';
            if uart_ready = '1' and uart_valid = '1' then
                if uart_counter < uart_text'length then
                    uart_counter := uart_counter + 1;
                else
                    uart_counter := 1;
                end if;
            end if;
        end if;
    end process;
end architecture;


    #FPGA #Icepi-Zero #HDL #VHDL
    #fpga #icepizero #hdl #vhdl
  39. Icepi Zero Bot @[email protected] ·

    @[email protected]

    @[email protected] asked

    library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1'); uart_data : out std_logic_vector(7 downto 0) := (others => '0'); uart_ready : in std_logic; uart_valid : out std_logic := '0' ); end my_code; architecture rtl of my_code is alias red : std_logic_vector(7 downto 0) is background_color(23 downto 16); alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8); alias blue : std_logic_vector(7 downto 0) is background_color(7 downto 0); signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant example_text : string := "Hello Fediverse! <3"; constant example_text_row : integer := 15; constant example_text_col : integer := 15; constant uart_text : string := "Hello Fediverse on UART!" & LF; begin char <= character'pos(example_text(col + 1 - example_text_col)) when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0; red <= std_logic_vector(to_unsigned(col*4, 8)); green <= std_logic_vector(to_unsigned(py, 8)); blue <= std_logic_vector(resize(frame_counter, 8)); foreground_color <= (others => '1'); process(clk) variable old_vsync : std_logic := '0'; variable uart_counter : integer range uart_text'range := 1; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then frame_counter <= frame_counter + 1; end if; old_vsync := vsync; uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8)); uart_valid <= '1'; if uart_ready = '1' and uart_valid = '1' then if uart_counter < uart_text'length then uart_counter := uart_counter + 1; else uart_counter := 1; end if; end if; end if; end process; end architecture;

    Success!

    UART Output

    ... [TRUNCATED] ...
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    UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1171242884.8%TRELLIS_FF177242880.7%TRELLIS_IO111975.6%
    TimingClockAchievedConstraint$glbnet$clkp39.04 MHz25 MHz$glbnet$clkt345.18 MHz250 MHz
    Code

    library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1');

        uart_data : out std_logic_vector(7 downto 0) := (others => '0');
        uart_ready : in std_logic;
        uart_valid : out std_logic := '0'
    );
end my_code;

architecture rtl of my_code is
    alias red   : std_logic_vector(7 downto 0) is background_color(23 downto 16);
    alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8);
    alias blue  : std_logic_vector(7 downto 0) is background_color(7 downto 0);

    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant example_text : string := "Hello Fediverse! <3";
    constant example_text_row : integer := 15;
    constant example_text_col : integer := 15;

    constant uart_text : string := "Hello Fediverse on UART!" & LF;
begin
    char <= character'pos(example_text(col + 1 - example_text_col))
        when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0;

    red   <= std_logic_vector(to_unsigned(col*4, 8));
    green <= std_logic_vector(to_unsigned(py, 8));
    blue  <= std_logic_vector(resize(frame_counter, 8));

    foreground_color <= (others => '1');

    process(clk)
        variable old_vsync : std_logic := '0';

        variable uart_counter : integer range uart_text'range := 1;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                frame_counter <= frame_counter + 1;
            end if;
            old_vsync := vsync;

            uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8));
            uart_valid <= '1';
            if uart_ready = '1' and uart_valid = '1' then
                if uart_counter < uart_text'length then
                    uart_counter := uart_counter + 1;
                else
                    uart_counter := 1;
                end if;
            end if;
        end if;
    end process;
end architecture;


    #FPGA #Icepi-Zero #HDL #VHDL
    #fpga #icepizero #hdl #vhdl
  40. Icepi Zero Bot @[email protected] ·

    @[email protected]

    @[email protected] asked

    library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1'); uart_data : out std_logic_vector(7 downto 0) := (others => '0'); uart_ready : in std_logic; uart_valid : out std_logic := '0' ); end my_code; architecture rtl of my_code is alias red : std_logic_vector(7 downto 0) is background_color(23 downto 16); alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8); alias blue : std_logic_vector(7 downto 0) is background_color(7 downto 0); signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant example_text : string := "Hello Fediverse! <3"; constant example_text_row : integer := 15; constant example_text_col : integer := 15; constant uart_text : string := "Hello Fediverse on UART!" & LF; begin char <= character'pos(example_text(col + 1 - example_text_col)) when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0; red <= std_logic_vector(to_unsigned(col*4, 8)); green <= std_logic_vector(to_unsigned(py, 8)); blue <= std_logic_vector(resize(frame_counter, 8)); foreground_color <= (others => '1'); process(clk) variable old_vsync : std_logic := '0'; variable uart_counter : integer range uart_text'range := 1; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then frame_counter <= frame_counter + 1; end if; old_vsync := vsync; uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8)); uart_valid <= '1'; if uart_ready = '1' and uart_valid = '1' then if uart_counter < uart_text'length then uart_counter := uart_counter + 1; else uart_counter := 1; end if; end if; end if; end process; end architecture;

    Success!

    UART Output

    ... [TRUNCATED] ...
iverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
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Hello Fed


    UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1171242884.8%TRELLIS_FF177242880.7%TRELLIS_IO111975.6%
    TimingClockAchievedConstraint$glbnet$clkp39.04 MHz25 MHz$glbnet$clkt345.18 MHz250 MHz
    Code

    library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1');

        uart_data : out std_logic_vector(7 downto 0) := (others => '0');
        uart_ready : in std_logic;
        uart_valid : out std_logic := '0'
    );
end my_code;

architecture rtl of my_code is
    alias red   : std_logic_vector(7 downto 0) is background_color(23 downto 16);
    alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8);
    alias blue  : std_logic_vector(7 downto 0) is background_color(7 downto 0);

    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant example_text : string := "Hello Fediverse! <3";
    constant example_text_row : integer := 15;
    constant example_text_col : integer := 15;

    constant uart_text : string := "Hello Fediverse on UART!" & LF;
begin
    char <= character'pos(example_text(col + 1 - example_text_col))
        when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0;

    red   <= std_logic_vector(to_unsigned(col*4, 8));
    green <= std_logic_vector(to_unsigned(py, 8));
    blue  <= std_logic_vector(resize(frame_counter, 8));

    foreground_color <= (others => '1');

    process(clk)
        variable old_vsync : std_logic := '0';

        variable uart_counter : integer range uart_text'range := 1;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                frame_counter <= frame_counter + 1;
            end if;
            old_vsync := vsync;

            uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8));
            uart_valid <= '1';
            if uart_ready = '1' and uart_valid = '1' then
                if uart_counter < uart_text'length then
                    uart_counter := uart_counter + 1;
                else
                    uart_counter := 1;
                end if;
            end if;
        end if;
    end process;
end architecture;


    #FPGA #Icepi-Zero #HDL #VHDL
    #fpga #icepizero #hdl #vhdl
  41. Icepi Zero Bot @[email protected] ·

    @[email protected]

    @[email protected] asked

    library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1'); uart_data : out std_logic_vector(7 downto 0) := (others => '0'); uart_ready : in std_logic; uart_valid : out std_logic := '0' ); end my_code; architecture rtl of my_code is alias red : std_logic_vector(7 downto 0) is background_color(23 downto 16); alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8); alias blue : std_logic_vector(7 downto 0) is background_color(7 downto 0); signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant example_text : string := "Hello Fediverse! <3"; constant example_text_row : integer := 15; constant example_text_col : integer := 15; constant uart_text : string := "Hello Fediverse on UART!" & LF; begin char <= character'pos(example_text(col + 1 - example_text_col)) when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0; red <= std_logic_vector(to_unsigned(col*4, 8)); green <= std_logic_vector(to_unsigned(py, 8)); blue <= std_logic_vector(resize(frame_counter, 8)); foreground_color <= (others => '1'); process(clk) variable old_vsync : std_logic := '0'; variable uart_counter : integer range uart_text'range := 1; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then frame_counter <= frame_counter + 1; end if; old_vsync := vsync; uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8)); uart_valid <= '1'; if uart_ready = '1' and uart_valid = '1' then if uart_counter < uart_text'length then uart_counter := uart_counter + 1; else uart_counter := 1; end if; end if; end if; end process; end architecture;

    Success!

    UART Output

    ... [TRUNCATED] ...
iverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
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Hello Fed


    UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1171242884.8%TRELLIS_FF177242880.7%TRELLIS_IO111975.6%
    TimingClockAchievedConstraint$glbnet$clkp39.04 MHz25 MHz$glbnet$clkt345.18 MHz250 MHz
    Code

    library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1');

        uart_data : out std_logic_vector(7 downto 0) := (others => '0');
        uart_ready : in std_logic;
        uart_valid : out std_logic := '0'
    );
end my_code;

architecture rtl of my_code is
    alias red   : std_logic_vector(7 downto 0) is background_color(23 downto 16);
    alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8);
    alias blue  : std_logic_vector(7 downto 0) is background_color(7 downto 0);

    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant example_text : string := "Hello Fediverse! <3";
    constant example_text_row : integer := 15;
    constant example_text_col : integer := 15;

    constant uart_text : string := "Hello Fediverse on UART!" & LF;
begin
    char <= character'pos(example_text(col + 1 - example_text_col))
        when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0;

    red   <= std_logic_vector(to_unsigned(col*4, 8));
    green <= std_logic_vector(to_unsigned(py, 8));
    blue  <= std_logic_vector(resize(frame_counter, 8));

    foreground_color <= (others => '1');

    process(clk)
        variable old_vsync : std_logic := '0';

        variable uart_counter : integer range uart_text'range := 1;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                frame_counter <= frame_counter + 1;
            end if;
            old_vsync := vsync;

            uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8));
            uart_valid <= '1';
            if uart_ready = '1' and uart_valid = '1' then
                if uart_counter < uart_text'length then
                    uart_counter := uart_counter + 1;
                else
                    uart_counter := 1;
                end if;
            end if;
        end if;
    end process;
end architecture;


    #FPGA #Icepi-Zero #HDL #VHDL
    #fpga #icepizero #hdl #vhdl
  42. Icepi Zero Bot @[email protected] ·

    @[email protected]

    @[email protected] asked

    library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1'); uart_data : out std_logic_vector(7 downto 0) := (others => '0'); uart_ready : in std_logic; uart_valid : out std_logic := '0' ); end my_code; architecture rtl of my_code is alias red : std_logic_vector(7 downto 0) is background_color(23 downto 16); alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8); alias blue : std_logic_vector(7 downto 0) is background_color(7 downto 0); signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant example_text : string := "Hello Fediverse! <3"; constant example_text_row : integer := 15; constant example_text_col : integer := 15; constant uart_text : string := "Hello Fediverse on UART!" & LF; begin char <= character'pos(example_text(col + 1 - example_text_col)) when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0; red <= std_logic_vector(to_unsigned(col*4, 8)); green <= std_logic_vector(to_unsigned(py, 8)); blue <= std_logic_vector(resize(frame_counter, 8)); foreground_color <= (others => '1'); process(clk) variable old_vsync : std_logic := '0'; variable uart_counter : integer range uart_text'range := 1; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then frame_counter <= frame_counter + 1; end if; old_vsync := vsync; uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8)); uart_valid <= '1'; if uart_ready = '1' and uart_valid = '1' then if uart_counter < uart_text'length then uart_counter := uart_counter + 1; else uart_counter := 1; end if; end if; end if; end process; end architecture;

    Success!

    UART Output

    ... [TRUNCATED] ...

Hello Fediverse on UART!
Hello Fediverse on UART!
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    UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1171242884.8%TRELLIS_FF177242880.7%TRELLIS_IO111975.6%
    TimingClockAchievedConstraint$glbnet$clkp39.04 MHz25 MHz$glbnet$clkt345.18 MHz250 MHz
    Code

    library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1');

        uart_data : out std_logic_vector(7 downto 0) := (others => '0');
        uart_ready : in std_logic;
        uart_valid : out std_logic := '0'
    );
end my_code;

architecture rtl of my_code is
    alias red   : std_logic_vector(7 downto 0) is background_color(23 downto 16);
    alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8);
    alias blue  : std_logic_vector(7 downto 0) is background_color(7 downto 0);

    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant example_text : string := "Hello Fediverse! <3";
    constant example_text_row : integer := 15;
    constant example_text_col : integer := 15;

    constant uart_text : string := "Hello Fediverse on UART!" & LF;
begin
    char <= character'pos(example_text(col + 1 - example_text_col))
        when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0;

    red   <= std_logic_vector(to_unsigned(col*4, 8));
    green <= std_logic_vector(to_unsigned(py, 8));
    blue  <= std_logic_vector(resize(frame_counter, 8));

    foreground_color <= (others => '1');

    process(clk)
        variable old_vsync : std_logic := '0';

        variable uart_counter : integer range uart_text'range := 1;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                frame_counter <= frame_counter + 1;
            end if;
            old_vsync := vsync;

            uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8));
            uart_valid <= '1';
            if uart_ready = '1' and uart_valid = '1' then
                if uart_counter < uart_text'length then
                    uart_counter := uart_counter + 1;
                else
                    uart_counter := 1;
                end if;
            end if;
        end if;
    end process;
end architecture;


    #FPGA #Icepi-Zero #HDL #VHDL
    #fpga #icepizero #hdl #vhdl
  43. Icepi Zero Bot @[email protected] ·

    @[email protected]

    @[email protected] asked

    library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1'); uart_data : out std_logic_vector(7 downto 0) := (others => '0'); uart_ready : in std_logic; uart_valid : out std_logic := '0' ); end my_code; architecture rtl of my_code is alias red : std_logic_vector(7 downto 0) is background_color(23 downto 16); alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8); alias blue : std_logic_vector(7 downto 0) is background_color(7 downto 0); signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant example_text : string := "Hello Fediverse! <3"; constant example_text_row : integer := 15; constant example_text_col : integer := 15; constant uart_text : string := "Hello Fediverse on UART!" & LF; begin char <= character'pos(example_text(col + 1 - example_text_col)) when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0; red <= std_logic_vector(to_unsigned(col*4, 8)); green <= std_logic_vector(to_unsigned(py, 8)); blue <= std_logic_vector(resize(frame_counter, 8)); foreground_color <= (others => '1'); process(clk) variable old_vsync : std_logic := '0'; variable uart_counter : integer range uart_text'range := 1; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then frame_counter <= frame_counter + 1; end if; old_vsync := vsync; uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8)); uart_valid <= '1'; if uart_ready = '1' and uart_valid = '1' then if uart_counter < uart_text'length then uart_counter := uart_counter + 1; else uart_counter := 1; end if; end if; end if; end process; end architecture;

    Success!

    UART Output

    ... [TRUNCATED] ...

Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
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    UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1171242884.8%TRELLIS_FF177242880.7%TRELLIS_IO111975.6%
    TimingClockAchievedConstraint$glbnet$clkp39.04 MHz25 MHz$glbnet$clkt345.18 MHz250 MHz
    Code

    library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1');

        uart_data : out std_logic_vector(7 downto 0) := (others => '0');
        uart_ready : in std_logic;
        uart_valid : out std_logic := '0'
    );
end my_code;

architecture rtl of my_code is
    alias red   : std_logic_vector(7 downto 0) is background_color(23 downto 16);
    alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8);
    alias blue  : std_logic_vector(7 downto 0) is background_color(7 downto 0);

    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant example_text : string := "Hello Fediverse! <3";
    constant example_text_row : integer := 15;
    constant example_text_col : integer := 15;

    constant uart_text : string := "Hello Fediverse on UART!" & LF;
begin
    char <= character'pos(example_text(col + 1 - example_text_col))
        when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0;

    red   <= std_logic_vector(to_unsigned(col*4, 8));
    green <= std_logic_vector(to_unsigned(py, 8));
    blue  <= std_logic_vector(resize(frame_counter, 8));

    foreground_color <= (others => '1');

    process(clk)
        variable old_vsync : std_logic := '0';

        variable uart_counter : integer range uart_text'range := 1;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                frame_counter <= frame_counter + 1;
            end if;
            old_vsync := vsync;

            uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8));
            uart_valid <= '1';
            if uart_ready = '1' and uart_valid = '1' then
                if uart_counter < uart_text'length then
                    uart_counter := uart_counter + 1;
                else
                    uart_counter := 1;
                end if;
            end if;
        end if;
    end process;
end architecture;


    #FPGA #Icepi-Zero #HDL #VHDL
    #fpga #icepizero #hdl #vhdl
  44. Icepi Zero Bot @[email protected] ·

    @[email protected]

    @[email protected] asked

    library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1'); uart_data : out std_logic_vector(7 downto 0) := (others => '0'); uart_ready : in std_logic; uart_valid : out std_logic := '0' ); end my_code; architecture rtl of my_code is alias red : std_logic_vector(7 downto 0) is background_color(23 downto 16); alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8); alias blue : std_logic_vector(7 downto 0) is background_color(7 downto 0); signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant example_text : string := "Hello Fediverse! <3"; constant example_text_row : integer := 15; constant example_text_col : integer := 15; constant uart_text : string := "Hello Fediverse on UART!" & LF; begin char <= character'pos(example_text(col + 1 - example_text_col)) when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0; red <= std_logic_vector(to_unsigned(col*4, 8)); green <= std_logic_vector(to_unsigned(py, 8)); blue <= std_logic_vector(resize(frame_counter, 8)); foreground_color <= (others => '1'); process(clk) variable old_vsync : std_logic := '0'; variable uart_counter : integer range uart_text'range := 1; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then frame_counter <= frame_counter + 1; end if; old_vsync := vsync; uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8)); uart_valid <= '1'; if uart_ready = '1' and uart_valid = '1' then if uart_counter < uart_text'length then uart_counter := uart_counter + 1; else uart_counter := 1; end if; end if; end if; end process; end architecture;

    Success!

    UART Output

    ... [TRUNCATED] ...
!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
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    UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1171242884.8%TRELLIS_FF177242880.7%TRELLIS_IO111975.6%
    TimingClockAchievedConstraint$glbnet$clkp39.04 MHz25 MHz$glbnet$clkt345.18 MHz250 MHz
    Code

    library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1');

        uart_data : out std_logic_vector(7 downto 0) := (others => '0');
        uart_ready : in std_logic;
        uart_valid : out std_logic := '0'
    );
end my_code;

architecture rtl of my_code is
    alias red   : std_logic_vector(7 downto 0) is background_color(23 downto 16);
    alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8);
    alias blue  : std_logic_vector(7 downto 0) is background_color(7 downto 0);

    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant example_text : string := "Hello Fediverse! <3";
    constant example_text_row : integer := 15;
    constant example_text_col : integer := 15;

    constant uart_text : string := "Hello Fediverse on UART!" & LF;
begin
    char <= character'pos(example_text(col + 1 - example_text_col))
        when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0;

    red   <= std_logic_vector(to_unsigned(col*4, 8));
    green <= std_logic_vector(to_unsigned(py, 8));
    blue  <= std_logic_vector(resize(frame_counter, 8));

    foreground_color <= (others => '1');

    process(clk)
        variable old_vsync : std_logic := '0';

        variable uart_counter : integer range uart_text'range := 1;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                frame_counter <= frame_counter + 1;
            end if;
            old_vsync := vsync;

            uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8));
            uart_valid <= '1';
            if uart_ready = '1' and uart_valid = '1' then
                if uart_counter < uart_text'length then
                    uart_counter := uart_counter + 1;
                else
                    uart_counter := 1;
                end if;
            end if;
        end if;
    end process;
end architecture;


    #FPGA #Icepi-Zero #HDL #VHDL
    #fpga #icepizero #hdl #vhdl
  45. Icepi Zero Bot @[email protected] ·

    @[email protected]

    @[email protected] asked

    library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1'); uart_data : out std_logic_vector(7 downto 0) := (others => '0'); uart_ready : in std_logic; uart_valid : out std_logic := '0' ); end my_code; architecture rtl of my_code is alias red : std_logic_vector(7 downto 0) is background_color(23 downto 16); alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8); alias blue : std_logic_vector(7 downto 0) is background_color(7 downto 0); signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant example_text : string := "Hello Fediverse! <3"; constant example_text_row : integer := 15; constant example_text_col : integer := 15; constant uart_text : string := "Hello Fediverse on UART!" & LF; begin char <= character'pos(example_text(col + 1 - example_text_col)) when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0; red <= std_logic_vector(to_unsigned(col*4, 8)); green <= std_logic_vector(to_unsigned(py, 8)); blue <= std_logic_vector(resize(frame_counter, 8)); foreground_color <= (others => '1'); process(clk) variable old_vsync : std_logic := '0'; variable uart_counter : integer range uart_text'range := 1; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then frame_counter <= frame_counter + 1; end if; old_vsync := vsync; uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8)); uart_valid <= '1'; if uart_ready = '1' and uart_valid = '1' then if uart_counter < uart_text'length then uart_counter := uart_counter + 1; else uart_counter := 1; end if; end if; end if; end process; end architecture;

    Success!

    UART Output

    ... [TRUNCATED] ...
!
Hello Fediverse on UART!
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    UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1171242884.8%TRELLIS_FF177242880.7%TRELLIS_IO111975.6%
    TimingClockAchievedConstraint$glbnet$clkp39.04 MHz25 MHz$glbnet$clkt345.18 MHz250 MHz
    Code

    library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1');

        uart_data : out std_logic_vector(7 downto 0) := (others => '0');
        uart_ready : in std_logic;
        uart_valid : out std_logic := '0'
    );
end my_code;

architecture rtl of my_code is
    alias red   : std_logic_vector(7 downto 0) is background_color(23 downto 16);
    alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8);
    alias blue  : std_logic_vector(7 downto 0) is background_color(7 downto 0);

    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant example_text : string := "Hello Fediverse! <3";
    constant example_text_row : integer := 15;
    constant example_text_col : integer := 15;

    constant uart_text : string := "Hello Fediverse on UART!" & LF;
begin
    char <= character'pos(example_text(col + 1 - example_text_col))
        when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0;

    red   <= std_logic_vector(to_unsigned(col*4, 8));
    green <= std_logic_vector(to_unsigned(py, 8));
    blue  <= std_logic_vector(resize(frame_counter, 8));

    foreground_color <= (others => '1');

    process(clk)
        variable old_vsync : std_logic := '0';

        variable uart_counter : integer range uart_text'range := 1;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                frame_counter <= frame_counter + 1;
            end if;
            old_vsync := vsync;

            uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8));
            uart_valid <= '1';
            if uart_ready = '1' and uart_valid = '1' then
                if uart_counter < uart_text'length then
                    uart_counter := uart_counter + 1;
                else
                    uart_counter := 1;
                end if;
            end if;
        end if;
    end process;
end architecture;


    #FPGA #Icepi-Zero #HDL #VHDL
    #fpga #icepizero #hdl #vhdl
  46. Icepi Zero Bot @[email protected] ·

    @[email protected]

    @[email protected] asked

    library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1'); uart_data : out std_logic_vector(7 downto 0) := (others => '0'); uart_ready : in std_logic; uart_valid : out std_logic := '0' ); end my_code; architecture rtl of my_code is alias red : std_logic_vector(7 downto 0) is background_color(23 downto 16); alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8); alias blue : std_logic_vector(7 downto 0) is background_color(7 downto 0); signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant example_text : string := "Hello Fediverse! <3"; constant example_text_row : integer := 15; constant example_text_col : integer := 15; constant uart_text : string := "Hello Fediverse on UART!" & LF; begin char <= character'pos(example_text(col + 1 - example_text_col)) when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0; red <= std_logic_vector(to_unsigned(col*4, 8)); green <= std_logic_vector(to_unsigned(py, 8)); blue <= std_logic_vector(resize(frame_counter, 8)); foreground_color <= (others => '1'); process(clk) variable old_vsync : std_logic := '0'; variable uart_counter : integer range uart_text'range := 1; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then frame_counter <= frame_counter + 1; end if; old_vsync := vsync; uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8)); uart_valid <= '1'; if uart_ready = '1' and uart_valid = '1' then if uart_counter < uart_text'length then uart_counter := uart_counter + 1; else uart_counter := 1; end if; end if; end if; end process; end architecture;

    Success!

    UART Output

    ... [TRUNCATED] ...
 on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
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Hello Fediverse


    UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1171242884.8%TRELLIS_FF177242880.7%TRELLIS_IO111975.6%
    TimingClockAchievedConstraint$glbnet$clkp39.04 MHz25 MHz$glbnet$clkt345.18 MHz250 MHz
    Code

    library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1');

        uart_data : out std_logic_vector(7 downto 0) := (others => '0');
        uart_ready : in std_logic;
        uart_valid : out std_logic := '0'
    );
end my_code;

architecture rtl of my_code is
    alias red   : std_logic_vector(7 downto 0) is background_color(23 downto 16);
    alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8);
    alias blue  : std_logic_vector(7 downto 0) is background_color(7 downto 0);

    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant example_text : string := "Hello Fediverse! <3";
    constant example_text_row : integer := 15;
    constant example_text_col : integer := 15;

    constant uart_text : string := "Hello Fediverse on UART!" & LF;
begin
    char <= character'pos(example_text(col + 1 - example_text_col))
        when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0;

    red   <= std_logic_vector(to_unsigned(col*4, 8));
    green <= std_logic_vector(to_unsigned(py, 8));
    blue  <= std_logic_vector(resize(frame_counter, 8));

    foreground_color <= (others => '1');

    process(clk)
        variable old_vsync : std_logic := '0';

        variable uart_counter : integer range uart_text'range := 1;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                frame_counter <= frame_counter + 1;
            end if;
            old_vsync := vsync;

            uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8));
            uart_valid <= '1';
            if uart_ready = '1' and uart_valid = '1' then
                if uart_counter < uart_text'length then
                    uart_counter := uart_counter + 1;
                else
                    uart_counter := 1;
                end if;
            end if;
        end if;
    end process;
end architecture;


    #FPGA #Icepi-Zero #HDL #VHDL
    #fpga #icepizero #hdl #vhdl
  47. Icepi Zero Bot @[email protected] ·

    @[email protected]

    @[email protected] asked

    library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1'); uart_data : out std_logic_vector(7 downto 0) := (others => '0'); uart_ready : in std_logic; uart_valid : out std_logic := '0' ); end my_code; architecture rtl of my_code is alias red : std_logic_vector(7 downto 0) is background_color(23 downto 16); alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8); alias blue : std_logic_vector(7 downto 0) is background_color(7 downto 0); signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant example_text : string := "Hello Fediverse! <3"; constant example_text_row : integer := 15; constant example_text_col : integer := 15; constant uart_text : string := "Hello Fediverse on UART!" & LF; begin char <= character'pos(example_text(col + 1 - example_text_col)) when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0; red <= std_logic_vector(to_unsigned(col*4, 8)); green <= std_logic_vector(to_unsigned(py, 8)); blue <= std_logic_vector(resize(frame_counter, 8)); foreground_color <= (others => '1'); process(clk) variable old_vsync : std_logic := '0'; variable uart_counter : integer range uart_text'range := 1; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then frame_counter <= frame_counter + 1; end if; old_vsync := vsync; uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8)); uart_valid <= '1'; if uart_ready = '1' and uart_valid = '1' then if uart_counter < uart_text'length then uart_counter := uart_counter + 1; else uart_counter := 1; end if; end if; end if; end process; end architecture;

    Success!

    UART Output

    ... [TRUNCATED] ...
 on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
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Hello Fediverse


    UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1171242884.8%TRELLIS_FF177242880.7%TRELLIS_IO111975.6%
    TimingClockAchievedConstraint$glbnet$clkp39.04 MHz25 MHz$glbnet$clkt345.18 MHz250 MHz
    Code

    library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1');

        uart_data : out std_logic_vector(7 downto 0) := (others => '0');
        uart_ready : in std_logic;
        uart_valid : out std_logic := '0'
    );
end my_code;

architecture rtl of my_code is
    alias red   : std_logic_vector(7 downto 0) is background_color(23 downto 16);
    alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8);
    alias blue  : std_logic_vector(7 downto 0) is background_color(7 downto 0);

    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant example_text : string := "Hello Fediverse! <3";
    constant example_text_row : integer := 15;
    constant example_text_col : integer := 15;

    constant uart_text : string := "Hello Fediverse on UART!" & LF;
begin
    char <= character'pos(example_text(col + 1 - example_text_col))
        when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0;

    red   <= std_logic_vector(to_unsigned(col*4, 8));
    green <= std_logic_vector(to_unsigned(py, 8));
    blue  <= std_logic_vector(resize(frame_counter, 8));

    foreground_color <= (others => '1');

    process(clk)
        variable old_vsync : std_logic := '0';

        variable uart_counter : integer range uart_text'range := 1;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                frame_counter <= frame_counter + 1;
            end if;
            old_vsync := vsync;

            uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8));
            uart_valid <= '1';
            if uart_ready = '1' and uart_valid = '1' then
                if uart_counter < uart_text'length then
                    uart_counter := uart_counter + 1;
                else
                    uart_counter := 1;
                end if;
            end if;
        end if;
    end process;
end architecture;


    #FPGA #Icepi-Zero #HDL #VHDL
    #fpga #icepizero #hdl #vhdl
  48. Icepi Zero Bot @[email protected] ·

    @[email protected]

    @[email protected] asked

    library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1'); uart_data : out std_logic_vector(7 downto 0) := (others => '0'); uart_ready : in std_logic; uart_valid : out std_logic := '0' ); end my_code; architecture rtl of my_code is alias red : std_logic_vector(7 downto 0) is background_color(23 downto 16); alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8); alias blue : std_logic_vector(7 downto 0) is background_color(7 downto 0); signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant example_text : string := "Hello Fediverse! <3"; constant example_text_row : integer := 15; constant example_text_col : integer := 15; constant uart_text : string := "Hello Fediverse on UART!" & LF; begin char <= character'pos(example_text(col + 1 - example_text_col)) when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0; red <= std_logic_vector(to_unsigned(col*4, 8)); green <= std_logic_vector(to_unsigned(py, 8)); blue <= std_logic_vector(resize(frame_counter, 8)); foreground_color <= (others => '1'); process(clk) variable old_vsync : std_logic := '0'; variable uart_counter : integer range uart_text'range := 1; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then frame_counter <= frame_counter + 1; end if; old_vsync := vsync; uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8)); uart_valid <= '1'; if uart_ready = '1' and uart_valid = '1' then if uart_counter < uart_text'length then uart_counter := uart_counter + 1; else uart_counter := 1; end if; end if; end if; end process; end architecture;

    Success!

    UART Output

    ... [TRUNCATED] ...
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    UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1171242884.8%TRELLIS_FF177242880.7%TRELLIS_IO111975.6%
    TimingClockAchievedConstraint$glbnet$clkp39.04 MHz25 MHz$glbnet$clkt345.18 MHz250 MHz
    Code

    library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1');

        uart_data : out std_logic_vector(7 downto 0) := (others => '0');
        uart_ready : in std_logic;
        uart_valid : out std_logic := '0'
    );
end my_code;

architecture rtl of my_code is
    alias red   : std_logic_vector(7 downto 0) is background_color(23 downto 16);
    alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8);
    alias blue  : std_logic_vector(7 downto 0) is background_color(7 downto 0);

    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant example_text : string := "Hello Fediverse! <3";
    constant example_text_row : integer := 15;
    constant example_text_col : integer := 15;

    constant uart_text : string := "Hello Fediverse on UART!" & LF;
begin
    char <= character'pos(example_text(col + 1 - example_text_col))
        when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0;

    red   <= std_logic_vector(to_unsigned(col*4, 8));
    green <= std_logic_vector(to_unsigned(py, 8));
    blue  <= std_logic_vector(resize(frame_counter, 8));

    foreground_color <= (others => '1');

    process(clk)
        variable old_vsync : std_logic := '0';

        variable uart_counter : integer range uart_text'range := 1;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                frame_counter <= frame_counter + 1;
            end if;
            old_vsync := vsync;

            uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8));
            uart_valid <= '1';
            if uart_ready = '1' and uart_valid = '1' then
                if uart_counter < uart_text'length then
                    uart_counter := uart_counter + 1;
                else
                    uart_counter := 1;
                end if;
            end if;
        end if;
    end process;
end architecture;


    #FPGA #Icepi-Zero #HDL #VHDL
    #fpga #icepizero #hdl #vhdl
  49. Icepi Zero Bot @[email protected] ·

    @[email protected]

    @[email protected] asked

    library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1'); uart_data : out std_logic_vector(7 downto 0) := (others => '0'); uart_ready : in std_logic; uart_valid : out std_logic := '0' ); end my_code; architecture rtl of my_code is alias red : std_logic_vector(7 downto 0) is background_color(23 downto 16); alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8); alias blue : std_logic_vector(7 downto 0) is background_color(7 downto 0); signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant example_text : string := "Hello Fediverse! <3"; constant example_text_row : integer := 15; constant example_text_col : integer := 15; constant uart_text : string := "Hello Fediverse on UART!" & LF; begin char <= character'pos(example_text(col + 1 - example_text_col)) when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0; red <= std_logic_vector(to_unsigned(col*4, 8)); green <= std_logic_vector(to_unsigned(py, 8)); blue <= std_logic_vector(resize(frame_counter, 8)); foreground_color <= (others => '1'); process(clk) variable old_vsync : std_logic := '0'; variable uart_counter : integer range uart_text'range := 1; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then frame_counter <= frame_counter + 1; end if; old_vsync := vsync; uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8)); uart_valid <= '1'; if uart_ready = '1' and uart_valid = '1' then if uart_counter < uart_text'length then uart_counter := uart_counter + 1; else uart_counter := 1; end if; end if; end if; end process; end architecture;

    Success!

    UART Output

    ... [TRUNCATED] ...
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    UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1171242884.8%TRELLIS_FF177242880.7%TRELLIS_IO111975.6%
    TimingClockAchievedConstraint$glbnet$clkp39.04 MHz25 MHz$glbnet$clkt345.18 MHz250 MHz
    Code

    library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1');

        uart_data : out std_logic_vector(7 downto 0) := (others => '0');
        uart_ready : in std_logic;
        uart_valid : out std_logic := '0'
    );
end my_code;

architecture rtl of my_code is
    alias red   : std_logic_vector(7 downto 0) is background_color(23 downto 16);
    alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8);
    alias blue  : std_logic_vector(7 downto 0) is background_color(7 downto 0);

    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant example_text : string := "Hello Fediverse! <3";
    constant example_text_row : integer := 15;
    constant example_text_col : integer := 15;

    constant uart_text : string := "Hello Fediverse on UART!" & LF;
begin
    char <= character'pos(example_text(col + 1 - example_text_col))
        when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0;

    red   <= std_logic_vector(to_unsigned(col*4, 8));
    green <= std_logic_vector(to_unsigned(py, 8));
    blue  <= std_logic_vector(resize(frame_counter, 8));

    foreground_color <= (others => '1');

    process(clk)
        variable old_vsync : std_logic := '0';

        variable uart_counter : integer range uart_text'range := 1;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                frame_counter <= frame_counter + 1;
            end if;
            old_vsync := vsync;

            uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8));
            uart_valid <= '1';
            if uart_ready = '1' and uart_valid = '1' then
                if uart_counter < uart_text'length then
                    uart_counter := uart_counter + 1;
                else
                    uart_counter := 1;
                end if;
            end if;
        end if;
    end process;
end architecture;


    #FPGA #Icepi-Zero #HDL #VHDL
    #fpga #icepizero #hdl #vhdl
  50. Icepi Zero Bot @[email protected] ·

    @[email protected]

    @[email protected] asked

    library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1'); uart_data : out std_logic_vector(7 downto 0) := (others => '0'); uart_ready : in std_logic; uart_valid : out std_logic := '0' ); end my_code; architecture rtl of my_code is alias red : std_logic_vector(7 downto 0) is background_color(23 downto 16); alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8); alias blue : std_logic_vector(7 downto 0) is background_color(7 downto 0); signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant example_text : string := "Hello Fediverse! <3"; constant example_text_row : integer := 15; constant example_text_col : integer := 15; constant uart_text : string := "Hello Fediverse on UART!" & LF; begin char <= character'pos(example_text(col + 1 - example_text_col)) when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0; red <= std_logic_vector(to_unsigned(col*4, 8)); green <= std_logic_vector(to_unsigned(py, 8)); blue <= std_logic_vector(resize(frame_counter, 8)); foreground_color <= (others => '1'); process(clk) variable old_vsync : std_logic := '0'; variable uart_counter : integer range uart_text'range := 1; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then frame_counter <= frame_counter + 1; end if; old_vsync := vsync; uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8)); uart_valid <= '1'; if uart_ready = '1' and uart_valid = '1' then if uart_counter < uart_text'length then uart_counter := uart_counter + 1; else uart_counter := 1; end if; end if; end if; end process; end architecture;

    Success!

    UART Output

    ... [TRUNCATED] ...
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    UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1171242884.8%TRELLIS_FF177242880.7%TRELLIS_IO111975.6%
    TimingClockAchievedConstraint$glbnet$clkp39.04 MHz25 MHz$glbnet$clkt345.18 MHz250 MHz
    Code

    library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1');

        uart_data : out std_logic_vector(7 downto 0) := (others => '0');
        uart_ready : in std_logic;
        uart_valid : out std_logic := '0'
    );
end my_code;

architecture rtl of my_code is
    alias red   : std_logic_vector(7 downto 0) is background_color(23 downto 16);
    alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8);
    alias blue  : std_logic_vector(7 downto 0) is background_color(7 downto 0);

    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant example_text : string := "Hello Fediverse! <3";
    constant example_text_row : integer := 15;
    constant example_text_col : integer := 15;

    constant uart_text : string := "Hello Fediverse on UART!" & LF;
begin
    char <= character'pos(example_text(col + 1 - example_text_col))
        when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0;

    red   <= std_logic_vector(to_unsigned(col*4, 8));
    green <= std_logic_vector(to_unsigned(py, 8));
    blue  <= std_logic_vector(resize(frame_counter, 8));

    foreground_color <= (others => '1');

    process(clk)
        variable old_vsync : std_logic := '0';

        variable uart_counter : integer range uart_text'range := 1;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                frame_counter <= frame_counter + 1;
            end if;
            old_vsync := vsync;

            uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8));
            uart_valid <= '1';
            if uart_ready = '1' and uart_valid = '1' then
                if uart_counter < uart_text'length then
                    uart_counter := uart_counter + 1;
                else
                    uart_counter := 1;
                end if;
            end if;
        end if;
    end process;
end architecture;


    #FPGA #Icepi-Zero #HDL #VHDL
    #fpga #icepizero #hdl #vhdl