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#vhdl — Public Fediverse posts

Live and recent posts from across the Fediverse tagged #vhdl, aggregated by home.social.

  1. Pawel @wozniakpawel ·

    I built a browser IDE that runs real open-source EDA tools. Write VHDL or SystemVerilog, hit run: GHDL/Icarus simulates it, Yosys synthesizes it, and you see the waveform and the netlist cell by cell. No install.

    Free fundamentals curriculum + engineering-flavored challenges, and a playground.

    risingedge.pro/

    #fpga #vhdl #verilog
  2. Open Source Electronics Wiki @[email protected] ·

    Which Verilog TMDS encoding library do you recommend that I use on the Ice Pi Zero? Here is my review of the options.

    wiki.pythonlinks.info/dvi-rtl-

    #Verilog #VHDL #tMDS #IcePiZero

    #verilog #vhdl #tmds #icepizero
  3. JCM @[email protected] ·

    @[email protected]

    I am pleased to announce that @icepi-zero-bot is back up and running. :waffy_party:

    Now inside my Kubernetes cluster on more powerful hardware, so you should hopefully see some faster synthesis times and slightly nicer videos!
    I think I secured it pretty well, but if someone manages to do something naughty, please don't nom-nom all my data :pleading_face:
    Also, please don't break my FPGA on purporse, oki? :3

    Sadly, I still need to figure out Spade support, because I couldn't find any prebuilt arm64 binaries for it :(

    So, if you want to write cool SystemVerilog/VHDL/Amaranth/Veryl code, have it run on a real FPGA and output video (no need to implement DVI yourself, dw), which is then recorded and posted, check out @icepi-zero-bot's profile! The profile description contains tons of explanations and templates.

    Soon, I will hopefully add Spade support back and also implement a UART interface, so you can also output text! The support for that in the bot is already there, I just need to implement a UART transmitter in VHDL and think of a cute and easy interface.



    RE: https://wafrn.jcm.re/fediverse/post/83972345-09e4-47d9-99d3-4a3885a2a198
    #fedibot #FPGA #HDL #VHDL #Verilog #SystemVerilog #Amaranth #Veryl
    #fedibot #fpga #hdl #vhdl #verilog #systemverilog
  4. JCM @[email protected] ·

    @[email protected]

    I am pleased to announce that @icepi-zero-bot is back up and running. :waffy_party:

    Now inside my Kubernetes cluster on more powerful hardware, so you should hopefully see some faster synthesis times and slightly nicer videos!
    I think I secured it pretty well, but if someone manages to do something naughty, please don't nom-nom all my data :pleading_face:
    Also, please don't break my FPGA on purporse, oki? :3

    Sadly, I still need to figure out Spade support, because I couldn't find any prebuilt arm64 binaries for it :(

    So, if you want to write cool SystemVerilog/VHDL/Amaranth/Veryl code, have it run on a real FPGA and output video (no need to implement DVI yourself, dw), which is then recorded and posted, check out @icepi-zero-bot's profile! The profile description contains tons of explanations and templates.

    Soon, I will hopefully add Spade support back and also implement a UART interface, so you can also output text! The support for that in the bot is already there, I just need to implement a UART transmitter in VHDL and think of a cute and easy interface.



    RE: https://wafrn.jcm.re/fediverse/post/83972345-09e4-47d9-99d3-4a3885a2a198
    #fedibot #FPGA #HDL #VHDL #Verilog #SystemVerilog #Amaranth #Veryl
    #fedibot #fpga #hdl #vhdl #verilog #systemverilog
  5. poleguy looking for lost tools @[email protected] ·

    Maybe you'll be my new boss? Come work for #Shure doing #FPGA #modem development in our #Wireless lab.

    I've been here 20 years. It's not bad. Ask me anything.

    careersus-shure.icims.com/jobs

    Put down my name and I'll get a referral bonus.

    #engineering #management #python #verilog #vhdl #proaudio #job #jobs #getfedihired #fedijobs #jobsearch #fedihire #illinois #chicago #askmeanything

    #shure #fpga #modem #wireless #engineering #management
  6. poleguy looking for lost tools @[email protected] ·

    Maybe you'll be my new boss? Come work for #Shure doing #FPGA #modem development in our #Wireless lab.

    I've been here 20 years. It's not bad. Ask me anything.

    careersus-shure.icims.com/jobs

    Put down my name and I'll get a referral bonus.

    #engineering #management #python #verilog #vhdl #proaudio #job #jobs #getfedihired #fedijobs #jobsearch #fedihire #illinois #chicago #askmeanything

    #shure #fpga #modem #wireless #engineering #management
  7. Habr @[email protected] ·

    Перепрыгивание с языка на язык как тактика прохождения интервью

    В 2010 году я участвовал в интервьировании на позицию по моделированию и верификации процессорных ядер. Один из кандидатов был благообразный седой американец, который до этого работал в IBM. Я задал вопрос про язык описания и верификации аппаратуры SystemVerilog. На это кандидат сказал, что он еще не освоил SystemVerilog, вписал его в резюме на будущее, но вообще использовал Verilog-95 и немного Verilog-2001. “Нет проблем”, - сказал я и задал вопрос по Verilog-95: “приведите примеры гонок (race conditions) при испрользовании верилога”. На это кандидат сказал, что вообще его опыт был больше связан с VHDL. “Блин, как он выкрутился” - подумал я, ведь в VHDL нет гонок как в верилоге из-за дизайна языка.

    habr.com/ru/articles/1033360/

    #SystemVerilog #verilog #Ada #VHDL #Jovial #Coral66 #IBM #Стенфорд #вопросы_на_собеседовании #внешний_вид

    #внешний_вид #вопросы_на_собеседовании #стенфорд #ibm #coral66 #jovial
  8. PipelineC @[email protected] ·

    Fun in the frequency domain 🤓 Camera pointed at it's own display also showing audio FFT for cool glitchy visualizer effect. Video processing all done in PipelineC hardware. And how?

    github.com/JulianKemmerer/Pipe

    #hardware #fpga #dsp #rtl #hdl #hls #verilog #vhdl #pipelinec

    #hardware #fpga #dsp #rtl #hdl #hls
  9. Gray Beard @[email protected] ·

    SystemLisp - an HDL simulator written in Common Lisp

    github.com/systemlisp

    #lisp #commonlisp #hdl #rtl #verilog #design #verification #vhdl #systemverilog #vlsi #programming #fpga

    #lisp #commonlisp #hdl #rtl #verilog #design
  10. cnx-software.com [Unofficial] @[email protected] ·

    AERIS-10 open-source hardware radar can track multiple objects up to 20km away

    web.brid.gy/r/https://www.cnx-

    #hardware #stmicrostm32 #xilinxartix #diy #fpga #military
  11. cnx-software.com [Unofficial] @[email protected] ·

    AERIS-10 open-source hardware radar can track multiple objects up to 20km away

    web.brid.gy/r/https://www.cnx-

    #hardware #stmicrostm32 #xilinxartix #diy #fpga #military
  12. PipelineC @[email protected] ·

    @nlnetlabs.bsky.social NLnet Foundation funded open source WireGuard router in FPGA. Featuring PipelineC for cryptography blocks 🤓 github.com/JulianKemmer... #hardware #fpga #rtl #hdl #hls #verilog #vhdl #cryptography #wireguard #pipelinec

    #hardware #fpga #rtl #hdl #hls #verilog
  13. PipelineC @[email protected] ·

    @nlnet NLnet Foundation funded open source WireGuard router in FPGA. Featuring PipelineC for cryptography blocks 🤓

    github.com/JulianKemmerer/Pipe

    #hardware #fpga #rtl #hdl #hls #verilog #vhdl #cryptography #wireguard #pipelinec

    #hardware #fpga #rtl #hdl #hls #verilog
  14. poleguy looking for lost tools @[email protected] ·

    New blog post.

    poleguy.com/blog/john-henry-an

    #AI #NoAI #AIcritic #slop #FPGA #verilog #vhdl

    #ai #noai #aicritic #slop #fpga #verilog
  15. PipelineC @[email protected] ·

    PipelineC holds the throughput lead on Latchup.app. For now! How does your design stack up against a pipelining tool? Far too time consuming and fun of a site 🤓 Look forward to seeing competing solutions.

    github.com/JulianKemmerer/Pipe

    #fpga #asic #rtl #hdl #verilog #vhdl #hls #eda

    #fpga #asic #rtl #hdl #verilog #vhdl
  16. poleguy looking for lost tools @[email protected] ·

    Start rtl counter with a timer that is initialized 10 seconds from a 32bit wrap point so that the software handling of wrap-around is well exercised during development.

    #rtl #fpga #verilog #vhdl #xilinx #alchitry #eureka #protonpack #software #softwaredevelopment #hardware #embedded #fensterFreitag

    #rtl #fpga #verilog #vhdl #xilinx #alchitry
  17. Patrick :neocat_flag_bi: @[email protected] ·

    One Open-source Project Daily

    Digital logic design tool and simulator

    https://github.com/logisim-evolution/logisim-evolution

    #1ospd #opensource #circuit #circuits #digitalcircuit #digitalcircuits #digitallogic #digitallogicdesign #education #fpga #logic #logisim #logisimevolution #simulator #timingdiagram #verilog #vhdl

    #1ospd #opensource #circuit #circuits #digitalcircuit #digitalcircuits
  18. JCM @[email protected] ·

    Small update announcement for the @icepi-zero-bot (that you might have noticed already):

    • The bot now reports details about utilization and clock speeds together with the video in the success post.
    • You can split your code into multiple messages if your instance has a low character limit for direct messages (see the bot's description for more details).

    For the future, I plan to:

    • Add support for more HDLs (tell me your favorite ones and I try to integrate them).
    • Support for outputting text via UART, that the host will capture and include in the success post.

    If you have any other ideas/wishes, feel free to tell me :D


    #FPGA #bot #fedibot #Icepi-Zero #VHDL #Verilog #SystemVerilog #Amaranth
    #fpga #bot #fedibot #icepizero #vhdl #verilog
  19. JCM @[email protected] ·

    Small update announcement for the @icepi-zero-bot (that you might have noticed already):

    • The bot now reports details about utilization and clock speeds together with the video in the success post.
    • You can split your code into multiple messages if your instance has a low character limit for direct messages (see the bot's description for more details).

    For the future, I plan to:

    • Add support for more HDLs (tell me your favorite ones and I try to integrate them).
    • Support for outputting text via UART, that the host will capture and include in the success post.

    If you have any other ideas/wishes, feel free to tell me :D


    #FPGA #bot #fedibot #Icepi-Zero #VHDL #Verilog #SystemVerilog #Amaranth
    #fpga #bot #fedibot #icepizero #vhdl #verilog
  20. JCM @[email protected] ·

    Small update announcement for the @icepi-zero-bot (that you might have noticed already):

    • The bot now reports details about utilization and clock speeds together with the video in the success post.
    • You can split your code into multiple messages if your instance has a low character limit for direct messages (see the bot's description for more details).

    For the future, I plan to:

    • Add support for more HDLs (tell me your favorite ones and I try to integrate them).
    • Support for outputting text via UART, that the host will capture and include in the success post.

    If you have any other ideas/wishes, feel free to tell me :D


    #FPGA #bot #fedibot #Icepi-Zero #VHDL #Verilog #SystemVerilog #Amaranth
    #fpga #bot #fedibot #icepizero #vhdl #verilog
  21. JCM @[email protected] ·

    Small update announcement for the @icepi-zero-bot (that you might have noticed already):

    • The bot now reports details about utilization and clock speeds together with the video in the success post.
    • You can split your code into multiple messages if your instance has a low character limit for direct messages (see the bot's description for more details).

    For the future, I plan to:

    • Add support for more HDLs (tell me your favorite ones and I try to integrate them).
    • Support for outputting text via UART, that the host will capture and include in the success post.

    If you have any other ideas/wishes, feel free to tell me :D


    #FPGA #bot #fedibot #Icepi-Zero #VHDL #Verilog #SystemVerilog #Amaranth
    #amaranth #systemverilog #verilog #vhdl #icepizero #fedibot