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  1. Klaus Frank @[email protected] ·

    What do you think, how well will trying to #vibecode #VHDL go?

    It sounds so dumb that I kinda want to try it out now*...

    * and maybe I will once I find some AI company claiming they can do it which probably doesn't take long AND where I don't have to pay anything.

    #vibecode #vhdl
  2. Paul Förster :verified_blue: @[email protected] ·

    I found this #VIC20 project repository on #GitHub for the #MEGA65. The xpr files in the CORE directory of the repository seem to be #Xilinx project files. Lacking know how and resources, I can’t turn these into core files for the MEGA 65.

    Could some kind soul please do that and upload the core files? I’d love to have a VIC-20 core for the MEGA 65. 🙏

    github.com/MJoergen/VIC20MEGA65

    #Commodore #Emulation #VHDL

    #vic20 #github #mega65 #xilinx #commodore #emulation
  3. Vladimir Vargas Cordero 🇨🇷 🙏🪷 @vladimirvc ·

    ELM11-Feather Is a Feather-Compatible Board That Speaks Lua Natively

    itsfoss.com/news/elm11-feather

    #fpga #lua #vhdl
  4. Pawel @wozniakpawel ·

    I built a browser IDE that runs real open-source EDA tools. Write VHDL or SystemVerilog, hit run: GHDL/Icarus simulates it, Yosys synthesizes it, and you see the waveform and the netlist cell by cell. No install.

    Free fundamentals curriculum + engineering-flavored challenges, and a playground.

    risingedge.pro/

    #fpga #vhdl #verilog
  5. Open Source Electronics Wiki @[email protected] ·

    Which Verilog TMDS encoding library do you recommend that I use on the Ice Pi Zero? Here is my review of the options.

    wiki.pythonlinks.info/dvi-rtl-

    #Verilog #VHDL #tMDS #IcePiZero

    #verilog #vhdl #tmds #icepizero
  6. Icepi Zero Bot @[email protected] ·

    @[email protected] asked

    library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1'); uart_data : out std_logic_vector(7 downto 0) := (others => '0'); uart_ready : in std_logic; uart_valid : out std_logic := '0' ); end my_code; architecture rtl of my_code is constant IMAGE_WIDTH : integer := 32; constant IMAGE_HEIGHT : integer := 25; type image_type is array (IMAGE_HEIGHT*IMAGE_WIDTH*12-1 downto 0) of std_logic; constant image : image_type := x"00000000000000000000000000000000000000000000000123400000000000111200000000000000000000000000000000000000000000000000000000000000000000000000044645700000000022344700000000000000000000000000000000000000000000000000000000000000000000000000056845700100000033556800100000000000000000000000000000000000000000000000000000000000000000000000145744611100000034555800000000000000000000000000000000000000000000000000000000000000000000000000033533522423422444633500011075364300000000000000000000000000000000000000000000000000000000000000012334568979b457345123000964eb7da73211100000000000000000000000000000000000000000000000000000000003448abaddadd8ab79a578211c86fa7fa7c86c867430000000000000000000000000000000000000000000000000000005788bcaddadd8ab8ab689777eddebae96f96f9696400000000000000000000000000000000000000000000000011122289a89a9cdadd9aaabb79a777cccca9d85d85b643100000000000000000000000000000000000000000000002217657659aaabcacdaddbcdbcd7ab456888866754532210000000000000000000000000000000000000000000000000332765765789acdadeaddadd9cd58923444522200000011133333300000000000000000000000000000000000000000011154377688978a9bcacd9cc7ac7ad347000000433999bbbddcaaa0000000000000000000000000000000000000000001223443452235679bcabc9bc9ab68b46a124444bbbeddeedddd7770000000000000000000000000000000000000005679bd7ac78b769678cdddeecddacc7ae47a567888cccdddccc8881110000000000001110000000000003333331111115668ab69b89c88a668bcddeecee9bc67b56a99bcccaaa999555111111000000555aaacccbbb333222777eeeeeeccccdddddbbb445abceefeffeeeeeeeeedeedeeddebbcbbcdddeeebbbbbbcccbbb666dddeffdeffffdddccceeedefbdfeffdefbeffff999cccdefadfbefcefdefcefbefbefdeeeefadfbefffffffcefeffcccfffadf4cfdeffffdefeffbdf4cfadf3cf3cfbefeeedddbdf3bf3cf4cf6cf3cf5cf4cf7cfcef4cf4cfdefdff5cfbefdddcccdef3cf9dfdef4cfbdf9df4cf7cf3cf4cf6cfefffffadf4cfadfcef9df4cfdefadf2bf9df4cf3cf8cfdef4cfcefccd888fff9df3bf9cf3af7bf6af5af5af7bfadf3afadffff8cf2bf3bfcefadf3bfadf8cf3bfbdf4bf9cf5bf7bf3afdefbbb444ddddef48f37f47f37f26f58f37f57fbcf89f47fcdf79f79fbdfeffbcf38f6af49f38fabf48fbcf9af27f37feefaaa000aaafff79f37fbcf57f37f8af37f68fccfddf57f89f58f9bfffffffbcf37fddfddf47f57f47fbcfddf37f47ffff999000344eeeddfbcfeffddfcdfdefabfeefffffffdefeefddfeefddeccdddf9afeeffffddfddfddfeeffffbcfbcffff77800000099aeeeeeeddeddeddeeeeeefdee89abbcddeccdddddde99a99aeeffffeefdddeeeddeddeccdcddeeefffddd45600000022456866845745745755767956822423544723534645723433477978a679446567457446346346568679558112"; constant SPEED : integer := 8; signal position_x : integer range -SPEED to WIDTH + SPEED := 0; signal position_y : integer range -SPEED to HEIGHT + SPEED := 0; signal random_bit : std_logic := '0'; signal color : std_logic_vector(23 downto 0) := x"FFFFFF"; component OSCG is generic ( DIV : integer := 128 ); port ( OSC : out std_logic ); end component; signal pos : integer range 0 to IMAGE_HEIGHT*IMAGE_WIDTH*12; signal r, g, b : std_logic_vector(3 downto 0); begin char <= 0; pos <= IMAGE_HEIGHT*IMAGE_WIDTH*12 - 1 - 12*(py - position_y)*(px - position_x); r <= image(pos) & image(pos - 1) & image(pos - 2) & image(pos - 3); g <= image(pos - 4) & image(pos - 5) & image(pos - 6) & image(pos - 7); b <= image(pos - 8) & image(pos - 9) & image(pos - 10) & image(pos - 11); background_color <= r & r & g & g & b & b when px >= position_x and px < position_x + IMAGE_WIDTH and py >= position_y and py < position_y + IMAGE_HEIGHT else x"000000"; foreground_color <= (others => '1'); rng : OSCG port map ( OSC => random_bit ); process(clk) variable old_vsync : std_logic := '0'; variable speed_x : integer range -SPEED to SPEED := SPEED; variable speed_y : integer range -SPEED to SPEED := SPEED; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then if position_x + speed_x + IMAGE_WIDTH >= WIDTH then speed_x := -SPEED; position_x <= WIDTH - IMAGE_WIDTH - 1; color <= color(22 downto 0) & random_bit; elsif position_x + speed_x < 0 then speed_x := SPEED; position_x <= 0; color <= color(22 downto 0) & random_bit; else position_x <= position_x + speed_x; end if; if position_y + speed_y + IMAGE_HEIGHT >= HEIGHT then speed_y := -SPEED; position_y <= HEIGHT - IMAGE_HEIGHT - 1; color <= color(22 downto 0) & random_bit; elsif position_y + speed_y < 0 then speed_y := SPEED; position_y <= 0; color <= color(22 downto 0) & random_bit; else position_y <= position_y + speed_y; end if; end if; old_vsync := vsync; end if; end process; end architecture;

    Success!

    UART Output


    UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%MULT18X18D2287.1%TRELLIS_COMB29372428812.1%TRELLIS_FF160242880.7%TRELLIS_IO111975.6%
    TimingClockAchievedConstraint$glbnet$clkp30.03 MHz25 MHz$glbnet$clkt341.41 MHz250 MHz
    Code

    library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1');

        uart_data : out std_logic_vector(7 downto 0) := (others => '0');
        uart_ready : in std_logic;
        uart_valid : out std_logic := '0'
    );
end my_code;

architecture rtl of my_code is
    constant IMAGE_WIDTH : integer := 32;
    constant IMAGE_HEIGHT : integer := 25;

    type image_type is array (IMAGE_HEIGHT*IMAGE_WIDTH*12-1 downto 0) of std_logic;
    constant image : image_type := x"00000000000000000000000000000000000000000000000123400000000000111200000000000000000000000000000000000000000000000000000000000000000000000000044645700000000022344700000000000000000000000000000000000000000000000000000000000000000000000000056845700100000033556800100000000000000000000000000000000000000000000000000000000000000000000000145744611100000034555800000000000000000000000000000000000000000000000000000000000000000000000000033533522423422444633500011075364300000000000000000000000000000000000000000000000000000000000000012334568979b457345123000964eb7da73211100000000000000000000000000000000000000000000000000000000003448abaddadd8ab79a578211c86fa7fa7c86c867430000000000000000000000000000000000000000000000000000005788bcaddadd8ab8ab689777eddebae96f96f9696400000000000000000000000000000000000000000000000011122289a89a9cdadd9aaabb79a777cccca9d85d85b643100000000000000000000000000000000000000000000002217657659aaabcacdaddbcdbcd7ab456888866754532210000000000000000000000000000000000000000000000000332765765789acdadeaddadd9cd58923444522200000011133333300000000000000000000000000000000000000000011154377688978a9bcacd9cc7ac7ad347000000433999bbbddcaaa0000000000000000000000000000000000000000001223443452235679bcabc9bc9ab68b46a124444bbbeddeedddd7770000000000000000000000000000000000000005679bd7ac78b769678cdddeecddacc7ae47a567888cccdddccc8881110000000000001110000000000003333331111115668ab69b89c88a668bcddeecee9bc67b56a99bcccaaa999555111111000000555aaacccbbb333222777eeeeeeccccdddddbbb445abceefeffeeeeeeeeedeedeeddebbcbbcdddeeebbbbbbcccbbb666dddeffdeffffdddccceeedefbdfeffdefbeffff999cccdefadfbefcefdefcefbefbefdeeeefadfbefffffffcefeffcccfffadf4cfdeffffdefeffbdf4cfadf3cf3cfbefeeedddbdf3bf3cf4cf6cf3cf5cf4cf7cfcef4cf4cfdefdff5cfbefdddcccdef3cf9dfdef4cfbdf9df4cf7cf3cf4cf6cfefffffadf4cfadfcef9df4cfdefadf2bf9df4cf3cf8cfdef4cfcefccd888fff9df3bf9cf3af7bf6af5af5af7bfadf3afadffff8cf2bf3bfcefadf3bfadf8cf3bfbdf4bf9cf5bf7bf3afdefbbb444ddddef48f37f47f37f26f58f37f57fbcf89f47fcdf79f79fbdfeffbcf38f6af49f38fabf48fbcf9af27f37feefaaa000aaafff79f37fbcf57f37f8af37f68fccfddf57f89f58f9bfffffffbcf37fddfddf47f57f47fbcfddf37f47ffff999000344eeeddfbcfeffddfcdfdefabfeefffffffdefeefddfeefddeccdddf9afeeffffddfddfddfeeffffbcfbcffff77800000099aeeeeeeddeddeddeeeeeefdee89abbcddeccdddddde99a99aeeffffeefdddeeeddeddeccdcddeeefffddd45600000022456866845745745755767956822423544723534645723433477978a679446567457446346346568679558112";

    constant SPEED : integer := 8;

    signal position_x : integer range -SPEED to WIDTH + SPEED := 0;
    signal position_y : integer range -SPEED to HEIGHT + SPEED := 0;

    signal random_bit : std_logic := '0';
    signal color : std_logic_vector(23 downto 0) := x"FFFFFF";

    component OSCG is
        generic (
            DIV : integer := 128
        );
        port (
            OSC : out std_logic
        );
    end component;

    signal pos : integer range 0 to IMAGE_HEIGHT*IMAGE_WIDTH*12;
    signal r, g, b : std_logic_vector(3 downto 0);
begin
    char <= 0;

    pos <= IMAGE_HEIGHT*IMAGE_WIDTH*12 - 1 - 12*(py - position_y)*(px - position_x);
    r <= image(pos) & image(pos - 1) & image(pos - 2) & image(pos - 3);
    g <= image(pos - 4) & image(pos - 5) & image(pos - 6) & image(pos - 7);
    b <= image(pos - 8) & image(pos - 9) & image(pos - 10) & image(pos - 11);

    background_color <= r & r & g & g & b & b
        when
            px >= position_x and px < position_x + IMAGE_WIDTH and
            py >= position_y and py < position_y + IMAGE_HEIGHT
        else x"000000";
    foreground_color <= (others => '1');

    rng : OSCG port map (
        OSC => random_bit
    );

    process(clk)
        variable old_vsync : std_logic := '0';
        variable speed_x : integer range -SPEED to SPEED := SPEED;
        variable speed_y : integer range -SPEED to SPEED := SPEED;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                if position_x + speed_x + IMAGE_WIDTH >= WIDTH then
                    speed_x := -SPEED;
                    position_x <= WIDTH - IMAGE_WIDTH - 1;

                    color <= color(22 downto 0) & random_bit;
                elsif position_x + speed_x < 0 then
                    speed_x := SPEED;
                    position_x <= 0;

                    color <= color(22 downto 0) & random_bit;
                else
                    position_x <= position_x + speed_x;
                end if;

                if position_y + speed_y + IMAGE_HEIGHT >= HEIGHT then
                    speed_y := -SPEED;
                    position_y <= HEIGHT - IMAGE_HEIGHT - 1;

                    color <= color(22 downto 0) & random_bit;
                elsif position_y + speed_y < 0 then
                    speed_y := SPEED;
                    position_y <= 0;

                    color <= color(22 downto 0) & random_bit;
                else
                    position_y <= position_y + speed_y;
                end if;
            end if;
            old_vsync := vsync;
        end if;
    end process;
end architecture;


    #FPGA #Icepi-Zero #HDL #VHDL
    #fpga #icepizero #hdl #vhdl
  7. Icepi Zero Bot @[email protected] ·

    @[email protected]

    @[email protected] asked

    library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1') ); end my_code; architecture rtl of my_code is constant IMAGE_WIDTH : integer := 117; constant IMAGE_HEIGHT : integer := 52; type image_type is array (0 to IMAGE_HEIGHT-1) of std_logic_vector(0 to IMAGE_WIDTH-1); constant image : image_type := ( "000000000111111111111111111111111111111111111111111111000000000000000000011111111111111111111111111111111100000000000", "000000000111111111111111111111111111111111111111111111000000000000000000111111111111111111111111111111111111100000000", "000000000111111111111111111111111111111111111111111111000000000000000001111111111111111111111111111111111111111000000", "000000000111111111111111111111111111111111111111111111100000000000000011111111111111111111111111111111111111111110000", "000000001111111111111111111111111111111111111111111111100000000000000011111111111111111111111111111111111111111111000", "000000001111111111111111111111111111111111111111111111100000000000000111111111111111111111111111111111111111111111100", "000000001111111111111111111111111111111111111111111111110000000000001111111111111111111111111111111111111111111111110", "000000001111111111110000000111111111111111111111111111110000000000011111111111111111111111110000000111111111111111111", "000000011111111111110000000000111111111111111111111111110000000000011111111111111111111111110000000000111111111111111", "000000011111111111110000000000011111111111111111111111111000000000111111111111111111111111110000000000011111111111111", "000000011111111111100000000000001111111111111111111111111000000001111111111111011111111111100000000000001111111111111", "000000011111111111100000000000000111111111111011111111111000000011111111111110011111111111100000000000000111111111111", "000000111111111111100000000000000111111111111011111111111100000111111111111100111111111111100000000000000111111111111", "000000111111111111100000000000000111111111111011111111111100000111111111111000111111111111100000000000000111111111111", "000000111111111111000000000000001111111111111001111111111100001111111111110000111111111111100000000000001111111111111", "000000111111111111000000000000001111111111111001111111111110011111111111110000111111111111000000000000001111111111111", "000001111111111111000000000000001111111111110001111111111110111111111111100000111111111111000000000000001111111111111", "000001111111111111000000000000011111111111110000111111111110111111111111000001111111111111000000000000011111111111110", "000001111111111111000000000000111111111111110000111111111111111111111110000001111111111111000000000000111111111111110", "000001111111111110000000000001111111111111100000111111111111111111111100000001111111111110000000000001111111111111100", "000001111111111110000000000111111111111111000000011111111111111111111000000001111111111110000000000111111111111111000", "000011111111111110000000111111111111111110000000011111111111111111110000000011111111111110000000111111111111111110000", "000011111111111111111111111111111111111100000000011111111111111111100000000011111111111111111111111111111111111100000", "000011111111111111111111111111111111111000000000001111111111111111100000000011111111111111111111111111111111111000000", "000011111111111111111111111111111111110000000000001111111111111111000000000011111111111111111111111111111111110000000", "000111111111111111111111111111111111000000000000000111111111111110000000000111111111111111111111111111111111000000000", "000111111111111111111111111111111100000000000000000111111111111100000000000111111111111111111111111111111100000000000", "000111111111111111111111111111100000000000000000000111111111111000000000000111111111111111111111111111100000000000000", "000111111111111111111111111100000000000000000000000011111111110000000000000111111111111111111111111100000000000000000", "000111111111111111111100000000000000000000000000000011111111100000000000000111111111111111111100000000000000000000000", "000000000000000000000000000000000000000000000000000011111111100000000000000000000000000000000000000000000000000000000", "000000000000000000000000000000000000000000000000000001111111000000000000000000000000000000000000000000000000000000000", "000000000000000000000000000000000000000000000000000001111110000000000000000000000000000000000000000000000000000000000", "000000000000000000000000000000000000000000000000000001111100000000000000000000000000000000000000000000000000000000000", "000000000000000000000000000000000000000000000000000000111000000000000000000000000000000000000000000000000000000000000", "000000000000000000000000000000000000000000000000000000110000000000000000000000000000000000000000000000000000000000000", "000000000000000000000000000001111111111111111111111111111111111111111111111111111000000000000000000000000000000000000", "000000000000000000011111111111111111111111111111111111111111111111111111111111111111111111100000000000000000000000000", "000000000000111111111111111111111111111111111111111111111111111111111111111111111111111111111111110000000000000000000", "000000011111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100000000000000", "000011111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110000000000", "011111111111111111111110011111001111111001111111000000011111111100000011111111100000001111111111111111111111100000000", "111111111111111111111110011111001111111001111111001111001111111100111111111111001111100111111111111111111111110000000", "111111111111111111111111001110011111111001111111001111100111111100111111111110011111110011111111111111111111111000000", "111111111111111111111111101100111111111001111111001111100111111100000011111110011111110011111111111111111111111000000", "111111111111111111111111100101111111111001111111001111100111111100111111111110011111110011111111111111111111110000000", "011111111111111111111111110001111111111001111111001111001111111100111111111111001111100111111111111111111111100000000", "000011111111111111111111111011111111111001111111000000011111111100000011111111100000001111111111111111111110000000000", "000000011111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100000000000000", "000000000000111111111111111111111111111111111111111111111111111111111111111111111111111111111111110000000000000000000", "000000000000000000011111111111111111111111111111111111111111111111111111111111111111111111110000000000000000000000000", "000000000000000000000000000001111111111111111111111111111111111111111111111111111100000000000000000000000000000000000" ); constant SPEED : integer := 8; signal position_x : integer range -SPEED to WIDTH + SPEED := 0; signal position_y : integer range -SPEED to HEIGHT + SPEED := 0; signal random_bit : std_logic := '0'; signal color : std_logic_vector(23 downto 0) := x"FFFFFF"; component OSCG is generic ( DIV : integer := 128 ); port ( OSC : out std_logic ); end component; begin char <= 0; background_color <= color when image(py - position_y)(px - position_x) = '1' and px >= position_x and px < position_x + IMAGE_WIDTH and py >= position_y and py < position_y + IMAGE_HEIGHT else x"000000"; foreground_color <= (others => '1'); rng : OSCG port map ( OSC => random_bit ); process(clk) variable old_vsync : std_logic := '0'; variable speed_x : integer range -SPEED to SPEED := SPEED; variable speed_y : integer range -SPEED to SPEED := SPEED; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then if position_x + speed_x + IMAGE_WIDTH >= WIDTH then speed_x := -SPEED; position_x <= WIDTH - IMAGE_WIDTH - 1; color <= color(22 downto 0) & random_bit; elsif position_x + speed_x < 0 then speed_x := SPEED; position_x <= 0; color <= color(22 downto 0) & random_bit; else position_x <= position_x + speed_x; end if; if position_y + speed_y + IMAGE_HEIGHT >= HEIGHT then speed_y := -SPEED; position_y <= HEIGHT - IMAGE_HEIGHT - 1; color <= color(22 downto 0) & random_bit; elsif position_y + speed_y < 0 then speed_y := SPEED; position_y <= 0; color <= color(22 downto 0) & random_bit; else position_y <= position_y + speed_y; end if; end if; old_vsync := vsync; end if; end process; end architecture;

    Success!

    UART Output


    UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%MULT18X18D1283.6%OSCG11100.0%TRELLIS_COMB1447242886.0%TRELLIS_FF180242880.7%TRELLIS_IO101975.1%
    TimingClockAchievedConstraint$glbnet$clkp34.93 MHz25 MHz$glbnet$clkt319.28 MHz250 MHz
    Code

    library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1')
    );
end my_code;

architecture rtl of my_code is
    constant IMAGE_WIDTH : integer := 117;
    constant IMAGE_HEIGHT : integer := 52;

    type image_type is array (0 to IMAGE_HEIGHT-1) of std_logic_vector(0 to IMAGE_WIDTH-1);
    constant image : image_type := (
"000000000111111111111111111111111111111111111111111111000000000000000000011111111111111111111111111111111100000000000",
"000000000111111111111111111111111111111111111111111111000000000000000000111111111111111111111111111111111111100000000",
"000000000111111111111111111111111111111111111111111111000000000000000001111111111111111111111111111111111111111000000",
"000000000111111111111111111111111111111111111111111111100000000000000011111111111111111111111111111111111111111110000",
"000000001111111111111111111111111111111111111111111111100000000000000011111111111111111111111111111111111111111111000",
"000000001111111111111111111111111111111111111111111111100000000000000111111111111111111111111111111111111111111111100",
"000000001111111111111111111111111111111111111111111111110000000000001111111111111111111111111111111111111111111111110",
"000000001111111111110000000111111111111111111111111111110000000000011111111111111111111111110000000111111111111111111",
"000000011111111111110000000000111111111111111111111111110000000000011111111111111111111111110000000000111111111111111",
"000000011111111111110000000000011111111111111111111111111000000000111111111111111111111111110000000000011111111111111",
"000000011111111111100000000000001111111111111111111111111000000001111111111111011111111111100000000000001111111111111",
"000000011111111111100000000000000111111111111011111111111000000011111111111110011111111111100000000000000111111111111",
"000000111111111111100000000000000111111111111011111111111100000111111111111100111111111111100000000000000111111111111",
"000000111111111111100000000000000111111111111011111111111100000111111111111000111111111111100000000000000111111111111",
"000000111111111111000000000000001111111111111001111111111100001111111111110000111111111111100000000000001111111111111",
"000000111111111111000000000000001111111111111001111111111110011111111111110000111111111111000000000000001111111111111",
"000001111111111111000000000000001111111111110001111111111110111111111111100000111111111111000000000000001111111111111",
"000001111111111111000000000000011111111111110000111111111110111111111111000001111111111111000000000000011111111111110",
"000001111111111111000000000000111111111111110000111111111111111111111110000001111111111111000000000000111111111111110",
"000001111111111110000000000001111111111111100000111111111111111111111100000001111111111110000000000001111111111111100",
"000001111111111110000000000111111111111111000000011111111111111111111000000001111111111110000000000111111111111111000",
"000011111111111110000000111111111111111110000000011111111111111111110000000011111111111110000000111111111111111110000",
"000011111111111111111111111111111111111100000000011111111111111111100000000011111111111111111111111111111111111100000",
"000011111111111111111111111111111111111000000000001111111111111111100000000011111111111111111111111111111111111000000",
"000011111111111111111111111111111111110000000000001111111111111111000000000011111111111111111111111111111111110000000",
"000111111111111111111111111111111111000000000000000111111111111110000000000111111111111111111111111111111111000000000",
"000111111111111111111111111111111100000000000000000111111111111100000000000111111111111111111111111111111100000000000",
"000111111111111111111111111111100000000000000000000111111111111000000000000111111111111111111111111111100000000000000",
"000111111111111111111111111100000000000000000000000011111111110000000000000111111111111111111111111100000000000000000",
"000111111111111111111100000000000000000000000000000011111111100000000000000111111111111111111100000000000000000000000",
"000000000000000000000000000000000000000000000000000011111111100000000000000000000000000000000000000000000000000000000",
"000000000000000000000000000000000000000000000000000001111111000000000000000000000000000000000000000000000000000000000",
"000000000000000000000000000000000000000000000000000001111110000000000000000000000000000000000000000000000000000000000",
"000000000000000000000000000000000000000000000000000001111100000000000000000000000000000000000000000000000000000000000",
"000000000000000000000000000000000000000000000000000000111000000000000000000000000000000000000000000000000000000000000",
"000000000000000000000000000000000000000000000000000000110000000000000000000000000000000000000000000000000000000000000",
"000000000000000000000000000001111111111111111111111111111111111111111111111111111000000000000000000000000000000000000",
"000000000000000000011111111111111111111111111111111111111111111111111111111111111111111111100000000000000000000000000",
"000000000000111111111111111111111111111111111111111111111111111111111111111111111111111111111111110000000000000000000",
"000000011111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100000000000000",
"000011111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110000000000",
"011111111111111111111110011111001111111001111111000000011111111100000011111111100000001111111111111111111111100000000",
"111111111111111111111110011111001111111001111111001111001111111100111111111111001111100111111111111111111111110000000",
"111111111111111111111111001110011111111001111111001111100111111100111111111110011111110011111111111111111111111000000",
"111111111111111111111111101100111111111001111111001111100111111100000011111110011111110011111111111111111111111000000",
"111111111111111111111111100101111111111001111111001111100111111100111111111110011111110011111111111111111111110000000",
"011111111111111111111111110001111111111001111111001111001111111100111111111111001111100111111111111111111111100000000",
"000011111111111111111111111011111111111001111111000000011111111100000011111111100000001111111111111111111110000000000",
"000000011111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100000000000000",
"000000000000111111111111111111111111111111111111111111111111111111111111111111111111111111111111110000000000000000000",
"000000000000000000011111111111111111111111111111111111111111111111111111111111111111111111110000000000000000000000000",
"000000000000000000000000000001111111111111111111111111111111111111111111111111111100000000000000000000000000000000000"
    );

    constant SPEED : integer := 8;

    signal position_x : integer range -SPEED to WIDTH + SPEED := 0;
    signal position_y : integer range -SPEED to HEIGHT + SPEED := 0;

    signal random_bit : std_logic := '0';
    signal color : std_logic_vector(23 downto 0) := x"FFFFFF";

    component OSCG is
        generic (
            DIV : integer := 128
        );
        port (
            OSC : out std_logic
        );
    end component;
begin
    char <= 0;

    background_color <= color when image(py - position_y)(px - position_x) = '1' and
            px >= position_x and px < position_x + IMAGE_WIDTH and
            py >= position_y and py < position_y + IMAGE_HEIGHT
        else x"000000";
    foreground_color <= (others => '1');

    rng : OSCG port map (
        OSC => random_bit
    );

    process(clk)
        variable old_vsync : std_logic := '0';
        variable speed_x : integer range -SPEED to SPEED := SPEED;
        variable speed_y : integer range -SPEED to SPEED := SPEED;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                if position_x + speed_x + IMAGE_WIDTH >= WIDTH then
                    speed_x := -SPEED;
                    position_x <= WIDTH - IMAGE_WIDTH - 1;

                    color <= color(22 downto 0) & random_bit;
                elsif position_x + speed_x < 0 then
                    speed_x := SPEED;
                    position_x <= 0;

                    color <= color(22 downto 0) & random_bit;
                else
                    position_x <= position_x + speed_x;
                end if;

                if position_y + speed_y + IMAGE_HEIGHT >= HEIGHT then
                    speed_y := -SPEED;
                    position_y <= HEIGHT - IMAGE_HEIGHT - 1;

                    color <= color(22 downto 0) & random_bit;
                elsif position_y + speed_y < 0 then
                    speed_y := SPEED;
                    position_y <= 0;

                    color <= color(22 downto 0) & random_bit;
                else
                    position_y <= position_y + speed_y;
                end if;
            end if;
            old_vsync := vsync;
        end if;
    end process;
end architecture;


    #FPGA #Icepi-Zero #HDL #VHDL
    #fpga #icepizero #hdl #vhdl
  8. poleguy looking for lost tools @[email protected] ·

    Maybe you'll be my new boss? Come work for #Shure doing #FPGA #modem development in our #Wireless lab.

    I've been here 20 years. It's not bad. Ask me anything.

    careersus-shure.icims.com/jobs

    Put down my name and I'll get a referral bonus.

    #engineering #management #python #verilog #vhdl #proaudio #job #jobs #getfedihired #fedijobs #jobsearch #fedihire #illinois #chicago #askmeanything

    #shure #fpga #modem #wireless #engineering #management
  9. Habr @[email protected] ·

    Перепрыгивание с языка на язык как тактика прохождения интервью

    В 2010 году я участвовал в интервьировании на позицию по моделированию и верификации процессорных ядер. Один из кандидатов был благообразный седой американец, который до этого работал в IBM. Я задал вопрос про язык описания и верификации аппаратуры SystemVerilog. На это кандидат сказал, что он еще не освоил SystemVerilog, вписал его в резюме на будущее, но вообще использовал Verilog-95 и немного Verilog-2001. “Нет проблем”, - сказал я и задал вопрос по Verilog-95: “приведите примеры гонок (race conditions) при испрользовании верилога”. На это кандидат сказал, что вообще его опыт был больше связан с VHDL. “Блин, как он выкрутился” - подумал я, ведь в VHDL нет гонок как в верилоге из-за дизайна языка.

    habr.com/ru/articles/1033360/

    #SystemVerilog #verilog #Ada #VHDL #Jovial #Coral66 #IBM #Стенфорд #вопросы_на_собеседовании #внешний_вид

    #внешний_вид #вопросы_на_собеседовании #стенфорд #ibm #coral66 #jovial
  10. alios @[email protected] ·

    Good read on #VHDL’s delta cycle algorithm in action. Delta cycles are an #HDL concept used to order events that occur in zero physical time:

    VHDL's crown jewel

    sigasi.com/opinion/jan/vhdls-c

    #vhdl #hdl
  11. N-gated Hacker News @[email protected] ·

    Ah, the "crown jewel" of VHDL: a riveting exploration into #determinism so compelling, it'll have you questioning if watching paint dry is more thrilling. 🤦‍♂️🤷‍♀️ Dive into an endless loop of corporate jargon and existential delta cycles, because who needs excitement when you have VHDL? ⚙️🛠️
    sigasi.com/opinion/jan/vhdls-c #VHDL #CorporateJargon #ExistentialCycles #TechHumor #ProgrammingFun #HackerNews #ngated

    #determinism #vhdl #corporatejargon #existentialcycles #techhumor #programmingfun
  12. Hacker News @[email protected] ·

    VHDL's Crown Jewel

    sigasi.com/opinion/jan/vhdls-c

    #HackerNews #VHDL #CrownJewel #VHDL #FPGA #HardwareDesign #TechInsights

    #hackernews #vhdl #crownjewel #fpga #hardwaredesign #techinsights
  13. PypelineC @pipelinec ·

    Fun in the frequency domain 🤓 Camera pointed at it's own display also showing audio FFT for cool glitchy visualizer effect. Video processing all done in PipelineC hardware. And how?

    github.com/JulianKemmerer/Pipe

    #hardware #fpga #dsp #rtl #hdl #hls
  14. Gray Beard @[email protected] ·

    SystemLisp - an HDL simulator written in Common Lisp

    github.com/systemlisp

    #lisp #commonlisp #hdl #rtl #verilog #design #verification #vhdl #systemverilog #vlsi #programming #fpga

    #lisp #commonlisp #hdl #rtl #verilog #design
  15. Habr @[email protected] ·

    Выступил отрицателем AI на конференции SNUG Silicon Valley

    AI - не микроархитектор, не проектировщик и не верификатор. Это все-лишь гламурный поисковик уже решенных и опубликованных задач. Именно такой вывод следовал из предоставленных мною на конференции SNUG Silicon Valley 2026 фактов как десятки студентов мучали ИИ чтобы решить мои задачки. Одну задачку ИИ решил лишь через полгода после выкладывания решений в интернет, другую за два месяца, потом пошла третья. При этом задачки были довольно банальные - мы в Самсунге даем делать такие статические конвейеры с контролем потока данных практикантам. Вот постер, сопровождающий мою статью:

    habr.com/ru/articles/1010978/

    #SNUG #Synopsys #Silicon_Valley #школа_синтеза_цифровых_схем #SystemVerilog #ASIC #FPGA #Samsung #задачи_на_собеседованиях #VHDL

    #vhdl #задачи_на_собеседованиях #samsung #fpga #asic #systemverilog
  16. cnx-software.com [Unofficial] @[email protected] ·

    AERIS-10 open-source hardware radar can track multiple objects up to 20km away

    web.brid.gy/r/https://www.cnx-

    #hardware #stmicrostm32 #xilinxartix #diy #fpga #military
  17. PipelineC @[email protected] ·

    @nlnetlabs.bsky.social NLnet Foundation funded open source WireGuard router in FPGA. Featuring PipelineC for cryptography blocks 🤓 github.com/JulianKemmer... #hardware #fpga #rtl #hdl #hls #verilog #vhdl #cryptography #wireguard #pipelinec

    #hardware #fpga #rtl #hdl #hls #verilog
  18. PypelineC @pipelinec ·

    @nlnet NLnet Foundation funded open source WireGuard router in FPGA. Featuring PipelineC for cryptography blocks 🤓

    github.com/JulianKemmerer/Pipe

    #hardware #fpga #rtl #hdl #hls #verilog
  19. poleguy looking for lost tools @[email protected] ·

    New blog post.

    poleguy.com/blog/john-henry-an

    #AI #NoAI #AIcritic #slop #FPGA #verilog #vhdl

    #ai #noai #aicritic #slop #fpga #verilog
  20. PypelineC @pipelinec ·

    PipelineC holds the throughput lead on Latchup.app. For now! How does your design stack up against a pipelining tool? Far too time consuming and fun of a site 🤓 Look forward to seeing competing solutions.

    github.com/JulianKemmerer/Pipe

    #fpga #asic #rtl #hdl #verilog #vhdl
  21. poleguy looking for lost tools @[email protected] ·

    Start rtl counter with a timer that is initialized 10 seconds from a 32bit wrap point so that the software handling of wrap-around is well exercised during development.

    #rtl #fpga #verilog #vhdl #xilinx #alchitry #eureka #protonpack #software #softwaredevelopment #hardware #embedded #fensterFreitag

    #rtl #fpga #verilog #vhdl #xilinx #alchitry