#vhdl — Public Fediverse posts

I built a browser IDE that runs real open-source EDA tools. Write VHDL or SystemVerilog, hit run: GHDL/Icarus simulates it, Yosys synthesizes it, and you see the waveform and the netlist cell by cell. No install.

Free fundamentals curriculum + engineering-flavored challenges, and a playground.

https://risingedge.pro/

#FPGA #VHDL #Verilog

Which Verilog TMDS encoding library do you recommend that I use on the Ice Pi Zero? Here is my review of the options.

https://wiki.pythonlinks.info/dvi-rtl-libraries

#Verilog #VHDL #tMDS #IcePiZero

Maybe you'll be my new boss? Come work for #Shure doing #FPGA #modem development in our #Wireless lab.

I've been here 20 years. It's not bad. Ask me anything.

https://careersus-shure.icims.com/jobs/4766/engineer-staff-managing%2c-fpga/job?mode=view

Put down my name and I'll get a referral bonus.

#engineering #management #python #verilog #vhdl #proaudio #job #jobs #getfedihired #fedijobs #jobsearch #fedihire #illinois #chicago #askmeanything

One Open-source Project Daily

Digital logic design tool and simulator

https://github.com/logisim-evolution/logisim-evolution

#1ospd #opensource #circuit #circuits #digitalcircuit #digitalcircuits #digitallogic #digitallogicdesign #education #fpga #logic #logisim #logisimevolution #simulator #timingdiagram #verilog #vhdl

Hello World from my new Icepi Zero! :D

the first example was to old, the #yosys Software changed the last years. But now I get an example to work. Nearly everything worked out of the box. After adding a udev/rules.d even programming worked!!! #Yeah

#Opensource #fpga #vhdl #verilog