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  1. Icepi Zero Bot @[email protected] ·

    @[email protected]

    @[email protected] asked

    library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1'); uart_data : out std_logic_vector(7 downto 0) := (others => '0'); uart_ready : in std_logic; uart_valid : out std_logic := '0' ); end my_code; architecture rtl of my_code is alias red : std_logic_vector(7 downto 0) is background_color(23 downto 16); alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8); alias blue : std_logic_vector(7 downto 0) is background_color(7 downto 0); signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant example_text : string := "Hello Fediverse! <3"; constant example_text_row : integer := 15; constant example_text_col : integer := 15; constant uart_text : string := "Hello Fediverse on UART!" & LF; begin char <= character'pos(example_text(col + 1 - example_text_col)) when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0; red <= std_logic_vector(to_unsigned(col*4, 8)); green <= std_logic_vector(to_unsigned(py, 8)); blue <= std_logic_vector(resize(frame_counter, 8)); foreground_color <= (others => '1'); process(clk) variable old_vsync : std_logic := '0'; variable uart_counter : integer range uart_text'range := 1; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then frame_counter <= frame_counter + 1; end if; old_vsync := vsync; uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8)); uart_valid <= '1'; if uart_ready = '1' and uart_valid = '1' then if uart_counter < uart_text'length then uart_counter := uart_counter + 1; else uart_counter := 1; end if; end if; end if; end process; end architecture;

    Success!

    UART Output

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    UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1171242884.8%TRELLIS_FF177242880.7%TRELLIS_IO111975.6%
    TimingClockAchievedConstraint$glbnet$clkp39.04 MHz25 MHz$glbnet$clkt345.18 MHz250 MHz
    Code

    library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1');

        uart_data : out std_logic_vector(7 downto 0) := (others => '0');
        uart_ready : in std_logic;
        uart_valid : out std_logic := '0'
    );
end my_code;

architecture rtl of my_code is
    alias red   : std_logic_vector(7 downto 0) is background_color(23 downto 16);
    alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8);
    alias blue  : std_logic_vector(7 downto 0) is background_color(7 downto 0);

    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant example_text : string := "Hello Fediverse! <3";
    constant example_text_row : integer := 15;
    constant example_text_col : integer := 15;

    constant uart_text : string := "Hello Fediverse on UART!" & LF;
begin
    char <= character'pos(example_text(col + 1 - example_text_col))
        when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0;

    red   <= std_logic_vector(to_unsigned(col*4, 8));
    green <= std_logic_vector(to_unsigned(py, 8));
    blue  <= std_logic_vector(resize(frame_counter, 8));

    foreground_color <= (others => '1');

    process(clk)
        variable old_vsync : std_logic := '0';

        variable uart_counter : integer range uart_text'range := 1;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                frame_counter <= frame_counter + 1;
            end if;
            old_vsync := vsync;

            uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8));
            uart_valid <= '1';
            if uart_ready = '1' and uart_valid = '1' then
                if uart_counter < uart_text'length then
                    uart_counter := uart_counter + 1;
                else
                    uart_counter := 1;
                end if;
            end if;
        end if;
    end process;
end architecture;


    #FPGA #Icepi-Zero #HDL #VHDL
    #fpga #icepizero #hdl #vhdl
  2. Icepi Zero Bot @[email protected] ·

    @[email protected]

    @[email protected] asked

    library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1'); uart_data : out std_logic_vector(7 downto 0) := (others => '0'); uart_ready : in std_logic; uart_valid : out std_logic := '0' ); end my_code; architecture rtl of my_code is alias red : std_logic_vector(7 downto 0) is background_color(23 downto 16); alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8); alias blue : std_logic_vector(7 downto 0) is background_color(7 downto 0); signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant example_text : string := "Hello Fediverse! <3"; constant example_text_row : integer := 15; constant example_text_col : integer := 15; constant uart_text : string := "Hello Fediverse on UART!" & LF; begin char <= character'pos(example_text(col + 1 - example_text_col)) when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0; red <= std_logic_vector(to_unsigned(col*4, 8)); green <= std_logic_vector(to_unsigned(py, 8)); blue <= std_logic_vector(resize(frame_counter, 8)); foreground_color <= (others => '1'); process(clk) variable old_vsync : std_logic := '0'; variable uart_counter : integer range uart_text'range := 1; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then frame_counter <= frame_counter + 1; end if; old_vsync := vsync; uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8)); uart_valid <= '1'; if uart_ready = '1' and uart_valid = '1' then if uart_counter < uart_text'length then uart_counter := uart_counter + 1; else uart_counter := 1; end if; end if; end if; end process; end architecture;

    Success!

    UART Output

    ... [TRUNCATED] ...
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    UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1171242884.8%TRELLIS_FF177242880.7%TRELLIS_IO111975.6%
    TimingClockAchievedConstraint$glbnet$clkp39.04 MHz25 MHz$glbnet$clkt345.18 MHz250 MHz
    Code

    library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1');

        uart_data : out std_logic_vector(7 downto 0) := (others => '0');
        uart_ready : in std_logic;
        uart_valid : out std_logic := '0'
    );
end my_code;

architecture rtl of my_code is
    alias red   : std_logic_vector(7 downto 0) is background_color(23 downto 16);
    alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8);
    alias blue  : std_logic_vector(7 downto 0) is background_color(7 downto 0);

    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant example_text : string := "Hello Fediverse! <3";
    constant example_text_row : integer := 15;
    constant example_text_col : integer := 15;

    constant uart_text : string := "Hello Fediverse on UART!" & LF;
begin
    char <= character'pos(example_text(col + 1 - example_text_col))
        when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0;

    red   <= std_logic_vector(to_unsigned(col*4, 8));
    green <= std_logic_vector(to_unsigned(py, 8));
    blue  <= std_logic_vector(resize(frame_counter, 8));

    foreground_color <= (others => '1');

    process(clk)
        variable old_vsync : std_logic := '0';

        variable uart_counter : integer range uart_text'range := 1;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                frame_counter <= frame_counter + 1;
            end if;
            old_vsync := vsync;

            uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8));
            uart_valid <= '1';
            if uart_ready = '1' and uart_valid = '1' then
                if uart_counter < uart_text'length then
                    uart_counter := uart_counter + 1;
                else
                    uart_counter := 1;
                end if;
            end if;
        end if;
    end process;
end architecture;


    #FPGA #Icepi-Zero #HDL #VHDL
    #fpga #icepizero #hdl #vhdl
  3. Icepi Zero Bot @[email protected] ·

    @[email protected]

    @[email protected] asked

    library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1'); uart_data : out std_logic_vector(7 downto 0) := (others => '0'); uart_ready : in std_logic; uart_valid : out std_logic := '0' ); end my_code; architecture rtl of my_code is alias red : std_logic_vector(7 downto 0) is background_color(23 downto 16); alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8); alias blue : std_logic_vector(7 downto 0) is background_color(7 downto 0); signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant example_text : string := "Hello Fediverse! <3"; constant example_text_row : integer := 15; constant example_text_col : integer := 15; constant uart_text : string := "Hello Fediverse on UART!" & LF; begin char <= character'pos(example_text(col + 1 - example_text_col)) when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0; red <= std_logic_vector(to_unsigned(col*4, 8)); green <= std_logic_vector(to_unsigned(py, 8)); blue <= std_logic_vector(resize(frame_counter, 8)); foreground_color <= (others => '1'); process(clk) variable old_vsync : std_logic := '0'; variable uart_counter : integer range uart_text'range := 1; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then frame_counter <= frame_counter + 1; end if; old_vsync := vsync; uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8)); uart_valid <= '1'; if uart_ready = '1' and uart_valid = '1' then if uart_counter < uart_text'length then uart_counter := uart_counter + 1; else uart_counter := 1; end if; end if; end if; end process; end architecture;

    Success!

    UART Output

    ... [TRUNCATED] ...
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    UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1171242884.8%TRELLIS_FF177242880.7%TRELLIS_IO111975.6%
    TimingClockAchievedConstraint$glbnet$clkp39.04 MHz25 MHz$glbnet$clkt345.18 MHz250 MHz
    Code

    library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1');

        uart_data : out std_logic_vector(7 downto 0) := (others => '0');
        uart_ready : in std_logic;
        uart_valid : out std_logic := '0'
    );
end my_code;

architecture rtl of my_code is
    alias red   : std_logic_vector(7 downto 0) is background_color(23 downto 16);
    alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8);
    alias blue  : std_logic_vector(7 downto 0) is background_color(7 downto 0);

    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant example_text : string := "Hello Fediverse! <3";
    constant example_text_row : integer := 15;
    constant example_text_col : integer := 15;

    constant uart_text : string := "Hello Fediverse on UART!" & LF;
begin
    char <= character'pos(example_text(col + 1 - example_text_col))
        when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0;

    red   <= std_logic_vector(to_unsigned(col*4, 8));
    green <= std_logic_vector(to_unsigned(py, 8));
    blue  <= std_logic_vector(resize(frame_counter, 8));

    foreground_color <= (others => '1');

    process(clk)
        variable old_vsync : std_logic := '0';

        variable uart_counter : integer range uart_text'range := 1;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                frame_counter <= frame_counter + 1;
            end if;
            old_vsync := vsync;

            uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8));
            uart_valid <= '1';
            if uart_ready = '1' and uart_valid = '1' then
                if uart_counter < uart_text'length then
                    uart_counter := uart_counter + 1;
                else
                    uart_counter := 1;
                end if;
            end if;
        end if;
    end process;
end architecture;


    #FPGA #Icepi-Zero #HDL #VHDL
    #fpga #icepizero #hdl #vhdl
  4. Icepi Zero Bot @[email protected] ·

    @[email protected]

    @[email protected] asked

    library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1'); uart_data : out std_logic_vector(7 downto 0) := (others => '0'); uart_ready : in std_logic; uart_valid : out std_logic := '0' ); end my_code; architecture rtl of my_code is alias red : std_logic_vector(7 downto 0) is background_color(23 downto 16); alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8); alias blue : std_logic_vector(7 downto 0) is background_color(7 downto 0); signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant example_text : string := "Hello Fediverse! <3"; constant example_text_row : integer := 15; constant example_text_col : integer := 15; constant uart_text : string := "Hello Fediverse on UART!" & LF; begin char <= character'pos(example_text(col + 1 - example_text_col)) when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0; red <= std_logic_vector(to_unsigned(col*4, 8)); green <= std_logic_vector(to_unsigned(py, 8)); blue <= std_logic_vector(resize(frame_counter, 8)); foreground_color <= (others => '1'); process(clk) variable old_vsync : std_logic := '0'; variable uart_counter : integer range uart_text'range := 1; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then frame_counter <= frame_counter + 1; end if; old_vsync := vsync; uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8)); uart_valid <= '1'; if uart_ready = '1' and uart_valid = '1' then if uart_counter < uart_text'length then uart_counter := uart_counter + 1; else uart_counter := 1; end if; end if; end if; end process; end architecture;

    Success!

    UART Output

    ... [TRUNCATED] ...
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    UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1171242884.8%TRELLIS_FF177242880.7%TRELLIS_IO111975.6%
    TimingClockAchievedConstraint$glbnet$clkp39.04 MHz25 MHz$glbnet$clkt345.18 MHz250 MHz
    Code

    library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1');

        uart_data : out std_logic_vector(7 downto 0) := (others => '0');
        uart_ready : in std_logic;
        uart_valid : out std_logic := '0'
    );
end my_code;

architecture rtl of my_code is
    alias red   : std_logic_vector(7 downto 0) is background_color(23 downto 16);
    alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8);
    alias blue  : std_logic_vector(7 downto 0) is background_color(7 downto 0);

    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant example_text : string := "Hello Fediverse! <3";
    constant example_text_row : integer := 15;
    constant example_text_col : integer := 15;

    constant uart_text : string := "Hello Fediverse on UART!" & LF;
begin
    char <= character'pos(example_text(col + 1 - example_text_col))
        when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0;

    red   <= std_logic_vector(to_unsigned(col*4, 8));
    green <= std_logic_vector(to_unsigned(py, 8));
    blue  <= std_logic_vector(resize(frame_counter, 8));

    foreground_color <= (others => '1');

    process(clk)
        variable old_vsync : std_logic := '0';

        variable uart_counter : integer range uart_text'range := 1;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                frame_counter <= frame_counter + 1;
            end if;
            old_vsync := vsync;

            uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8));
            uart_valid <= '1';
            if uart_ready = '1' and uart_valid = '1' then
                if uart_counter < uart_text'length then
                    uart_counter := uart_counter + 1;
                else
                    uart_counter := 1;
                end if;
            end if;
        end if;
    end process;
end architecture;


    #FPGA #Icepi-Zero #HDL #VHDL
    #fpga #icepizero #hdl #vhdl
  5. Icepi Zero Bot @[email protected] ·

    @[email protected]

    @[email protected] asked

    library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1'); uart_data : out std_logic_vector(7 downto 0) := (others => '0'); uart_ready : in std_logic; uart_valid : out std_logic := '0' ); end my_code; architecture rtl of my_code is alias red : std_logic_vector(7 downto 0) is background_color(23 downto 16); alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8); alias blue : std_logic_vector(7 downto 0) is background_color(7 downto 0); signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant example_text : string := "Hello Fediverse! <3"; constant example_text_row : integer := 15; constant example_text_col : integer := 15; constant uart_text : string := "Hello Fediverse on UART!" & LF; begin char <= character'pos(example_text(col + 1 - example_text_col)) when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0; red <= std_logic_vector(to_unsigned(col*4, 8)); green <= std_logic_vector(to_unsigned(py, 8)); blue <= std_logic_vector(resize(frame_counter, 8)); foreground_color <= (others => '1'); process(clk) variable old_vsync : std_logic := '0'; variable uart_counter : integer range uart_text'range := 1; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then frame_counter <= frame_counter + 1; end if; old_vsync := vsync; uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8)); uart_valid <= '1'; if uart_ready = '1' and uart_valid = '1' then if uart_counter < uart_text'length then uart_counter := uart_counter + 1; else uart_counter := 1; end if; end if; end if; end process; end architecture;

    Success!

    UART Output

    ... [TRUNCATED] ...
iverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
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Hello Fed


    UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1171242884.8%TRELLIS_FF177242880.7%TRELLIS_IO111975.6%
    TimingClockAchievedConstraint$glbnet$clkp39.04 MHz25 MHz$glbnet$clkt345.18 MHz250 MHz
    Code

    library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1');

        uart_data : out std_logic_vector(7 downto 0) := (others => '0');
        uart_ready : in std_logic;
        uart_valid : out std_logic := '0'
    );
end my_code;

architecture rtl of my_code is
    alias red   : std_logic_vector(7 downto 0) is background_color(23 downto 16);
    alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8);
    alias blue  : std_logic_vector(7 downto 0) is background_color(7 downto 0);

    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant example_text : string := "Hello Fediverse! <3";
    constant example_text_row : integer := 15;
    constant example_text_col : integer := 15;

    constant uart_text : string := "Hello Fediverse on UART!" & LF;
begin
    char <= character'pos(example_text(col + 1 - example_text_col))
        when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0;

    red   <= std_logic_vector(to_unsigned(col*4, 8));
    green <= std_logic_vector(to_unsigned(py, 8));
    blue  <= std_logic_vector(resize(frame_counter, 8));

    foreground_color <= (others => '1');

    process(clk)
        variable old_vsync : std_logic := '0';

        variable uart_counter : integer range uart_text'range := 1;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                frame_counter <= frame_counter + 1;
            end if;
            old_vsync := vsync;

            uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8));
            uart_valid <= '1';
            if uart_ready = '1' and uart_valid = '1' then
                if uart_counter < uart_text'length then
                    uart_counter := uart_counter + 1;
                else
                    uart_counter := 1;
                end if;
            end if;
        end if;
    end process;
end architecture;


    #FPGA #Icepi-Zero #HDL #VHDL
    #fpga #icepizero #hdl #vhdl
  6. Icepi Zero Bot @[email protected] ·

    @[email protected]

    @[email protected] asked

    library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1'); uart_data : out std_logic_vector(7 downto 0) := (others => '0'); uart_ready : in std_logic; uart_valid : out std_logic := '0' ); end my_code; architecture rtl of my_code is alias red : std_logic_vector(7 downto 0) is background_color(23 downto 16); alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8); alias blue : std_logic_vector(7 downto 0) is background_color(7 downto 0); signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant example_text : string := "Hello Fediverse! <3"; constant example_text_row : integer := 15; constant example_text_col : integer := 15; constant uart_text : string := "Hello Fediverse on UART!" & LF; begin char <= character'pos(example_text(col + 1 - example_text_col)) when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0; red <= std_logic_vector(to_unsigned(col*4, 8)); green <= std_logic_vector(to_unsigned(py, 8)); blue <= std_logic_vector(resize(frame_counter, 8)); foreground_color <= (others => '1'); process(clk) variable old_vsync : std_logic := '0'; variable uart_counter : integer range uart_text'range := 1; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then frame_counter <= frame_counter + 1; end if; old_vsync := vsync; uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8)); uart_valid <= '1'; if uart_ready = '1' and uart_valid = '1' then if uart_counter < uart_text'length then uart_counter := uart_counter + 1; else uart_counter := 1; end if; end if; end if; end process; end architecture;

    Success!

    UART Output

    ... [TRUNCATED] ...
iverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
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Hello Fed


    UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1171242884.8%TRELLIS_FF177242880.7%TRELLIS_IO111975.6%
    TimingClockAchievedConstraint$glbnet$clkp39.04 MHz25 MHz$glbnet$clkt345.18 MHz250 MHz
    Code

    library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1');

        uart_data : out std_logic_vector(7 downto 0) := (others => '0');
        uart_ready : in std_logic;
        uart_valid : out std_logic := '0'
    );
end my_code;

architecture rtl of my_code is
    alias red   : std_logic_vector(7 downto 0) is background_color(23 downto 16);
    alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8);
    alias blue  : std_logic_vector(7 downto 0) is background_color(7 downto 0);

    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant example_text : string := "Hello Fediverse! <3";
    constant example_text_row : integer := 15;
    constant example_text_col : integer := 15;

    constant uart_text : string := "Hello Fediverse on UART!" & LF;
begin
    char <= character'pos(example_text(col + 1 - example_text_col))
        when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0;

    red   <= std_logic_vector(to_unsigned(col*4, 8));
    green <= std_logic_vector(to_unsigned(py, 8));
    blue  <= std_logic_vector(resize(frame_counter, 8));

    foreground_color <= (others => '1');

    process(clk)
        variable old_vsync : std_logic := '0';

        variable uart_counter : integer range uart_text'range := 1;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                frame_counter <= frame_counter + 1;
            end if;
            old_vsync := vsync;

            uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8));
            uart_valid <= '1';
            if uart_ready = '1' and uart_valid = '1' then
                if uart_counter < uart_text'length then
                    uart_counter := uart_counter + 1;
                else
                    uart_counter := 1;
                end if;
            end if;
        end if;
    end process;
end architecture;


    #FPGA #Icepi-Zero #HDL #VHDL
    #fpga #icepizero #hdl #vhdl
  7. Icepi Zero Bot @[email protected] ·

    @[email protected]

    @[email protected] asked

    library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1'); uart_data : out std_logic_vector(7 downto 0) := (others => '0'); uart_ready : in std_logic; uart_valid : out std_logic := '0' ); end my_code; architecture rtl of my_code is alias red : std_logic_vector(7 downto 0) is background_color(23 downto 16); alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8); alias blue : std_logic_vector(7 downto 0) is background_color(7 downto 0); signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant example_text : string := "Hello Fediverse! <3"; constant example_text_row : integer := 15; constant example_text_col : integer := 15; constant uart_text : string := "Hello Fediverse on UART!" & LF; begin char <= character'pos(example_text(col + 1 - example_text_col)) when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0; red <= std_logic_vector(to_unsigned(col*4, 8)); green <= std_logic_vector(to_unsigned(py, 8)); blue <= std_logic_vector(resize(frame_counter, 8)); foreground_color <= (others => '1'); process(clk) variable old_vsync : std_logic := '0'; variable uart_counter : integer range uart_text'range := 1; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then frame_counter <= frame_counter + 1; end if; old_vsync := vsync; uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8)); uart_valid <= '1'; if uart_ready = '1' and uart_valid = '1' then if uart_counter < uart_text'length then uart_counter := uart_counter + 1; else uart_counter := 1; end if; end if; end if; end process; end architecture;

    Success!

    UART Output

    ... [TRUNCATED] ...

Hello Fediverse on UART!
Hello Fediverse on UART!
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    UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1171242884.8%TRELLIS_FF177242880.7%TRELLIS_IO111975.6%
    TimingClockAchievedConstraint$glbnet$clkp39.04 MHz25 MHz$glbnet$clkt345.18 MHz250 MHz
    Code

    library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1');

        uart_data : out std_logic_vector(7 downto 0) := (others => '0');
        uart_ready : in std_logic;
        uart_valid : out std_logic := '0'
    );
end my_code;

architecture rtl of my_code is
    alias red   : std_logic_vector(7 downto 0) is background_color(23 downto 16);
    alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8);
    alias blue  : std_logic_vector(7 downto 0) is background_color(7 downto 0);

    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant example_text : string := "Hello Fediverse! <3";
    constant example_text_row : integer := 15;
    constant example_text_col : integer := 15;

    constant uart_text : string := "Hello Fediverse on UART!" & LF;
begin
    char <= character'pos(example_text(col + 1 - example_text_col))
        when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0;

    red   <= std_logic_vector(to_unsigned(col*4, 8));
    green <= std_logic_vector(to_unsigned(py, 8));
    blue  <= std_logic_vector(resize(frame_counter, 8));

    foreground_color <= (others => '1');

    process(clk)
        variable old_vsync : std_logic := '0';

        variable uart_counter : integer range uart_text'range := 1;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                frame_counter <= frame_counter + 1;
            end if;
            old_vsync := vsync;

            uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8));
            uart_valid <= '1';
            if uart_ready = '1' and uart_valid = '1' then
                if uart_counter < uart_text'length then
                    uart_counter := uart_counter + 1;
                else
                    uart_counter := 1;
                end if;
            end if;
        end if;
    end process;
end architecture;


    #FPGA #Icepi-Zero #HDL #VHDL
    #fpga #icepizero #hdl #vhdl
  8. Icepi Zero Bot @[email protected] ·

    @[email protected]

    @[email protected] asked

    library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1'); uart_data : out std_logic_vector(7 downto 0) := (others => '0'); uart_ready : in std_logic; uart_valid : out std_logic := '0' ); end my_code; architecture rtl of my_code is alias red : std_logic_vector(7 downto 0) is background_color(23 downto 16); alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8); alias blue : std_logic_vector(7 downto 0) is background_color(7 downto 0); signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant example_text : string := "Hello Fediverse! <3"; constant example_text_row : integer := 15; constant example_text_col : integer := 15; constant uart_text : string := "Hello Fediverse on UART!" & LF; begin char <= character'pos(example_text(col + 1 - example_text_col)) when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0; red <= std_logic_vector(to_unsigned(col*4, 8)); green <= std_logic_vector(to_unsigned(py, 8)); blue <= std_logic_vector(resize(frame_counter, 8)); foreground_color <= (others => '1'); process(clk) variable old_vsync : std_logic := '0'; variable uart_counter : integer range uart_text'range := 1; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then frame_counter <= frame_counter + 1; end if; old_vsync := vsync; uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8)); uart_valid <= '1'; if uart_ready = '1' and uart_valid = '1' then if uart_counter < uart_text'length then uart_counter := uart_counter + 1; else uart_counter := 1; end if; end if; end if; end process; end architecture;

    Success!

    UART Output

    ... [TRUNCATED] ...

Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
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    UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1171242884.8%TRELLIS_FF177242880.7%TRELLIS_IO111975.6%
    TimingClockAchievedConstraint$glbnet$clkp39.04 MHz25 MHz$glbnet$clkt345.18 MHz250 MHz
    Code

    library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1');

        uart_data : out std_logic_vector(7 downto 0) := (others => '0');
        uart_ready : in std_logic;
        uart_valid : out std_logic := '0'
    );
end my_code;

architecture rtl of my_code is
    alias red   : std_logic_vector(7 downto 0) is background_color(23 downto 16);
    alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8);
    alias blue  : std_logic_vector(7 downto 0) is background_color(7 downto 0);

    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant example_text : string := "Hello Fediverse! <3";
    constant example_text_row : integer := 15;
    constant example_text_col : integer := 15;

    constant uart_text : string := "Hello Fediverse on UART!" & LF;
begin
    char <= character'pos(example_text(col + 1 - example_text_col))
        when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0;

    red   <= std_logic_vector(to_unsigned(col*4, 8));
    green <= std_logic_vector(to_unsigned(py, 8));
    blue  <= std_logic_vector(resize(frame_counter, 8));

    foreground_color <= (others => '1');

    process(clk)
        variable old_vsync : std_logic := '0';

        variable uart_counter : integer range uart_text'range := 1;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                frame_counter <= frame_counter + 1;
            end if;
            old_vsync := vsync;

            uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8));
            uart_valid <= '1';
            if uart_ready = '1' and uart_valid = '1' then
                if uart_counter < uart_text'length then
                    uart_counter := uart_counter + 1;
                else
                    uart_counter := 1;
                end if;
            end if;
        end if;
    end process;
end architecture;


    #FPGA #Icepi-Zero #HDL #VHDL
    #fpga #icepizero #hdl #vhdl
  9. Icepi Zero Bot @[email protected] ·

    @[email protected]

    @[email protected] asked

    library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1'); uart_data : out std_logic_vector(7 downto 0) := (others => '0'); uart_ready : in std_logic; uart_valid : out std_logic := '0' ); end my_code; architecture rtl of my_code is alias red : std_logic_vector(7 downto 0) is background_color(23 downto 16); alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8); alias blue : std_logic_vector(7 downto 0) is background_color(7 downto 0); signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant example_text : string := "Hello Fediverse! <3"; constant example_text_row : integer := 15; constant example_text_col : integer := 15; constant uart_text : string := "Hello Fediverse on UART!" & LF; begin char <= character'pos(example_text(col + 1 - example_text_col)) when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0; red <= std_logic_vector(to_unsigned(col*4, 8)); green <= std_logic_vector(to_unsigned(py, 8)); blue <= std_logic_vector(resize(frame_counter, 8)); foreground_color <= (others => '1'); process(clk) variable old_vsync : std_logic := '0'; variable uart_counter : integer range uart_text'range := 1; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then frame_counter <= frame_counter + 1; end if; old_vsync := vsync; uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8)); uart_valid <= '1'; if uart_ready = '1' and uart_valid = '1' then if uart_counter < uart_text'length then uart_counter := uart_counter + 1; else uart_counter := 1; end if; end if; end if; end process; end architecture;

    Success!

    UART Output

    ... [TRUNCATED] ...
!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
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    UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1171242884.8%TRELLIS_FF177242880.7%TRELLIS_IO111975.6%
    TimingClockAchievedConstraint$glbnet$clkp39.04 MHz25 MHz$glbnet$clkt345.18 MHz250 MHz
    Code

    library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1');

        uart_data : out std_logic_vector(7 downto 0) := (others => '0');
        uart_ready : in std_logic;
        uart_valid : out std_logic := '0'
    );
end my_code;

architecture rtl of my_code is
    alias red   : std_logic_vector(7 downto 0) is background_color(23 downto 16);
    alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8);
    alias blue  : std_logic_vector(7 downto 0) is background_color(7 downto 0);

    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant example_text : string := "Hello Fediverse! <3";
    constant example_text_row : integer := 15;
    constant example_text_col : integer := 15;

    constant uart_text : string := "Hello Fediverse on UART!" & LF;
begin
    char <= character'pos(example_text(col + 1 - example_text_col))
        when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0;

    red   <= std_logic_vector(to_unsigned(col*4, 8));
    green <= std_logic_vector(to_unsigned(py, 8));
    blue  <= std_logic_vector(resize(frame_counter, 8));

    foreground_color <= (others => '1');

    process(clk)
        variable old_vsync : std_logic := '0';

        variable uart_counter : integer range uart_text'range := 1;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                frame_counter <= frame_counter + 1;
            end if;
            old_vsync := vsync;

            uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8));
            uart_valid <= '1';
            if uart_ready = '1' and uart_valid = '1' then
                if uart_counter < uart_text'length then
                    uart_counter := uart_counter + 1;
                else
                    uart_counter := 1;
                end if;
            end if;
        end if;
    end process;
end architecture;


    #FPGA #Icepi-Zero #HDL #VHDL
    #fpga #icepizero #hdl #vhdl
  10. Icepi Zero Bot @[email protected] ·

    @[email protected]

    @[email protected] asked

    library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1'); uart_data : out std_logic_vector(7 downto 0) := (others => '0'); uart_ready : in std_logic; uart_valid : out std_logic := '0' ); end my_code; architecture rtl of my_code is alias red : std_logic_vector(7 downto 0) is background_color(23 downto 16); alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8); alias blue : std_logic_vector(7 downto 0) is background_color(7 downto 0); signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant example_text : string := "Hello Fediverse! <3"; constant example_text_row : integer := 15; constant example_text_col : integer := 15; constant uart_text : string := "Hello Fediverse on UART!" & LF; begin char <= character'pos(example_text(col + 1 - example_text_col)) when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0; red <= std_logic_vector(to_unsigned(col*4, 8)); green <= std_logic_vector(to_unsigned(py, 8)); blue <= std_logic_vector(resize(frame_counter, 8)); foreground_color <= (others => '1'); process(clk) variable old_vsync : std_logic := '0'; variable uart_counter : integer range uart_text'range := 1; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then frame_counter <= frame_counter + 1; end if; old_vsync := vsync; uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8)); uart_valid <= '1'; if uart_ready = '1' and uart_valid = '1' then if uart_counter < uart_text'length then uart_counter := uart_counter + 1; else uart_counter := 1; end if; end if; end if; end process; end architecture;

    Success!

    UART Output

    ... [TRUNCATED] ...
!
Hello Fediverse on UART!
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    UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1171242884.8%TRELLIS_FF177242880.7%TRELLIS_IO111975.6%
    TimingClockAchievedConstraint$glbnet$clkp39.04 MHz25 MHz$glbnet$clkt345.18 MHz250 MHz
    Code

    library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1');

        uart_data : out std_logic_vector(7 downto 0) := (others => '0');
        uart_ready : in std_logic;
        uart_valid : out std_logic := '0'
    );
end my_code;

architecture rtl of my_code is
    alias red   : std_logic_vector(7 downto 0) is background_color(23 downto 16);
    alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8);
    alias blue  : std_logic_vector(7 downto 0) is background_color(7 downto 0);

    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant example_text : string := "Hello Fediverse! <3";
    constant example_text_row : integer := 15;
    constant example_text_col : integer := 15;

    constant uart_text : string := "Hello Fediverse on UART!" & LF;
begin
    char <= character'pos(example_text(col + 1 - example_text_col))
        when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0;

    red   <= std_logic_vector(to_unsigned(col*4, 8));
    green <= std_logic_vector(to_unsigned(py, 8));
    blue  <= std_logic_vector(resize(frame_counter, 8));

    foreground_color <= (others => '1');

    process(clk)
        variable old_vsync : std_logic := '0';

        variable uart_counter : integer range uart_text'range := 1;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                frame_counter <= frame_counter + 1;
            end if;
            old_vsync := vsync;

            uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8));
            uart_valid <= '1';
            if uart_ready = '1' and uart_valid = '1' then
                if uart_counter < uart_text'length then
                    uart_counter := uart_counter + 1;
                else
                    uart_counter := 1;
                end if;
            end if;
        end if;
    end process;
end architecture;


    #FPGA #Icepi-Zero #HDL #VHDL
    #fpga #icepizero #hdl #vhdl
  11. Icepi Zero Bot @[email protected] ·

    @[email protected]

    @[email protected] asked

    library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1'); uart_data : out std_logic_vector(7 downto 0) := (others => '0'); uart_ready : in std_logic; uart_valid : out std_logic := '0' ); end my_code; architecture rtl of my_code is alias red : std_logic_vector(7 downto 0) is background_color(23 downto 16); alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8); alias blue : std_logic_vector(7 downto 0) is background_color(7 downto 0); signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant example_text : string := "Hello Fediverse! <3"; constant example_text_row : integer := 15; constant example_text_col : integer := 15; constant uart_text : string := "Hello Fediverse on UART!" & LF; begin char <= character'pos(example_text(col + 1 - example_text_col)) when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0; red <= std_logic_vector(to_unsigned(col*4, 8)); green <= std_logic_vector(to_unsigned(py, 8)); blue <= std_logic_vector(resize(frame_counter, 8)); foreground_color <= (others => '1'); process(clk) variable old_vsync : std_logic := '0'; variable uart_counter : integer range uart_text'range := 1; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then frame_counter <= frame_counter + 1; end if; old_vsync := vsync; uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8)); uart_valid <= '1'; if uart_ready = '1' and uart_valid = '1' then if uart_counter < uart_text'length then uart_counter := uart_counter + 1; else uart_counter := 1; end if; end if; end if; end process; end architecture;

    Success!

    UART Output

    ... [TRUNCATED] ...
 on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
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Hello Fediverse


    UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1171242884.8%TRELLIS_FF177242880.7%TRELLIS_IO111975.6%
    TimingClockAchievedConstraint$glbnet$clkp39.04 MHz25 MHz$glbnet$clkt345.18 MHz250 MHz
    Code

    library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1');

        uart_data : out std_logic_vector(7 downto 0) := (others => '0');
        uart_ready : in std_logic;
        uart_valid : out std_logic := '0'
    );
end my_code;

architecture rtl of my_code is
    alias red   : std_logic_vector(7 downto 0) is background_color(23 downto 16);
    alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8);
    alias blue  : std_logic_vector(7 downto 0) is background_color(7 downto 0);

    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant example_text : string := "Hello Fediverse! <3";
    constant example_text_row : integer := 15;
    constant example_text_col : integer := 15;

    constant uart_text : string := "Hello Fediverse on UART!" & LF;
begin
    char <= character'pos(example_text(col + 1 - example_text_col))
        when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0;

    red   <= std_logic_vector(to_unsigned(col*4, 8));
    green <= std_logic_vector(to_unsigned(py, 8));
    blue  <= std_logic_vector(resize(frame_counter, 8));

    foreground_color <= (others => '1');

    process(clk)
        variable old_vsync : std_logic := '0';

        variable uart_counter : integer range uart_text'range := 1;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                frame_counter <= frame_counter + 1;
            end if;
            old_vsync := vsync;

            uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8));
            uart_valid <= '1';
            if uart_ready = '1' and uart_valid = '1' then
                if uart_counter < uart_text'length then
                    uart_counter := uart_counter + 1;
                else
                    uart_counter := 1;
                end if;
            end if;
        end if;
    end process;
end architecture;


    #FPGA #Icepi-Zero #HDL #VHDL
    #fpga #icepizero #hdl #vhdl
  12. Icepi Zero Bot @[email protected] ·

    @[email protected]

    @[email protected] asked

    library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1'); uart_data : out std_logic_vector(7 downto 0) := (others => '0'); uart_ready : in std_logic; uart_valid : out std_logic := '0' ); end my_code; architecture rtl of my_code is alias red : std_logic_vector(7 downto 0) is background_color(23 downto 16); alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8); alias blue : std_logic_vector(7 downto 0) is background_color(7 downto 0); signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant example_text : string := "Hello Fediverse! <3"; constant example_text_row : integer := 15; constant example_text_col : integer := 15; constant uart_text : string := "Hello Fediverse on UART!" & LF; begin char <= character'pos(example_text(col + 1 - example_text_col)) when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0; red <= std_logic_vector(to_unsigned(col*4, 8)); green <= std_logic_vector(to_unsigned(py, 8)); blue <= std_logic_vector(resize(frame_counter, 8)); foreground_color <= (others => '1'); process(clk) variable old_vsync : std_logic := '0'; variable uart_counter : integer range uart_text'range := 1; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then frame_counter <= frame_counter + 1; end if; old_vsync := vsync; uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8)); uart_valid <= '1'; if uart_ready = '1' and uart_valid = '1' then if uart_counter < uart_text'length then uart_counter := uart_counter + 1; else uart_counter := 1; end if; end if; end if; end process; end architecture;

    Success!

    UART Output

    ... [TRUNCATED] ...
 on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
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Hello Fediverse


    UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1171242884.8%TRELLIS_FF177242880.7%TRELLIS_IO111975.6%
    TimingClockAchievedConstraint$glbnet$clkp39.04 MHz25 MHz$glbnet$clkt345.18 MHz250 MHz
    Code

    library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1');

        uart_data : out std_logic_vector(7 downto 0) := (others => '0');
        uart_ready : in std_logic;
        uart_valid : out std_logic := '0'
    );
end my_code;

architecture rtl of my_code is
    alias red   : std_logic_vector(7 downto 0) is background_color(23 downto 16);
    alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8);
    alias blue  : std_logic_vector(7 downto 0) is background_color(7 downto 0);

    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant example_text : string := "Hello Fediverse! <3";
    constant example_text_row : integer := 15;
    constant example_text_col : integer := 15;

    constant uart_text : string := "Hello Fediverse on UART!" & LF;
begin
    char <= character'pos(example_text(col + 1 - example_text_col))
        when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0;

    red   <= std_logic_vector(to_unsigned(col*4, 8));
    green <= std_logic_vector(to_unsigned(py, 8));
    blue  <= std_logic_vector(resize(frame_counter, 8));

    foreground_color <= (others => '1');

    process(clk)
        variable old_vsync : std_logic := '0';

        variable uart_counter : integer range uart_text'range := 1;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                frame_counter <= frame_counter + 1;
            end if;
            old_vsync := vsync;

            uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8));
            uart_valid <= '1';
            if uart_ready = '1' and uart_valid = '1' then
                if uart_counter < uart_text'length then
                    uart_counter := uart_counter + 1;
                else
                    uart_counter := 1;
                end if;
            end if;
        end if;
    end process;
end architecture;


    #FPGA #Icepi-Zero #HDL #VHDL
    #fpga #icepizero #hdl #vhdl
  13. Icepi Zero Bot @[email protected] ·

    @[email protected]

    @[email protected] asked

    library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1'); uart_data : out std_logic_vector(7 downto 0) := (others => '0'); uart_ready : in std_logic; uart_valid : out std_logic := '0' ); end my_code; architecture rtl of my_code is alias red : std_logic_vector(7 downto 0) is background_color(23 downto 16); alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8); alias blue : std_logic_vector(7 downto 0) is background_color(7 downto 0); signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant example_text : string := "Hello Fediverse! <3"; constant example_text_row : integer := 15; constant example_text_col : integer := 15; constant uart_text : string := "Hello Fediverse on UART!" & LF; begin char <= character'pos(example_text(col + 1 - example_text_col)) when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0; red <= std_logic_vector(to_unsigned(col*4, 8)); green <= std_logic_vector(to_unsigned(py, 8)); blue <= std_logic_vector(resize(frame_counter, 8)); foreground_color <= (others => '1'); process(clk) variable old_vsync : std_logic := '0'; variable uart_counter : integer range uart_text'range := 1; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then frame_counter <= frame_counter + 1; end if; old_vsync := vsync; uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8)); uart_valid <= '1'; if uart_ready = '1' and uart_valid = '1' then if uart_counter < uart_text'length then uart_counter := uart_counter + 1; else uart_counter := 1; end if; end if; end if; end process; end architecture;

    Success!

    UART Output

    ... [TRUNCATED] ...
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    UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1171242884.8%TRELLIS_FF177242880.7%TRELLIS_IO111975.6%
    TimingClockAchievedConstraint$glbnet$clkp39.04 MHz25 MHz$glbnet$clkt345.18 MHz250 MHz
    Code

    library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1');

        uart_data : out std_logic_vector(7 downto 0) := (others => '0');
        uart_ready : in std_logic;
        uart_valid : out std_logic := '0'
    );
end my_code;

architecture rtl of my_code is
    alias red   : std_logic_vector(7 downto 0) is background_color(23 downto 16);
    alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8);
    alias blue  : std_logic_vector(7 downto 0) is background_color(7 downto 0);

    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant example_text : string := "Hello Fediverse! <3";
    constant example_text_row : integer := 15;
    constant example_text_col : integer := 15;

    constant uart_text : string := "Hello Fediverse on UART!" & LF;
begin
    char <= character'pos(example_text(col + 1 - example_text_col))
        when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0;

    red   <= std_logic_vector(to_unsigned(col*4, 8));
    green <= std_logic_vector(to_unsigned(py, 8));
    blue  <= std_logic_vector(resize(frame_counter, 8));

    foreground_color <= (others => '1');

    process(clk)
        variable old_vsync : std_logic := '0';

        variable uart_counter : integer range uart_text'range := 1;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                frame_counter <= frame_counter + 1;
            end if;
            old_vsync := vsync;

            uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8));
            uart_valid <= '1';
            if uart_ready = '1' and uart_valid = '1' then
                if uart_counter < uart_text'length then
                    uart_counter := uart_counter + 1;
                else
                    uart_counter := 1;
                end if;
            end if;
        end if;
    end process;
end architecture;


    #FPGA #Icepi-Zero #HDL #VHDL
    #fpga #icepizero #hdl #vhdl
  14. Icepi Zero Bot @[email protected] ·

    @[email protected]

    @[email protected] asked

    library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1'); uart_data : out std_logic_vector(7 downto 0) := (others => '0'); uart_ready : in std_logic; uart_valid : out std_logic := '0' ); end my_code; architecture rtl of my_code is alias red : std_logic_vector(7 downto 0) is background_color(23 downto 16); alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8); alias blue : std_logic_vector(7 downto 0) is background_color(7 downto 0); signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant example_text : string := "Hello Fediverse! <3"; constant example_text_row : integer := 15; constant example_text_col : integer := 15; constant uart_text : string := "Hello Fediverse on UART!" & LF; begin char <= character'pos(example_text(col + 1 - example_text_col)) when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0; red <= std_logic_vector(to_unsigned(col*4, 8)); green <= std_logic_vector(to_unsigned(py, 8)); blue <= std_logic_vector(resize(frame_counter, 8)); foreground_color <= (others => '1'); process(clk) variable old_vsync : std_logic := '0'; variable uart_counter : integer range uart_text'range := 1; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then frame_counter <= frame_counter + 1; end if; old_vsync := vsync; uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8)); uart_valid <= '1'; if uart_ready = '1' and uart_valid = '1' then if uart_counter < uart_text'length then uart_counter := uart_counter + 1; else uart_counter := 1; end if; end if; end if; end process; end architecture;

    Success!

    UART Output

    ... [TRUNCATED] ...
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    UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1171242884.8%TRELLIS_FF177242880.7%TRELLIS_IO111975.6%
    TimingClockAchievedConstraint$glbnet$clkp39.04 MHz25 MHz$glbnet$clkt345.18 MHz250 MHz
    Code

    library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1');

        uart_data : out std_logic_vector(7 downto 0) := (others => '0');
        uart_ready : in std_logic;
        uart_valid : out std_logic := '0'
    );
end my_code;

architecture rtl of my_code is
    alias red   : std_logic_vector(7 downto 0) is background_color(23 downto 16);
    alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8);
    alias blue  : std_logic_vector(7 downto 0) is background_color(7 downto 0);

    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant example_text : string := "Hello Fediverse! <3";
    constant example_text_row : integer := 15;
    constant example_text_col : integer := 15;

    constant uart_text : string := "Hello Fediverse on UART!" & LF;
begin
    char <= character'pos(example_text(col + 1 - example_text_col))
        when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0;

    red   <= std_logic_vector(to_unsigned(col*4, 8));
    green <= std_logic_vector(to_unsigned(py, 8));
    blue  <= std_logic_vector(resize(frame_counter, 8));

    foreground_color <= (others => '1');

    process(clk)
        variable old_vsync : std_logic := '0';

        variable uart_counter : integer range uart_text'range := 1;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                frame_counter <= frame_counter + 1;
            end if;
            old_vsync := vsync;

            uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8));
            uart_valid <= '1';
            if uart_ready = '1' and uart_valid = '1' then
                if uart_counter < uart_text'length then
                    uart_counter := uart_counter + 1;
                else
                    uart_counter := 1;
                end if;
            end if;
        end if;
    end process;
end architecture;


    #FPGA #Icepi-Zero #HDL #VHDL
    #fpga #icepizero #hdl #vhdl
  15. Icepi Zero Bot @[email protected] ·

    @[email protected]

    @[email protected] asked

    library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1'); uart_data : out std_logic_vector(7 downto 0) := (others => '0'); uart_ready : in std_logic; uart_valid : out std_logic := '0' ); end my_code; architecture rtl of my_code is alias red : std_logic_vector(7 downto 0) is background_color(23 downto 16); alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8); alias blue : std_logic_vector(7 downto 0) is background_color(7 downto 0); signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant example_text : string := "Hello Fediverse! <3"; constant example_text_row : integer := 15; constant example_text_col : integer := 15; constant uart_text : string := "Hello Fediverse on UART!" & LF; begin char <= character'pos(example_text(col + 1 - example_text_col)) when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0; red <= std_logic_vector(to_unsigned(col*4, 8)); green <= std_logic_vector(to_unsigned(py, 8)); blue <= std_logic_vector(resize(frame_counter, 8)); foreground_color <= (others => '1'); process(clk) variable old_vsync : std_logic := '0'; variable uart_counter : integer range uart_text'range := 1; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then frame_counter <= frame_counter + 1; end if; old_vsync := vsync; uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8)); uart_valid <= '1'; if uart_ready = '1' and uart_valid = '1' then if uart_counter < uart_text'length then uart_counter := uart_counter + 1; else uart_counter := 1; end if; end if; end if; end process; end architecture;

    Success!

    UART Output

    ... [TRUNCATED] ...
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    UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1171242884.8%TRELLIS_FF177242880.7%TRELLIS_IO111975.6%
    TimingClockAchievedConstraint$glbnet$clkp39.04 MHz25 MHz$glbnet$clkt345.18 MHz250 MHz
    Code

    library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1');

        uart_data : out std_logic_vector(7 downto 0) := (others => '0');
        uart_ready : in std_logic;
        uart_valid : out std_logic := '0'
    );
end my_code;

architecture rtl of my_code is
    alias red   : std_logic_vector(7 downto 0) is background_color(23 downto 16);
    alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8);
    alias blue  : std_logic_vector(7 downto 0) is background_color(7 downto 0);

    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant example_text : string := "Hello Fediverse! <3";
    constant example_text_row : integer := 15;
    constant example_text_col : integer := 15;

    constant uart_text : string := "Hello Fediverse on UART!" & LF;
begin
    char <= character'pos(example_text(col + 1 - example_text_col))
        when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0;

    red   <= std_logic_vector(to_unsigned(col*4, 8));
    green <= std_logic_vector(to_unsigned(py, 8));
    blue  <= std_logic_vector(resize(frame_counter, 8));

    foreground_color <= (others => '1');

    process(clk)
        variable old_vsync : std_logic := '0';

        variable uart_counter : integer range uart_text'range := 1;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                frame_counter <= frame_counter + 1;
            end if;
            old_vsync := vsync;

            uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8));
            uart_valid <= '1';
            if uart_ready = '1' and uart_valid = '1' then
                if uart_counter < uart_text'length then
                    uart_counter := uart_counter + 1;
                else
                    uart_counter := 1;
                end if;
            end if;
        end if;
    end process;
end architecture;


    #FPGA #Icepi-Zero #HDL #VHDL
    #fpga #icepizero #hdl #vhdl
  16. Icepi Zero Bot @[email protected] ·

    @[email protected]

    @[email protected] asked

    library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1'); uart_data : out std_logic_vector(7 downto 0) := (others => '0'); uart_ready : in std_logic; uart_valid : out std_logic := '0' ); end my_code; architecture rtl of my_code is alias red : std_logic_vector(7 downto 0) is background_color(23 downto 16); alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8); alias blue : std_logic_vector(7 downto 0) is background_color(7 downto 0); signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant example_text : string := "Hello Fediverse! <3"; constant example_text_row : integer := 15; constant example_text_col : integer := 15; constant uart_text : string := "Hello Fediverse on UART!" & LF; begin char <= character'pos(example_text(col + 1 - example_text_col)) when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0; red <= std_logic_vector(to_unsigned(col*4, 8)); green <= std_logic_vector(to_unsigned(py, 8)); blue <= std_logic_vector(resize(frame_counter, 8)); foreground_color <= (others => '1'); process(clk) variable old_vsync : std_logic := '0'; variable uart_counter : integer range uart_text'range := 1; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then frame_counter <= frame_counter + 1; end if; old_vsync := vsync; uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8)); uart_valid <= '1'; if uart_ready = '1' and uart_valid = '1' then if uart_counter < uart_text'length then uart_counter := uart_counter + 1; else uart_counter := 1; end if; end if; end if; end process; end architecture;

    Success!

    UART Output

    ... [TRUNCATED] ...
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    UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1171242884.8%TRELLIS_FF177242880.7%TRELLIS_IO111975.6%
    TimingClockAchievedConstraint$glbnet$clkp39.04 MHz25 MHz$glbnet$clkt345.18 MHz250 MHz
    Code

    library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1');

        uart_data : out std_logic_vector(7 downto 0) := (others => '0');
        uart_ready : in std_logic;
        uart_valid : out std_logic := '0'
    );
end my_code;

architecture rtl of my_code is
    alias red   : std_logic_vector(7 downto 0) is background_color(23 downto 16);
    alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8);
    alias blue  : std_logic_vector(7 downto 0) is background_color(7 downto 0);

    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant example_text : string := "Hello Fediverse! <3";
    constant example_text_row : integer := 15;
    constant example_text_col : integer := 15;

    constant uart_text : string := "Hello Fediverse on UART!" & LF;
begin
    char <= character'pos(example_text(col + 1 - example_text_col))
        when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0;

    red   <= std_logic_vector(to_unsigned(col*4, 8));
    green <= std_logic_vector(to_unsigned(py, 8));
    blue  <= std_logic_vector(resize(frame_counter, 8));

    foreground_color <= (others => '1');

    process(clk)
        variable old_vsync : std_logic := '0';

        variable uart_counter : integer range uart_text'range := 1;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                frame_counter <= frame_counter + 1;
            end if;
            old_vsync := vsync;

            uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8));
            uart_valid <= '1';
            if uart_ready = '1' and uart_valid = '1' then
                if uart_counter < uart_text'length then
                    uart_counter := uart_counter + 1;
                else
                    uart_counter := 1;
                end if;
            end if;
        end if;
    end process;
end architecture;


    #FPGA #Icepi-Zero #HDL #VHDL
    #fpga #icepizero #hdl #vhdl
  17. Icepi Zero Bot @[email protected] ·

    @[email protected]

    @[email protected] asked

    library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1'); uart_data : out std_logic_vector(7 downto 0) := (others => '0'); uart_ready : in std_logic; uart_valid : out std_logic := '0' ); end my_code; architecture rtl of my_code is alias red : std_logic_vector(7 downto 0) is background_color(23 downto 16); alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8); alias blue : std_logic_vector(7 downto 0) is background_color(7 downto 0); signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant example_text : string := "Hello Fediverse! <3"; constant example_text_row : integer := 15; constant example_text_col : integer := 15; constant uart_text : string := "Hello Fediverse on UART!" & LF; begin char <= character'pos(example_text(col + 1 - example_text_col)) when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0; red <= std_logic_vector(to_unsigned(col*4, 8)); green <= std_logic_vector(to_unsigned(py, 8)); blue <= std_logic_vector(resize(frame_counter, 8)); foreground_color <= (others => '1'); process(clk) variable old_vsync : std_logic := '0'; variable uart_counter : integer range uart_text'range := 1; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then frame_counter <= frame_counter + 1; end if; old_vsync := vsync; uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8)); uart_valid <= '1'; if uart_ready = '1' and uart_valid = '1' then if uart_counter < uart_text'length then uart_counter := uart_counter + 1; else uart_counter := 1; end if; end if; end if; end process; end architecture;

    Success!

    UART Output

    ... [TRUNCATED] ...
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    UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1171242884.8%TRELLIS_FF177242880.7%TRELLIS_IO111975.6%
    TimingClockAchievedConstraint$glbnet$clkp39.04 MHz25 MHz$glbnet$clkt345.18 MHz250 MHz
    Code

    library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1');

        uart_data : out std_logic_vector(7 downto 0) := (others => '0');
        uart_ready : in std_logic;
        uart_valid : out std_logic := '0'
    );
end my_code;

architecture rtl of my_code is
    alias red   : std_logic_vector(7 downto 0) is background_color(23 downto 16);
    alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8);
    alias blue  : std_logic_vector(7 downto 0) is background_color(7 downto 0);

    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant example_text : string := "Hello Fediverse! <3";
    constant example_text_row : integer := 15;
    constant example_text_col : integer := 15;

    constant uart_text : string := "Hello Fediverse on UART!" & LF;
begin
    char <= character'pos(example_text(col + 1 - example_text_col))
        when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0;

    red   <= std_logic_vector(to_unsigned(col*4, 8));
    green <= std_logic_vector(to_unsigned(py, 8));
    blue  <= std_logic_vector(resize(frame_counter, 8));

    foreground_color <= (others => '1');

    process(clk)
        variable old_vsync : std_logic := '0';

        variable uart_counter : integer range uart_text'range := 1;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                frame_counter <= frame_counter + 1;
            end if;
            old_vsync := vsync;

            uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8));
            uart_valid <= '1';
            if uart_ready = '1' and uart_valid = '1' then
                if uart_counter < uart_text'length then
                    uart_counter := uart_counter + 1;
                else
                    uart_counter := 1;
                end if;
            end if;
        end if;
    end process;
end architecture;


    #FPGA #Icepi-Zero #HDL #VHDL
    #fpga #icepizero #hdl #vhdl
  18. Icepi Zero Bot @[email protected] ·

    @[email protected]

    @[email protected] asked

    library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1'); uart_data : out std_logic_vector(7 downto 0) := (others => '0'); uart_ready : in std_logic; uart_valid : out std_logic := '0' ); end my_code; architecture rtl of my_code is alias red : std_logic_vector(7 downto 0) is background_color(23 downto 16); alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8); alias blue : std_logic_vector(7 downto 0) is background_color(7 downto 0); signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant example_text : string := "Hello Fediverse! <3"; constant example_text_row : integer := 15; constant example_text_col : integer := 15; constant uart_text : string := "Hello Fediverse on UART!" & LF; begin char <= character'pos(example_text(col + 1 - example_text_col)) when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0; red <= std_logic_vector(to_unsigned(col*4, 8)); green <= std_logic_vector(to_unsigned(py, 8)); blue <= std_logic_vector(resize(frame_counter, 8)); foreground_color <= (others => '1'); process(clk) variable old_vsync : std_logic := '0'; variable uart_counter : integer range uart_text'range := 1; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then frame_counter <= frame_counter + 1; end if; old_vsync := vsync; uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8)); uart_valid <= '1'; if uart_ready = '1' and uart_valid = '1' then if uart_counter < uart_text'length then uart_counter := uart_counter + 1; else uart_counter := 1; end if; end if; end if; end process; end architecture;

    Success!

    UART Output

    ... [TRUNCATED] ...
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    UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1171242884.8%TRELLIS_FF177242880.7%TRELLIS_IO111975.6%
    TimingClockAchievedConstraint$glbnet$clkp39.04 MHz25 MHz$glbnet$clkt345.18 MHz250 MHz
    Code

    library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1');

        uart_data : out std_logic_vector(7 downto 0) := (others => '0');
        uart_ready : in std_logic;
        uart_valid : out std_logic := '0'
    );
end my_code;

architecture rtl of my_code is
    alias red   : std_logic_vector(7 downto 0) is background_color(23 downto 16);
    alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8);
    alias blue  : std_logic_vector(7 downto 0) is background_color(7 downto 0);

    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant example_text : string := "Hello Fediverse! <3";
    constant example_text_row : integer := 15;
    constant example_text_col : integer := 15;

    constant uart_text : string := "Hello Fediverse on UART!" & LF;
begin
    char <= character'pos(example_text(col + 1 - example_text_col))
        when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0;

    red   <= std_logic_vector(to_unsigned(col*4, 8));
    green <= std_logic_vector(to_unsigned(py, 8));
    blue  <= std_logic_vector(resize(frame_counter, 8));

    foreground_color <= (others => '1');

    process(clk)
        variable old_vsync : std_logic := '0';

        variable uart_counter : integer range uart_text'range := 1;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                frame_counter <= frame_counter + 1;
            end if;
            old_vsync := vsync;

            uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8));
            uart_valid <= '1';
            if uart_ready = '1' and uart_valid = '1' then
                if uart_counter < uart_text'length then
                    uart_counter := uart_counter + 1;
                else
                    uart_counter := 1;
                end if;
            end if;
        end if;
    end process;
end architecture;


    #FPGA #Icepi-Zero #HDL #VHDL
    #fpga #icepizero #hdl #vhdl
  19. Icepi Zero Bot @[email protected] ·

    @[email protected]

    @[email protected] asked

    library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1'); uart_data : out std_logic_vector(7 downto 0) := (others => '0'); uart_ready : in std_logic; uart_valid : out std_logic := '0' ); end my_code; architecture rtl of my_code is alias red : std_logic_vector(7 downto 0) is background_color(23 downto 16); alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8); alias blue : std_logic_vector(7 downto 0) is background_color(7 downto 0); signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant example_text : string := "Hello Fediverse! <3"; constant example_text_row : integer := 15; constant example_text_col : integer := 15; constant uart_text : string := "Hello Fediverse on UART!" & LF; begin char <= character'pos(example_text(col + 1 - example_text_col)) when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0; red <= std_logic_vector(to_unsigned(col*4, 8)); green <= std_logic_vector(to_unsigned(py, 8)); blue <= std_logic_vector(resize(frame_counter, 8)); foreground_color <= (others => '1'); process(clk) variable old_vsync : std_logic := '0'; variable uart_counter : integer range uart_text'range := 1; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then frame_counter <= frame_counter + 1; end if; old_vsync := vsync; uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8)); uart_valid <= '1'; if uart_ready = '1' and uart_valid = '1' then if uart_counter < uart_text'length then uart_counter := uart_counter + 1; else uart_counter := 1; end if; end if; end if; end process; end architecture;

    Success!

    UART Output

    ... [TRUNCATED] ...
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    UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1171242884.8%TRELLIS_FF177242880.7%TRELLIS_IO111975.6%
    TimingClockAchievedConstraint$glbnet$clkp39.04 MHz25 MHz$glbnet$clkt345.18 MHz250 MHz
    Code

    library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1');

        uart_data : out std_logic_vector(7 downto 0) := (others => '0');
        uart_ready : in std_logic;
        uart_valid : out std_logic := '0'
    );
end my_code;

architecture rtl of my_code is
    alias red   : std_logic_vector(7 downto 0) is background_color(23 downto 16);
    alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8);
    alias blue  : std_logic_vector(7 downto 0) is background_color(7 downto 0);

    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant example_text : string := "Hello Fediverse! <3";
    constant example_text_row : integer := 15;
    constant example_text_col : integer := 15;

    constant uart_text : string := "Hello Fediverse on UART!" & LF;
begin
    char <= character'pos(example_text(col + 1 - example_text_col))
        when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0;

    red   <= std_logic_vector(to_unsigned(col*4, 8));
    green <= std_logic_vector(to_unsigned(py, 8));
    blue  <= std_logic_vector(resize(frame_counter, 8));

    foreground_color <= (others => '1');

    process(clk)
        variable old_vsync : std_logic := '0';

        variable uart_counter : integer range uart_text'range := 1;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                frame_counter <= frame_counter + 1;
            end if;
            old_vsync := vsync;

            uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8));
            uart_valid <= '1';
            if uart_ready = '1' and uart_valid = '1' then
                if uart_counter < uart_text'length then
                    uart_counter := uart_counter + 1;
                else
                    uart_counter := 1;
                end if;
            end if;
        end if;
    end process;
end architecture;


    #FPGA #Icepi-Zero #HDL #VHDL
    #fpga #icepizero #hdl #vhdl
  20. Icepi Zero Bot @[email protected] ·

    @[email protected]

    @[email protected] asked

    library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1'); uart_data : out std_logic_vector(7 downto 0) := (others => '0'); uart_ready : in std_logic; uart_valid : out std_logic := '0' ); end my_code; architecture rtl of my_code is alias red : std_logic_vector(7 downto 0) is background_color(23 downto 16); alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8); alias blue : std_logic_vector(7 downto 0) is background_color(7 downto 0); signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant example_text : string := "Hello Fediverse! <3"; constant example_text_row : integer := 15; constant example_text_col : integer := 15; constant uart_text : string := "Hello Fediverse on UART!" & LF; begin char <= character'pos(example_text(col + 1 - example_text_col)) when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0; red <= std_logic_vector(to_unsigned(col*4, 8)); green <= std_logic_vector(to_unsigned(py, 8)); blue <= std_logic_vector(resize(frame_counter, 8)); foreground_color <= (others => '1'); process(clk) variable old_vsync : std_logic := '0'; variable uart_counter : integer range uart_text'range := 1; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then frame_counter <= frame_counter + 1; end if; old_vsync := vsync; uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8)); uart_valid <= '1'; if uart_ready = '1' and uart_valid = '1' then if uart_counter < uart_text'length then uart_counter := uart_counter + 1; else uart_counter := 1; end if; end if; end if; end process; end architecture;

    Success!

    UART Output

    ... [TRUNCATED] ...
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    UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1171242884.8%TRELLIS_FF177242880.7%TRELLIS_IO111975.6%
    TimingClockAchievedConstraint$glbnet$clkp39.04 MHz25 MHz$glbnet$clkt345.18 MHz250 MHz
    Code

    library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1');

        uart_data : out std_logic_vector(7 downto 0) := (others => '0');
        uart_ready : in std_logic;
        uart_valid : out std_logic := '0'
    );
end my_code;

architecture rtl of my_code is
    alias red   : std_logic_vector(7 downto 0) is background_color(23 downto 16);
    alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8);
    alias blue  : std_logic_vector(7 downto 0) is background_color(7 downto 0);

    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant example_text : string := "Hello Fediverse! <3";
    constant example_text_row : integer := 15;
    constant example_text_col : integer := 15;

    constant uart_text : string := "Hello Fediverse on UART!" & LF;
begin
    char <= character'pos(example_text(col + 1 - example_text_col))
        when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0;

    red   <= std_logic_vector(to_unsigned(col*4, 8));
    green <= std_logic_vector(to_unsigned(py, 8));
    blue  <= std_logic_vector(resize(frame_counter, 8));

    foreground_color <= (others => '1');

    process(clk)
        variable old_vsync : std_logic := '0';

        variable uart_counter : integer range uart_text'range := 1;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                frame_counter <= frame_counter + 1;
            end if;
            old_vsync := vsync;

            uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8));
            uart_valid <= '1';
            if uart_ready = '1' and uart_valid = '1' then
                if uart_counter < uart_text'length then
                    uart_counter := uart_counter + 1;
                else
                    uart_counter := 1;
                end if;
            end if;
        end if;
    end process;
end architecture;


    #FPGA #Icepi-Zero #HDL #VHDL
    #fpga #icepizero #hdl #vhdl
  21. Icepi Zero Bot @[email protected] ·

    @[email protected]

    @[email protected] asked

    library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1'); uart_data : out std_logic_vector(7 downto 0) := (others => '0'); uart_ready : in std_logic; uart_valid : out std_logic := '0' ); end my_code; architecture rtl of my_code is alias red : std_logic_vector(7 downto 0) is background_color(23 downto 16); alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8); alias blue : std_logic_vector(7 downto 0) is background_color(7 downto 0); signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant example_text : string(1 to 20) := "Hello Fediverse! <3" & LF; constant example_text_row : integer := 15; constant example_text_col : integer := 15; begin char <= character'pos(example_text(col + 1 - example_text_col)) when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0; red <= std_logic_vector(to_unsigned(col*4, 8)); green <= std_logic_vector(to_unsigned(py, 8)); blue <= std_logic_vector(resize(frame_counter, 8)); foreground_color <= (others => '1'); process(clk) variable old_vsync : std_logic := '0'; variable uart_counter : integer range example_text'range := 1; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then frame_counter <= frame_counter + 1; end if; old_vsync := vsync; uart_data <= std_logic_vector(to_unsigned(character'pos(example_text(uart_counter)), 8)); uart_valid <= '1'; if uart_ready = '1' and uart_valid = '1' then if uart_counter < example_text'length then uart_counter := uart_counter + 1; else uart_counter := 1; end if; end if; end if; end process; end architecture;

    Success!

    UART Output

    ... [TRUNCATED] ...
 <3
Hello Fediverse! <3
Hello Fediverse! <3
Hello Fediverse! <3
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Hello Fediverse! <3
Hello Fediverse! <3
Hello Fediverse! <3
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    UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1191242884.9%TRELLIS_FF177242880.7%TRELLIS_IO111975.6%
    TimingClockAchievedConstraint$glbnet$clkp41.75 MHz25 MHz$glbnet$clkt333.22 MHz250 MHz
    Code

    library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1');

        uart_data : out std_logic_vector(7 downto 0) := (others => '0');
        uart_ready : in std_logic;
        uart_valid : out std_logic := '0'
    );
end my_code;

architecture rtl of my_code is
    alias red   : std_logic_vector(7 downto 0) is background_color(23 downto 16);
    alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8);
    alias blue  : std_logic_vector(7 downto 0) is background_color(7 downto 0);

    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant example_text : string(1 to 20) := "Hello Fediverse! <3" & LF;
    constant example_text_row : integer := 15;
    constant example_text_col : integer := 15;
begin
    char <= character'pos(example_text(col + 1 - example_text_col))
        when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0;

    red   <= std_logic_vector(to_unsigned(col*4, 8));
    green <= std_logic_vector(to_unsigned(py, 8));
    blue  <= std_logic_vector(resize(frame_counter, 8));

    foreground_color <= (others => '1');

    process(clk)
        variable old_vsync : std_logic := '0';

        variable uart_counter : integer range example_text'range := 1;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                frame_counter <= frame_counter + 1;
            end if;
            old_vsync := vsync;

            uart_data <= std_logic_vector(to_unsigned(character'pos(example_text(uart_counter)), 8));
            uart_valid <= '1';
            if uart_ready = '1' and uart_valid = '1' then
                if uart_counter < example_text'length then
                    uart_counter := uart_counter + 1;
                else
                    uart_counter := 1;
                end if;
            end if;
        end if;
    end process;
end architecture;


    #FPGA #Icepi-Zero #HDL #VHDL
    #fpga #icepizero #hdl #vhdl
  22. Icepi Zero Bot @[email protected] ·

    @[email protected]

    @[email protected] asked

    library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1'); uart_data : out std_logic_vector(7 downto 0) := (others => '0'); uart_ready : in std_logic; uart_valid : out std_logic := '0' ); end my_code; architecture rtl of my_code is alias red : std_logic_vector(7 downto 0) is background_color(23 downto 16); alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8); alias blue : std_logic_vector(7 downto 0) is background_color(7 downto 0); signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant example_text : string(1 to 20) := "Hello Fediverse! <3" & LF; constant example_text_row : integer := 15; constant example_text_col : integer := 15; begin char <= character'pos(example_text(col + 1 - example_text_col)) when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0; red <= std_logic_vector(to_unsigned(col*4, 8)); green <= std_logic_vector(to_unsigned(py, 8)); blue <= std_logic_vector(resize(frame_counter, 8)); foreground_color <= (others => '1'); process(clk) variable old_vsync : std_logic := '0'; variable uart_counter : integer range example_text'range := 1; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then frame_counter <= frame_counter + 1; end if; old_vsync := vsync; uart_data <= std_logic_vector(to_unsigned(character'pos(example_text(uart_counter)), 8)); uart_valid <= '1'; if uart_ready = '1' and uart_valid = '1' then if uart_counter < example_text'length then uart_counter := uart_counter + 1; else uart_counter := 1; end if; end if; end if; end process; end architecture;

    Success!

    UART Output

    ... [TRUNCATED] ...
 <3
Hello Fediverse! <3
Hello Fediverse! <3
Hello Fediverse! <3
Hello Fediverse! <3
Hello Fediverse! <3
Hello Fediverse! <3
Hello Fediverse! <3
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    UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1191242884.9%TRELLIS_FF177242880.7%TRELLIS_IO111975.6%
    TimingClockAchievedConstraint$glbnet$clkp41.75 MHz25 MHz$glbnet$clkt333.22 MHz250 MHz
    Code

    library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1');

        uart_data : out std_logic_vector(7 downto 0) := (others => '0');
        uart_ready : in std_logic;
        uart_valid : out std_logic := '0'
    );
end my_code;

architecture rtl of my_code is
    alias red   : std_logic_vector(7 downto 0) is background_color(23 downto 16);
    alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8);
    alias blue  : std_logic_vector(7 downto 0) is background_color(7 downto 0);

    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant example_text : string(1 to 20) := "Hello Fediverse! <3" & LF;
    constant example_text_row : integer := 15;
    constant example_text_col : integer := 15;
begin
    char <= character'pos(example_text(col + 1 - example_text_col))
        when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0;

    red   <= std_logic_vector(to_unsigned(col*4, 8));
    green <= std_logic_vector(to_unsigned(py, 8));
    blue  <= std_logic_vector(resize(frame_counter, 8));

    foreground_color <= (others => '1');

    process(clk)
        variable old_vsync : std_logic := '0';

        variable uart_counter : integer range example_text'range := 1;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                frame_counter <= frame_counter + 1;
            end if;
            old_vsync := vsync;

            uart_data <= std_logic_vector(to_unsigned(character'pos(example_text(uart_counter)), 8));
            uart_valid <= '1';
            if uart_ready = '1' and uart_valid = '1' then
                if uart_counter < example_text'length then
                    uart_counter := uart_counter + 1;
                else
                    uart_counter := 1;
                end if;
            end if;
        end if;
    end process;
end architecture;


    #FPGA #Icepi-Zero #HDL #VHDL
    #fpga #icepizero #hdl #vhdl
  23. Icepi Zero Bot @[email protected] ·

    @[email protected]

    @[email protected] asked

    library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1'); uart_data : out std_logic_vector(7 downto 0) := (others => '0'); uart_ready : in std_logic; uart_valid : out std_logic := '0' ); end my_code; architecture rtl of my_code is alias red : std_logic_vector(7 downto 0) is background_color(23 downto 16); alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8); alias blue : std_logic_vector(7 downto 0) is background_color(7 downto 0); signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant example_text : string(1 to 19) := "Hello Fediverse! <3"; constant example_text_row : integer := 15; constant example_text_col : integer := 15; begin char <= character'pos(example_text(col + 1 - example_text_col)) when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0; red <= std_logic_vector(to_unsigned(col*4, 8)); green <= std_logic_vector(to_unsigned(py, 8)); blue <= std_logic_vector(resize(frame_counter, 8)); foreground_color <= (others => '1'); process(clk) variable old_vsync : std_logic := '0'; variable uart_counter : integer range example_text'range := 1; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then frame_counter <= frame_counter + 1; end if; old_vsync := vsync; uart_data <= std_logic_vector(to_unsigned(character'pos(example_text(uart_counter)), 8)); uart_valid <= '1'; if uart_ready = '1' and uart_valid = '1' then if uart_counter < example_text'length then uart_counter := uart_counter + 1; else uart_counter := 1; end if; end if; end if; end process; end architecture;

    Success!

    UART Output

    ... [TRUNCATED] ...
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    UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1375242885.7%TRELLIS_FF230242880.9%TRELLIS_IO111975.6%
    TimingClockAchievedConstraint$glbnet$clkp39.66 MHz25 MHz$glbnet$clkt338.87 MHz250 MHz
    Code

    library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1');

        uart_data : out std_logic_vector(7 downto 0) := (others => '0');
        uart_ready : in std_logic;
        uart_valid : out std_logic := '0'
    );
end my_code;

architecture rtl of my_code is
    alias red   : std_logic_vector(7 downto 0) is background_color(23 downto 16);
    alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8);
    alias blue  : std_logic_vector(7 downto 0) is background_color(7 downto 0);

    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant example_text : string(1 to 19) := "Hello Fediverse! <3";
    constant example_text_row : integer := 15;
    constant example_text_col : integer := 15;
begin
    char <= character'pos(example_text(col + 1 - example_text_col))
        when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0;

    red   <= std_logic_vector(to_unsigned(col*4, 8));
    green <= std_logic_vector(to_unsigned(py, 8));
    blue  <= std_logic_vector(resize(frame_counter, 8));

    foreground_color <= (others => '1');

    process(clk)
        variable old_vsync : std_logic := '0';

        variable uart_counter : integer range example_text'range := 1;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                frame_counter <= frame_counter + 1;
            end if;
            old_vsync := vsync;

            uart_data <= std_logic_vector(to_unsigned(character'pos(example_text(uart_counter)), 8));
            uart_valid <= '1';
            if uart_ready = '1' and uart_valid = '1' then
                if uart_counter < example_text'length then
                    uart_counter := uart_counter + 1;
                else
                    uart_counter := 1;
                end if;
            end if;
        end if;
    end process;
end architecture;


    #FPGA #Icepi-Zero #HDL #VHDL
    #fpga #icepizero #hdl #vhdl
  24. Icepi Zero Bot @[email protected] ·

    @[email protected]

    @[email protected] asked

    library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1'); uart_data : out std_logic_vector(7 downto 0) := (others => '0'); uart_ready : in std_logic; uart_valid : out std_logic := '0' ); end my_code; architecture rtl of my_code is alias red : std_logic_vector(7 downto 0) is background_color(23 downto 16); alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8); alias blue : std_logic_vector(7 downto 0) is background_color(7 downto 0); signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant example_text : string(1 to 19) := "Hello Fediverse! <3"; constant example_text_row : integer := 15; constant example_text_col : integer := 15; begin char <= character'pos(example_text(col + 1 - example_text_col)) when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0; red <= std_logic_vector(to_unsigned(col*4, 8)); green <= std_logic_vector(to_unsigned(py, 8)); blue <= std_logic_vector(resize(frame_counter, 8)); foreground_color <= (others => '1'); process(clk) variable old_vsync : std_logic := '0'; variable uart_counter : integer range example_text'range := 1; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then frame_counter <= frame_counter + 1; end if; old_vsync := vsync; uart_data <= std_logic_vector(to_unsigned(character'pos(example_text(uart_counter)), 8)); uart_valid <= '1'; if uart_ready = '1' and uart_valid = '1' then if uart_counter < example_text'length then uart_counter := uart_counter + 1; else uart_counter := 1; end if; end if; end if; end process; end architecture;

    Success!

    UART Output

    ... [TRUNCATED] ...
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BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2


    UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1375242885.7%TRELLIS_FF230242880.9%TRELLIS_IO111975.6%
    TimingClockAchievedConstraint$glbnet$clkp39.66 MHz25 MHz$glbnet$clkt338.87 MHz250 MHz
    Code

    library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1');

        uart_data : out std_logic_vector(7 downto 0) := (others => '0');
        uart_ready : in std_logic;
        uart_valid : out std_logic := '0'
    );
end my_code;

architecture rtl of my_code is
    alias red   : std_logic_vector(7 downto 0) is background_color(23 downto 16);
    alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8);
    alias blue  : std_logic_vector(7 downto 0) is background_color(7 downto 0);

    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant example_text : string(1 to 19) := "Hello Fediverse! <3";
    constant example_text_row : integer := 15;
    constant example_text_col : integer := 15;
begin
    char <= character'pos(example_text(col + 1 - example_text_col))
        when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0;

    red   <= std_logic_vector(to_unsigned(col*4, 8));
    green <= std_logic_vector(to_unsigned(py, 8));
    blue  <= std_logic_vector(resize(frame_counter, 8));

    foreground_color <= (others => '1');

    process(clk)
        variable old_vsync : std_logic := '0';

        variable uart_counter : integer range example_text'range := 1;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                frame_counter <= frame_counter + 1;
            end if;
            old_vsync := vsync;

            uart_data <= std_logic_vector(to_unsigned(character'pos(example_text(uart_counter)), 8));
            uart_valid <= '1';
            if uart_ready = '1' and uart_valid = '1' then
                if uart_counter < example_text'length then
                    uart_counter := uart_counter + 1;
                else
                    uart_counter := 1;
                end if;
            end if;
        end if;
    end process;
end architecture;


    #FPGA #Icepi-Zero #HDL #VHDL
    #fpga #icepizero #hdl #vhdl
  25. Icepi Zero Bot @[email protected] ·

    @[email protected]

    @[email protected] asked

    library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity bouncing_text is generic( CONSOLE_COLUMNS : integer; CONSOLE_ROWS : integer; SPEED : integer := 1; TEXT : string; INIT_X : integer := 0; INIT_Y : integer := 0 ); port ( clk : in std_logic; reset : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; vsync : in std_logic; bounce_x : out std_logic; bounce_y : out std_logic; char : out integer range 0 to 127 := 0 ); end entity bouncing_text; architecture rtl of bouncing_text is signal position_x : integer range -SPEED to CONSOLE_COLUMNS + SPEED := INIT_X; signal position_y : integer range -SPEED to CONSOLE_ROWS + SPEED := INIT_Y; begin char <= character'pos(TEXT(col + 1 - position_x)) when col >= position_x and col < TEXT'length + position_x and row = position_y else 0; process(clk) variable old_vsync : std_logic := '0'; variable speed_x : integer range -SPEED to SPEED := SPEED; variable speed_y : integer range -SPEED to SPEED := SPEED; begin if rising_edge(clk) then bounce_x <= '0'; bounce_y <= '0'; if vsync = '0' and old_vsync = '1' then if position_x + speed_x + TEXT'length >= CONSOLE_COLUMNS then speed_x := -SPEED; position_x <= CONSOLE_COLUMNS - TEXT'length - 1; bounce_x <= '1'; elsif position_x + speed_x < 0 then speed_x := SPEED; position_x <= 0; bounce_x <= '1'; else position_x <= position_x + speed_x; end if; if position_y + speed_y + 1 >= CONSOLE_ROWS then speed_y := -SPEED; position_y <= CONSOLE_ROWS - 1 - 1; bounce_y <= '1'; elsif position_y + speed_y < 0 then speed_y := SPEED; position_y <= 0; bounce_y <= '1'; else position_y <= position_y + speed_y; end if; end if; old_vsync := vsync; end if; end process; end architecture; library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1') ); end my_code; architecture rtl of my_code is signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant text1 : string(1 to 19) := "I am back! Miau~ :3"; constant text2 : string(1 to 13) := "*pat pat pat*"; constant text3 : string(1 to 15) := "nyaaaaaaaaaarge"; signal char1, char2, char3 : integer range 0 to 127 := 0; type rgb_key_array_t is array (0 to 4) of std_logic_vector(23 downto 0); constant rgb_key_array : rgb_key_array_t := (x"5bcffa", x"f5abb9", x"ffffff", x"f5abb9", x"5bcffa"); begin bounce1 : entity work.bouncing_text generic map ( CONSOLE_COLUMNS => CONSOLE_COLUMNS, CONSOLE_ROWS => CONSOLE_ROWS, TEXT => text1, INIT_X => 0, INIT_Y => 0 ) port map ( clk => clk, reset => rst, col => col, row => row, vsync => vsync, bounce_x => open, bounce_y => open, char => char1 ); bounce2 : entity work.bouncing_text generic map ( CONSOLE_COLUMNS => CONSOLE_COLUMNS, CONSOLE_ROWS => CONSOLE_ROWS, TEXT => text2, INIT_X => 15, INIT_Y => 3 ) port map ( clk => clk, reset => rst, col => col, row => row, vsync => vsync, bounce_x => open, bounce_y => open, char => char2 ); bounce3 : entity work.bouncing_text generic map ( CONSOLE_COLUMNS => CONSOLE_COLUMNS, CONSOLE_ROWS => CONSOLE_ROWS, TEXT => text3, INIT_X => 5, INIT_Y => 10 ) port map ( clk => clk, reset => rst, col => col, row => row, vsync => vsync, bounce_x => open, bounce_y => open, char => char3 ); char <= char1 + char2 + char3; foreground_color <= (others => '0'); background_color <= rgb_key_array((py / (HEIGHT / 5)) mod 5); end architecture;

    Success!

    UART Output


    UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1837242887.6%TRELLIS_FF167242880.7%TRELLIS_IO101975.1%
    TimingClockAchievedConstraint$glbnet$clkp47.17 MHz25 MHz$glbnet$clkt350.51 MHz250 MHz
    Code

    library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity bouncing_text is
    generic(
        CONSOLE_COLUMNS : integer;
        CONSOLE_ROWS : integer;
        SPEED : integer := 1;
        TEXT : string;
        INIT_X : integer := 0;
        INIT_Y : integer := 0
    );
    port (
        clk   : in std_logic;
        reset : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;
        vsync : in std_logic;

        bounce_x : out std_logic;
        bounce_y : out std_logic;
        char : out integer range 0 to 127 := 0
    );
end entity bouncing_text;

architecture rtl of bouncing_text is
    signal position_x : integer range -SPEED to CONSOLE_COLUMNS + SPEED := INIT_X;
    signal position_y : integer range -SPEED to CONSOLE_ROWS + SPEED := INIT_Y;
begin
    char <= character'pos(TEXT(col + 1 - position_x))
        when col >= position_x and col < TEXT'length + position_x and row = position_y else 0;

    process(clk)
        variable old_vsync : std_logic := '0';
        variable speed_x : integer range -SPEED to SPEED := SPEED;
        variable speed_y : integer range -SPEED to SPEED := SPEED;
    begin
        if rising_edge(clk) then
            bounce_x <= '0';
            bounce_y <= '0';
            if vsync = '0' and old_vsync = '1' then
                if position_x + speed_x + TEXT'length >= CONSOLE_COLUMNS then
                    speed_x := -SPEED;
                    position_x <= CONSOLE_COLUMNS - TEXT'length - 1;
                    bounce_x <= '1';
                elsif position_x + speed_x < 0 then
                    speed_x := SPEED;
                    position_x <= 0;
                    bounce_x <= '1';
                else
                    position_x <= position_x + speed_x;
                end if;

                if position_y + speed_y + 1 >= CONSOLE_ROWS then
                    speed_y := -SPEED;
                    position_y <= CONSOLE_ROWS - 1 - 1;
                    bounce_y <= '1';
                elsif position_y + speed_y < 0 then
                    speed_y := SPEED;
                    position_y <= 0;
                    bounce_y <= '1';
                else
                    position_y <= position_y + speed_y;
                end if;
            end if;
            old_vsync := vsync;
        end if;
    end process;
end architecture;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1')
    );
end my_code;

architecture rtl of my_code is
    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant text1 : string(1 to 19) := "I am back! Miau~ :3";
    constant text2 : string(1 to 13) := "*pat pat pat*";
    constant text3 : string(1 to 15) := "nyaaaaaaaaaarge";

    signal char1, char2, char3 : integer range 0 to 127 := 0;

    type rgb_key_array_t is array (0 to 4) of std_logic_vector(23 downto 0);
    constant rgb_key_array : rgb_key_array_t := (x"5bcffa", x"f5abb9", x"ffffff", x"f5abb9", x"5bcffa");
begin
    bounce1 : entity work.bouncing_text
        generic map ( CONSOLE_COLUMNS => CONSOLE_COLUMNS, CONSOLE_ROWS => CONSOLE_ROWS, TEXT => text1, INIT_X => 0, INIT_Y => 0 )
        port map ( clk => clk, reset => rst, col => col, row => row, vsync => vsync, bounce_x => open, bounce_y => open, char => char1 );
    bounce2 : entity work.bouncing_text
        generic map ( CONSOLE_COLUMNS => CONSOLE_COLUMNS, CONSOLE_ROWS => CONSOLE_ROWS, TEXT => text2, INIT_X => 15, INIT_Y => 3 )
        port map ( clk => clk, reset => rst, col => col, row => row, vsync => vsync, bounce_x => open, bounce_y => open, char => char2 );
    bounce3 : entity work.bouncing_text
        generic map ( CONSOLE_COLUMNS => CONSOLE_COLUMNS, CONSOLE_ROWS => CONSOLE_ROWS, TEXT => text3, INIT_X => 5, INIT_Y => 10 )
        port map ( clk => clk, reset => rst, col => col, row => row, vsync => vsync, bounce_x => open, bounce_y => open, char => char3 );

    char <= char1 + char2 + char3;

    foreground_color <= (others => '0');
    background_color <= rgb_key_array((py / (HEIGHT / 5)) mod 5);
end architecture;


    #FPGA #Icepi-Zero #HDL #VHDL
    #fpga #icepizero #hdl #vhdl
  26. Icepi Zero Bot @[email protected] ·

    @[email protected]

    @[email protected] asked

    library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity bouncing_text is generic( CONSOLE_COLUMNS : integer; CONSOLE_ROWS : integer; SPEED : integer := 1; TEXT : string; INIT_X : integer := 0; INIT_Y : integer := 0 ); port ( clk : in std_logic; reset : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; vsync : in std_logic; bounce_x : out std_logic; bounce_y : out std_logic; char : out integer range 0 to 127 := 0 ); end entity bouncing_text; architecture rtl of bouncing_text is signal position_x : integer range -SPEED to CONSOLE_COLUMNS + SPEED := INIT_X; signal position_y : integer range -SPEED to CONSOLE_ROWS + SPEED := INIT_Y; begin char <= character'pos(TEXT(col + 1 - position_x)) when col >= position_x and col < TEXT'length + position_x and row = position_y else 0; process(clk) variable old_vsync : std_logic := '0'; variable speed_x : integer range -SPEED to SPEED := SPEED; variable speed_y : integer range -SPEED to SPEED := SPEED; begin if rising_edge(clk) then bounce_x <= '0'; bounce_y <= '0'; if vsync = '0' and old_vsync = '1' then if position_x + speed_x + TEXT'length >= CONSOLE_COLUMNS then speed_x := -SPEED; position_x <= CONSOLE_COLUMNS - TEXT'length - 1; bounce_x <= '1'; elsif position_x + speed_x < 0 then speed_x := SPEED; position_x <= 0; bounce_x <= '1'; else position_x <= position_x + speed_x; end if; if position_y + speed_y + 1 >= CONSOLE_ROWS then speed_y := -SPEED; position_y <= CONSOLE_ROWS - 1 - 1; bounce_y <= '1'; elsif position_y + speed_y < 0 then speed_y := SPEED; position_y <= 0; bounce_y <= '1'; else position_y <= position_y + speed_y; end if; end if; old_vsync := vsync; end if; end process; end architecture; library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1') ); end my_code; architecture rtl of my_code is signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant text1 : string(1 to 19) := "I am back! Miau~ :3"; constant text2 : string(1 to 13) := "*pat pat pat*"; constant text3 : string(1 to 15) := "nyaaaaaaaaaarge"; signal char1, char2, char3 : integer range 0 to 127 := 0; type rgb_key_array_t is array (0 to 4) of std_logic_vector(23 downto 0); constant rgb_key_array : rgb_key_array_t := (x"5bcffa", x"f5abb9", x"ffffff", x"f5abb9", x"5bcffa"); begin bounce1 : entity work.bouncing_text generic map ( CONSOLE_COLUMNS => CONSOLE_COLUMNS, CONSOLE_ROWS => CONSOLE_ROWS, TEXT => text1, INIT_X => 0, INIT_Y => 0 ) port map ( clk => clk, reset => rst, col => col, row => row, vsync => vsync, bounce_x => open, bounce_y => open, char => char1 ); bounce2 : entity work.bouncing_text generic map ( CONSOLE_COLUMNS => CONSOLE_COLUMNS, CONSOLE_ROWS => CONSOLE_ROWS, TEXT => text2, INIT_X => 15, INIT_Y => 3 ) port map ( clk => clk, reset => rst, col => col, row => row, vsync => vsync, bounce_x => open, bounce_y => open, char => char2 ); bounce3 : entity work.bouncing_text generic map ( CONSOLE_COLUMNS => CONSOLE_COLUMNS, CONSOLE_ROWS => CONSOLE_ROWS, TEXT => text3, INIT_X => 5, INIT_Y => 10 ) port map ( clk => clk, reset => rst, col => col, row => row, vsync => vsync, bounce_x => open, bounce_y => open, char => char3 ); char <= char1 + char2 + char3; foreground_color <= (others => '0'); background_color <= rgb_key_array((py / (HEIGHT / 5)) mod 5); end architecture;

    Success!

    UART Output


    UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1837242887.6%TRELLIS_FF167242880.7%TRELLIS_IO101975.1%
    TimingClockAchievedConstraint$glbnet$clkp47.17 MHz25 MHz$glbnet$clkt350.51 MHz250 MHz
    Code

    library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity bouncing_text is
    generic(
        CONSOLE_COLUMNS : integer;
        CONSOLE_ROWS : integer;
        SPEED : integer := 1;
        TEXT : string;
        INIT_X : integer := 0;
        INIT_Y : integer := 0
    );
    port (
        clk   : in std_logic;
        reset : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;
        vsync : in std_logic;

        bounce_x : out std_logic;
        bounce_y : out std_logic;
        char : out integer range 0 to 127 := 0
    );
end entity bouncing_text;

architecture rtl of bouncing_text is
    signal position_x : integer range -SPEED to CONSOLE_COLUMNS + SPEED := INIT_X;
    signal position_y : integer range -SPEED to CONSOLE_ROWS + SPEED := INIT_Y;
begin
    char <= character'pos(TEXT(col + 1 - position_x))
        when col >= position_x and col < TEXT'length + position_x and row = position_y else 0;

    process(clk)
        variable old_vsync : std_logic := '0';
        variable speed_x : integer range -SPEED to SPEED := SPEED;
        variable speed_y : integer range -SPEED to SPEED := SPEED;
    begin
        if rising_edge(clk) then
            bounce_x <= '0';
            bounce_y <= '0';
            if vsync = '0' and old_vsync = '1' then
                if position_x + speed_x + TEXT'length >= CONSOLE_COLUMNS then
                    speed_x := -SPEED;
                    position_x <= CONSOLE_COLUMNS - TEXT'length - 1;
                    bounce_x <= '1';
                elsif position_x + speed_x < 0 then
                    speed_x := SPEED;
                    position_x <= 0;
                    bounce_x <= '1';
                else
                    position_x <= position_x + speed_x;
                end if;

                if position_y + speed_y + 1 >= CONSOLE_ROWS then
                    speed_y := -SPEED;
                    position_y <= CONSOLE_ROWS - 1 - 1;
                    bounce_y <= '1';
                elsif position_y + speed_y < 0 then
                    speed_y := SPEED;
                    position_y <= 0;
                    bounce_y <= '1';
                else
                    position_y <= position_y + speed_y;
                end if;
            end if;
            old_vsync := vsync;
        end if;
    end process;
end architecture;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1')
    );
end my_code;

architecture rtl of my_code is
    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant text1 : string(1 to 19) := "I am back! Miau~ :3";
    constant text2 : string(1 to 13) := "*pat pat pat*";
    constant text3 : string(1 to 15) := "nyaaaaaaaaaarge";

    signal char1, char2, char3 : integer range 0 to 127 := 0;

    type rgb_key_array_t is array (0 to 4) of std_logic_vector(23 downto 0);
    constant rgb_key_array : rgb_key_array_t := (x"5bcffa", x"f5abb9", x"ffffff", x"f5abb9", x"5bcffa");
begin
    bounce1 : entity work.bouncing_text
        generic map ( CONSOLE_COLUMNS => CONSOLE_COLUMNS, CONSOLE_ROWS => CONSOLE_ROWS, TEXT => text1, INIT_X => 0, INIT_Y => 0 )
        port map ( clk => clk, reset => rst, col => col, row => row, vsync => vsync, bounce_x => open, bounce_y => open, char => char1 );
    bounce2 : entity work.bouncing_text
        generic map ( CONSOLE_COLUMNS => CONSOLE_COLUMNS, CONSOLE_ROWS => CONSOLE_ROWS, TEXT => text2, INIT_X => 15, INIT_Y => 3 )
        port map ( clk => clk, reset => rst, col => col, row => row, vsync => vsync, bounce_x => open, bounce_y => open, char => char2 );
    bounce3 : entity work.bouncing_text
        generic map ( CONSOLE_COLUMNS => CONSOLE_COLUMNS, CONSOLE_ROWS => CONSOLE_ROWS, TEXT => text3, INIT_X => 5, INIT_Y => 10 )
        port map ( clk => clk, reset => rst, col => col, row => row, vsync => vsync, bounce_x => open, bounce_y => open, char => char3 );

    char <= char1 + char2 + char3;

    foreground_color <= (others => '0');
    background_color <= rgb_key_array((py / (HEIGHT / 5)) mod 5);
end architecture;


    #FPGA #Icepi-Zero #HDL #VHDL
    #fpga #icepizero #hdl #vhdl
  27. Icepi Zero Bot @[email protected] ·

    @[email protected]

    @[email protected] asked

    library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity bouncing_text is generic( CONSOLE_COLUMNS : integer; CONSOLE_ROWS : integer; SPEED : integer := 1; TEXT : string; INIT_X : integer := 0; INIT_Y : integer := 0 ); port ( clk : in std_logic; reset : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; vsync : in std_logic; bounce_x : out std_logic; bounce_y : out std_logic; char : out integer range 0 to 127 := 0 ); end entity bouncing_text; architecture rtl of bouncing_text is signal position_x : integer range -SPEED to CONSOLE_COLUMNS + SPEED := INIT_X; signal position_y : integer range -SPEED to CONSOLE_ROWS + SPEED := INIT_Y; begin char <= character'pos(TEXT(col + 1 - position_x)) when col >= position_x and col < TEXT'length + position_x and row = position_y else 0; process(clk) variable old_vsync : std_logic := '0'; variable speed_x : integer range -SPEED to SPEED := SPEED; variable speed_y : integer range -SPEED to SPEED := SPEED; begin if rising_edge(clk) then bounce_x <= '0'; bounce_y <= '0'; if vsync = '0' and old_vsync = '1' then if position_x + speed_x + TEXT'length >= CONSOLE_COLUMNS then speed_x := -SPEED; position_x <= CONSOLE_COLUMNS - TEXT'length - 1; bounce_x <= '1'; elsif position_x + speed_x < 0 then speed_x := SPEED; position_x <= 0; bounce_x <= '1'; else position_x <= position_x + speed_x; end if; if position_y + speed_y + 1 >= CONSOLE_ROWS then speed_y := -SPEED; position_y <= CONSOLE_ROWS - 1 - 1; bounce_y <= '1'; elsif position_y + speed_y < 0 then speed_y := SPEED; position_y <= 0; bounce_y <= '1'; else position_y <= position_y + speed_y; end if; end if; old_vsync := vsync; end if; end process; end architecture; library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1') ); end my_code; architecture rtl of my_code is signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant text1 : string(1 to 19) := "I am back! Miau~ :3"; constant text2 : string(1 to 13) := "*pat pat pat*"; signal char1, char2 : integer range 0 to 127 := 0; type rgb_key_array_t is array (0 to 4) of std_logic_vector(23 downto 0); constant rgb_key_array : rgb_key_array_t := (x"5bcffa", x"f5abb9", x"ffffff", x"f5abb9", x"5bcffa"); signal random_bit : std_logic := '0'; signal color : std_logic_vector(23 downto 0) := x"000000"; component OSCG is generic ( DIV : integer := 128 ); port ( OSC : out std_logic ); end component; begin bounce1 : entity work.bouncing_text generic map ( CONSOLE_COLUMNS => CONSOLE_COLUMNS, CONSOLE_ROWS => CONSOLE_ROWS, TEXT => text1, INIT_X => 0, INIT_Y => 0 ) port map ( clk => clk, reset => rst, col => col, row => row, vsync => vsync, bounce_x => open, bounce_y => open, char => char1 ); bounce2 : entity work.bouncing_text generic map ( CONSOLE_COLUMNS => CONSOLE_COLUMNS, CONSOLE_ROWS => CONSOLE_ROWS, TEXT => text2, INIT_X => 15, INIT_Y => 3 ) port map ( clk => clk, reset => rst, col => col, row => row, vsync => vsync, bounce_x => open, bounce_y => open, char => char2 ); char <= char1 + char2; foreground_color <= color; background_color <= rgb_key_array((py / (HEIGHT / 5)) mod 5); rng : OSCG port map ( OSC => random_bit ); end architecture;

    Success!

    UART Output


    UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1464242886.0%TRELLIS_FF150242880.6%TRELLIS_IO101975.1%
    TimingClockAchievedConstraint$glbnet$clkp47.84 MHz25 MHz$glbnet$clkt320.62 MHz250 MHz
    Code

    library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity bouncing_text is
    generic(
        CONSOLE_COLUMNS : integer;
        CONSOLE_ROWS : integer;
        SPEED : integer := 1;
        TEXT : string;
        INIT_X : integer := 0;
        INIT_Y : integer := 0
    );
    port (
        clk   : in std_logic;
        reset : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;
        vsync : in std_logic;

        bounce_x : out std_logic;
        bounce_y : out std_logic;
        char : out integer range 0 to 127 := 0
    );
end entity bouncing_text;

architecture rtl of bouncing_text is
    signal position_x : integer range -SPEED to CONSOLE_COLUMNS + SPEED := INIT_X;
    signal position_y : integer range -SPEED to CONSOLE_ROWS + SPEED := INIT_Y;
begin
    char <= character'pos(TEXT(col + 1 - position_x))
        when col >= position_x and col < TEXT'length + position_x and row = position_y else 0;

    process(clk)
        variable old_vsync : std_logic := '0';
        variable speed_x : integer range -SPEED to SPEED := SPEED;
        variable speed_y : integer range -SPEED to SPEED := SPEED;
    begin
        if rising_edge(clk) then
            bounce_x <= '0';
            bounce_y <= '0';
            if vsync = '0' and old_vsync = '1' then
                if position_x + speed_x + TEXT'length >= CONSOLE_COLUMNS then
                    speed_x := -SPEED;
                    position_x <= CONSOLE_COLUMNS - TEXT'length - 1;
                    bounce_x <= '1';
                elsif position_x + speed_x < 0 then
                    speed_x := SPEED;
                    position_x <= 0;
                    bounce_x <= '1';
                else
                    position_x <= position_x + speed_x;
                end if;

                if position_y + speed_y + 1 >= CONSOLE_ROWS then
                    speed_y := -SPEED;
                    position_y <= CONSOLE_ROWS - 1 - 1;
                    bounce_y <= '1';
                elsif position_y + speed_y < 0 then
                    speed_y := SPEED;
                    position_y <= 0;
                    bounce_y <= '1';
                else
                    position_y <= position_y + speed_y;
                end if;
            end if;
            old_vsync := vsync;
        end if;
    end process;
end architecture;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1')
    );
end my_code;

architecture rtl of my_code is
    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant text1 : string(1 to 19) := "I am back! Miau~ :3";
    constant text2 : string(1 to 13) := "*pat pat pat*";

    signal char1, char2 : integer range 0 to 127 := 0;

    type rgb_key_array_t is array (0 to 4) of std_logic_vector(23 downto 0);
    constant rgb_key_array : rgb_key_array_t := (x"5bcffa", x"f5abb9", x"ffffff", x"f5abb9", x"5bcffa");

    signal random_bit : std_logic := '0';
    signal color : std_logic_vector(23 downto 0) := x"000000";

    component OSCG is
        generic (
            DIV : integer := 128
        );
        port (
            OSC : out std_logic
        );
    end component;
begin
    bounce1 : entity work.bouncing_text
        generic map (
            CONSOLE_COLUMNS => CONSOLE_COLUMNS, CONSOLE_ROWS => CONSOLE_ROWS,
            TEXT => text1, INIT_X => 0, INIT_Y => 0
        )
        port map (
            clk => clk, reset => rst,
            col => col, row => row, vsync => vsync,
            bounce_x => open, bounce_y => open,
            char => char1
        );
    bounce2 : entity work.bouncing_text
        generic map (
            CONSOLE_COLUMNS => CONSOLE_COLUMNS, CONSOLE_ROWS => CONSOLE_ROWS,
            TEXT => text2, INIT_X => 15, INIT_Y => 3
        )
        port map (
            clk => clk, reset => rst,
            col => col, row => row, vsync => vsync,
            bounce_x => open, bounce_y => open,
            char => char2
        );

    char <= char1 + char2;

    foreground_color <= color;
    background_color <= rgb_key_array((py / (HEIGHT / 5)) mod 5);

    rng : OSCG port map (
        OSC => random_bit
    );
end architecture;


    #FPGA #Icepi-Zero #HDL #VHDL
    #fpga #icepizero #hdl #vhdl
  28. Icepi Zero Bot @[email protected] ·

    @[email protected]

    @[email protected] asked

    library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity bouncing_text is generic( CONSOLE_COLUMNS : integer; CONSOLE_ROWS : integer; SPEED : integer := 1; TEXT : string; INIT_X : integer := 0; INIT_Y : integer := 0 ); port ( clk : in std_logic; reset : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; vsync : in std_logic; bounce_x : out std_logic; bounce_y : out std_logic; char : out integer range 0 to 127 := 0 ); end entity bouncing_text; architecture rtl of bouncing_text is signal position_x : integer range -SPEED to CONSOLE_COLUMNS + SPEED := INIT_X; signal position_y : integer range -SPEED to CONSOLE_ROWS + SPEED := INIT_Y; begin char <= character'pos(TEXT(col + 1 - position_x)) when col >= position_x and col < TEXT'length + position_x and row = position_y else 0; process(clk) variable old_vsync : std_logic := '0'; variable speed_x : integer range -SPEED to SPEED := SPEED; variable speed_y : integer range -SPEED to SPEED := SPEED; begin if rising_edge(clk) then bounce_x <= '0'; bounce_y <= '0'; if vsync = '0' and old_vsync = '1' then if position_x + speed_x + TEXT'length >= CONSOLE_COLUMNS then speed_x := -SPEED; position_x <= CONSOLE_COLUMNS - TEXT'length - 1; bounce_x <= '1'; elsif position_x + speed_x < 0 then speed_x := SPEED; position_x <= 0; bounce_x <= '1'; else position_x <= position_x + speed_x; end if; if position_y + speed_y + 1 >= CONSOLE_ROWS then speed_y := -SPEED; position_y <= CONSOLE_ROWS - 1 - 1; bounce_y <= '1'; elsif position_y + speed_y < 0 then speed_y := SPEED; position_y <= 0; bounce_y <= '1'; else position_y <= position_y + speed_y; end if; end if; old_vsync := vsync; end if; end process; end architecture; library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1') ); end my_code; architecture rtl of my_code is signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant text1 : string(1 to 19) := "I am back! Miau~ :3"; constant text2 : string(1 to 13) := "*pat pat pat*"; signal char1, char2 : integer range 0 to 127 := 0; type rgb_key_array_t is array (0 to 4) of std_logic_vector(23 downto 0); constant rgb_key_array : rgb_key_array_t := (x"5bcffa", x"f5abb9", x"ffffff", x"f5abb9", x"5bcffa"); signal random_bit : std_logic := '0'; signal color : std_logic_vector(23 downto 0) := x"000000"; component OSCG is generic ( DIV : integer := 128 ); port ( OSC : out std_logic ); end component; begin bounce1 : entity work.bouncing_text generic map ( CONSOLE_COLUMNS => CONSOLE_COLUMNS, CONSOLE_ROWS => CONSOLE_ROWS, TEXT => text1, INIT_X => 0, INIT_Y => 0 ) port map ( clk => clk, reset => rst, col => col, row => row, vsync => vsync, bounce_x => open, bounce_y => open, char => char1 ); bounce2 : entity work.bouncing_text generic map ( CONSOLE_COLUMNS => CONSOLE_COLUMNS, CONSOLE_ROWS => CONSOLE_ROWS, TEXT => text2, INIT_X => 15, INIT_Y => 3 ) port map ( clk => clk, reset => rst, col => col, row => row, vsync => vsync, bounce_x => open, bounce_y => open, char => char2 ); char <= char1 + char2; foreground_color <= color; background_color <= rgb_key_array((py / (HEIGHT / 5)) mod 5); rng : OSCG port map ( OSC => random_bit ); end architecture;

    Success!

    UART Output


    UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1464242886.0%TRELLIS_FF150242880.6%TRELLIS_IO101975.1%
    TimingClockAchievedConstraint$glbnet$clkp47.84 MHz25 MHz$glbnet$clkt320.62 MHz250 MHz
    Code

    library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity bouncing_text is
    generic(
        CONSOLE_COLUMNS : integer;
        CONSOLE_ROWS : integer;
        SPEED : integer := 1;
        TEXT : string;
        INIT_X : integer := 0;
        INIT_Y : integer := 0
    );
    port (
        clk   : in std_logic;
        reset : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;
        vsync : in std_logic;

        bounce_x : out std_logic;
        bounce_y : out std_logic;
        char : out integer range 0 to 127 := 0
    );
end entity bouncing_text;

architecture rtl of bouncing_text is
    signal position_x : integer range -SPEED to CONSOLE_COLUMNS + SPEED := INIT_X;
    signal position_y : integer range -SPEED to CONSOLE_ROWS + SPEED := INIT_Y;
begin
    char <= character'pos(TEXT(col + 1 - position_x))
        when col >= position_x and col < TEXT'length + position_x and row = position_y else 0;

    process(clk)
        variable old_vsync : std_logic := '0';
        variable speed_x : integer range -SPEED to SPEED := SPEED;
        variable speed_y : integer range -SPEED to SPEED := SPEED;
    begin
        if rising_edge(clk) then
            bounce_x <= '0';
            bounce_y <= '0';
            if vsync = '0' and old_vsync = '1' then
                if position_x + speed_x + TEXT'length >= CONSOLE_COLUMNS then
                    speed_x := -SPEED;
                    position_x <= CONSOLE_COLUMNS - TEXT'length - 1;
                    bounce_x <= '1';
                elsif position_x + speed_x < 0 then
                    speed_x := SPEED;
                    position_x <= 0;
                    bounce_x <= '1';
                else
                    position_x <= position_x + speed_x;
                end if;

                if position_y + speed_y + 1 >= CONSOLE_ROWS then
                    speed_y := -SPEED;
                    position_y <= CONSOLE_ROWS - 1 - 1;
                    bounce_y <= '1';
                elsif position_y + speed_y < 0 then
                    speed_y := SPEED;
                    position_y <= 0;
                    bounce_y <= '1';
                else
                    position_y <= position_y + speed_y;
                end if;
            end if;
            old_vsync := vsync;
        end if;
    end process;
end architecture;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1')
    );
end my_code;

architecture rtl of my_code is
    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant text1 : string(1 to 19) := "I am back! Miau~ :3";
    constant text2 : string(1 to 13) := "*pat pat pat*";

    signal char1, char2 : integer range 0 to 127 := 0;

    type rgb_key_array_t is array (0 to 4) of std_logic_vector(23 downto 0);
    constant rgb_key_array : rgb_key_array_t := (x"5bcffa", x"f5abb9", x"ffffff", x"f5abb9", x"5bcffa");

    signal random_bit : std_logic := '0';
    signal color : std_logic_vector(23 downto 0) := x"000000";

    component OSCG is
        generic (
            DIV : integer := 128
        );
        port (
            OSC : out std_logic
        );
    end component;
begin
    bounce1 : entity work.bouncing_text
        generic map (
            CONSOLE_COLUMNS => CONSOLE_COLUMNS, CONSOLE_ROWS => CONSOLE_ROWS,
            TEXT => text1, INIT_X => 0, INIT_Y => 0
        )
        port map (
            clk => clk, reset => rst,
            col => col, row => row, vsync => vsync,
            bounce_x => open, bounce_y => open,
            char => char1
        );
    bounce2 : entity work.bouncing_text
        generic map (
            CONSOLE_COLUMNS => CONSOLE_COLUMNS, CONSOLE_ROWS => CONSOLE_ROWS,
            TEXT => text2, INIT_X => 15, INIT_Y => 3
        )
        port map (
            clk => clk, reset => rst,
            col => col, row => row, vsync => vsync,
            bounce_x => open, bounce_y => open,
            char => char2
        );

    char <= char1 + char2;

    foreground_color <= color;
    background_color <= rgb_key_array((py / (HEIGHT / 5)) mod 5);

    rng : OSCG port map (
        OSC => random_bit
    );
end architecture;


    #FPGA #Icepi-Zero #HDL #VHDL
    #fpga #icepizero #hdl #vhdl
  29. Icepi Zero Bot @[email protected] ·

    @[email protected]

    @[email protected] asked

    library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity bouncing_text is generic( CONSOLE_COLUMNS : integer; CONSOLE_ROWS : integer; SPEED : integer := 1; TEXT : string; INIT_X : integer := 0; INIT_Y : integer := 0 ); port ( clk : in std_logic; reset : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; vsync : in std_logic; bounce_x : out std_logic; bounce_y : out std_logic; char : out integer range 0 to 127 := 0 ); end entity bouncing_text; architecture rtl of bouncing_text is signal position_x : integer range -SPEED to CONSOLE_COLUMNS + SPEED := INIT_X; signal position_y : integer range -SPEED to CONSOLE_ROWS + SPEED := INIT_Y; begin char <= character'pos(TEXT(col + 1 - position_x)) when col >= position_x and col < TEXT'length + position_x and row = position_y else 0; process(clk) variable old_vsync : std_logic := '0'; variable speed_x : integer range -SPEED to SPEED := SPEED; variable speed_y : integer range -SPEED to SPEED := SPEED; begin if rising_edge(clk) then bounce_x <= '0'; bounce_y <= '0'; if vsync = '0' and old_vsync = '1' then if position_x + speed_x + TEXT'length >= CONSOLE_COLUMNS then speed_x := -SPEED; position_x <= CONSOLE_COLUMNS - TEXT'length - 1; bounce_x <= '1'; elsif position_x + speed_x < 0 then speed_x := SPEED; position_x <= 0; bounce_x <= '1'; else position_x <= position_x + speed_x; end if; if position_y + speed_y + 1 >= CONSOLE_ROWS then speed_y := -SPEED; position_y <= CONSOLE_ROWS - 1 - 1; bounce_y <= '1'; elsif position_y + speed_y < 0 then speed_y := SPEED; position_y <= 0; bounce_y <= '1'; else position_y <= position_y + speed_y; end if; end if; old_vsync := vsync; end if; end process; end architecture; library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1') ); end my_code; architecture rtl of my_code is signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant text1 : string(1 to 19) := "I am back! Miau~ :3"; constant text2 : string(1 to 19) := "I am back! Miau~ :3"; type rgb_key_array_t is array (0 to 4) of std_logic_vector(23 downto 0); constant rgb_key_array : rgb_key_array_t := (x"5bcffa", x"f5abb9", x"ffffff", x"f5abb9", x"5bcffa"); signal random_bit : std_logic := '0'; signal color : std_logic_vector(23 downto 0) := x"000000"; component OSCG is generic ( DIV : integer := 128 ); port ( OSC : out std_logic ); end component; begin bounce1 : entity work.bouncing_text generic map ( CONSOLE_COLUMNS => CONSOLE_COLUMNS, CONSOLE_ROWS => CONSOLE_ROWS, TEXT => text1 ) port map ( clk => clk, reset => rst, col => col, row => row, vsync => vsync, bounce_x => open, bounce_y => open, char => char ); foreground_color <= color; background_color <= rgb_key_array((py / (HEIGHT / 5)) mod 5); rng : OSCG port map ( OSC => random_bit ); end architecture;

    Success!

    UART Output


    UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB966242884.0%TRELLIS_FF133242880.5%TRELLIS_IO101975.1%
    TimingClockAchievedConstraint$glbnet$clkp56.02 MHz25 MHz$glbnet$clkt365.1 MHz250 MHz
    Code

    library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity bouncing_text is
    generic(
        CONSOLE_COLUMNS : integer;
        CONSOLE_ROWS : integer;
        SPEED : integer := 1;
        TEXT : string;
        INIT_X : integer := 0;
        INIT_Y : integer := 0
    );
    port (
        clk   : in std_logic;
        reset : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;
        vsync : in std_logic;

        bounce_x : out std_logic;
        bounce_y : out std_logic;
        char : out integer range 0 to 127 := 0
    );
end entity bouncing_text;

architecture rtl of bouncing_text is
    signal position_x : integer range -SPEED to CONSOLE_COLUMNS + SPEED := INIT_X;
    signal position_y : integer range -SPEED to CONSOLE_ROWS + SPEED := INIT_Y;
begin
    char <= character'pos(TEXT(col + 1 - position_x))
        when col >= position_x and col < TEXT'length + position_x and row = position_y else 0;

    process(clk)
        variable old_vsync : std_logic := '0';
        variable speed_x : integer range -SPEED to SPEED := SPEED;
        variable speed_y : integer range -SPEED to SPEED := SPEED;
    begin
        if rising_edge(clk) then
            bounce_x <= '0';
            bounce_y <= '0';
            if vsync = '0' and old_vsync = '1' then
                if position_x + speed_x + TEXT'length >= CONSOLE_COLUMNS then
                    speed_x := -SPEED;
                    position_x <= CONSOLE_COLUMNS - TEXT'length - 1;
                    bounce_x <= '1';
                elsif position_x + speed_x < 0 then
                    speed_x := SPEED;
                    position_x <= 0;
                    bounce_x <= '1';
                else
                    position_x <= position_x + speed_x;
                end if;

                if position_y + speed_y + 1 >= CONSOLE_ROWS then
                    speed_y := -SPEED;
                    position_y <= CONSOLE_ROWS - 1 - 1;
                    bounce_y <= '1';
                elsif position_y + speed_y < 0 then
                    speed_y := SPEED;
                    position_y <= 0;
                    bounce_y <= '1';
                else
                    position_y <= position_y + speed_y;
                end if;
            end if;
            old_vsync := vsync;
        end if;
    end process;
end architecture;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1')
    );
end my_code;

architecture rtl of my_code is
    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant text1 : string(1 to 19) := "I am back! Miau~ :3";
    constant text2 : string(1 to 19) := "I am back! Miau~ :3";

    type rgb_key_array_t is array (0 to 4) of std_logic_vector(23 downto 0);
    constant rgb_key_array : rgb_key_array_t := (x"5bcffa", x"f5abb9", x"ffffff", x"f5abb9", x"5bcffa");

    signal random_bit : std_logic := '0';
    signal color : std_logic_vector(23 downto 0) := x"000000";

    component OSCG is
        generic (
            DIV : integer := 128
        );
        port (
            OSC : out std_logic
        );
    end component;
begin
    bounce1 : entity work.bouncing_text
        generic map (
            CONSOLE_COLUMNS => CONSOLE_COLUMNS,
            CONSOLE_ROWS => CONSOLE_ROWS,
            TEXT => text1
        )
        port map (
            clk => clk,
            reset => rst,

            col => col,
            row => row,
            vsync => vsync,

            bounce_x => open,
            bounce_y => open,
            char => char
        );

    foreground_color <= color;
    background_color <= rgb_key_array((py / (HEIGHT / 5)) mod 5);

    rng : OSCG port map (
        OSC => random_bit
    );
end architecture;


    #FPGA #Icepi-Zero #HDL #VHDL
    #fpga #icepizero #hdl #vhdl
  30. Icepi Zero Bot @[email protected] ·

    @[email protected]

    @[email protected] asked

    library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity bouncing_text is generic( CONSOLE_COLUMNS : integer; CONSOLE_ROWS : integer; SPEED : integer := 1; TEXT : string; INIT_X : integer := 0; INIT_Y : integer := 0 ); port ( clk : in std_logic; reset : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; vsync : in std_logic; bounce_x : out std_logic; bounce_y : out std_logic; char : out integer range 0 to 127 := 0 ); end entity bouncing_text; architecture rtl of bouncing_text is signal position_x : integer range -SPEED to CONSOLE_COLUMNS + SPEED := INIT_X; signal position_y : integer range -SPEED to CONSOLE_ROWS + SPEED := INIT_Y; begin char <= character'pos(TEXT(col + 1 - position_x)) when col >= position_x and col < TEXT'length + position_x and row = position_y else 0; process(clk) variable old_vsync : std_logic := '0'; variable speed_x : integer range -SPEED to SPEED := SPEED; variable speed_y : integer range -SPEED to SPEED := SPEED; begin if rising_edge(clk) then bounce_x <= '0'; bounce_y <= '0'; if vsync = '0' and old_vsync = '1' then if position_x + speed_x + TEXT'length >= CONSOLE_COLUMNS then speed_x := -SPEED; position_x <= CONSOLE_COLUMNS - TEXT'length - 1; bounce_x <= '1'; elsif position_x + speed_x < 0 then speed_x := SPEED; position_x <= 0; bounce_x <= '1'; else position_x <= position_x + speed_x; end if; if position_y + speed_y + 1 >= CONSOLE_ROWS then speed_y := -SPEED; position_y <= CONSOLE_ROWS - 1 - 1; bounce_y <= '1'; elsif position_y + speed_y < 0 then speed_y := SPEED; position_y <= 0; bounce_y <= '1'; else position_y <= position_y + speed_y; end if; end if; old_vsync := vsync; end if; end process; end architecture; library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1') ); end my_code; architecture rtl of my_code is signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant text1 : string(1 to 19) := "I am back! Miau~ :3"; constant text2 : string(1 to 19) := "I am back! Miau~ :3"; type rgb_key_array_t is array (0 to 4) of std_logic_vector(23 downto 0); constant rgb_key_array : rgb_key_array_t := (x"5bcffa", x"f5abb9", x"ffffff", x"f5abb9", x"5bcffa"); signal random_bit : std_logic := '0'; signal color : std_logic_vector(23 downto 0) := x"000000"; component OSCG is generic ( DIV : integer := 128 ); port ( OSC : out std_logic ); end component; begin bounce1 : entity work.bouncing_text generic map ( CONSOLE_COLUMNS => CONSOLE_COLUMNS, CONSOLE_ROWS => CONSOLE_ROWS, TEXT => text1 ) port map ( clk => clk, reset => rst, col => col, row => row, vsync => vsync, bounce_x => open, bounce_y => open, char => char ); foreground_color <= color; background_color <= rgb_key_array((py / (HEIGHT / 5)) mod 5); rng : OSCG port map ( OSC => random_bit ); end architecture;

    Success!

    UART Output


    UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB966242884.0%TRELLIS_FF133242880.5%TRELLIS_IO101975.1%
    TimingClockAchievedConstraint$glbnet$clkp56.02 MHz25 MHz$glbnet$clkt365.1 MHz250 MHz
    Code

    library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity bouncing_text is
    generic(
        CONSOLE_COLUMNS : integer;
        CONSOLE_ROWS : integer;
        SPEED : integer := 1;
        TEXT : string;
        INIT_X : integer := 0;
        INIT_Y : integer := 0
    );
    port (
        clk   : in std_logic;
        reset : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;
        vsync : in std_logic;

        bounce_x : out std_logic;
        bounce_y : out std_logic;
        char : out integer range 0 to 127 := 0
    );
end entity bouncing_text;

architecture rtl of bouncing_text is
    signal position_x : integer range -SPEED to CONSOLE_COLUMNS + SPEED := INIT_X;
    signal position_y : integer range -SPEED to CONSOLE_ROWS + SPEED := INIT_Y;
begin
    char <= character'pos(TEXT(col + 1 - position_x))
        when col >= position_x and col < TEXT'length + position_x and row = position_y else 0;

    process(clk)
        variable old_vsync : std_logic := '0';
        variable speed_x : integer range -SPEED to SPEED := SPEED;
        variable speed_y : integer range -SPEED to SPEED := SPEED;
    begin
        if rising_edge(clk) then
            bounce_x <= '0';
            bounce_y <= '0';
            if vsync = '0' and old_vsync = '1' then
                if position_x + speed_x + TEXT'length >= CONSOLE_COLUMNS then
                    speed_x := -SPEED;
                    position_x <= CONSOLE_COLUMNS - TEXT'length - 1;
                    bounce_x <= '1';
                elsif position_x + speed_x < 0 then
                    speed_x := SPEED;
                    position_x <= 0;
                    bounce_x <= '1';
                else
                    position_x <= position_x + speed_x;
                end if;

                if position_y + speed_y + 1 >= CONSOLE_ROWS then
                    speed_y := -SPEED;
                    position_y <= CONSOLE_ROWS - 1 - 1;
                    bounce_y <= '1';
                elsif position_y + speed_y < 0 then
                    speed_y := SPEED;
                    position_y <= 0;
                    bounce_y <= '1';
                else
                    position_y <= position_y + speed_y;
                end if;
            end if;
            old_vsync := vsync;
        end if;
    end process;
end architecture;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1')
    );
end my_code;

architecture rtl of my_code is
    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant text1 : string(1 to 19) := "I am back! Miau~ :3";
    constant text2 : string(1 to 19) := "I am back! Miau~ :3";

    type rgb_key_array_t is array (0 to 4) of std_logic_vector(23 downto 0);
    constant rgb_key_array : rgb_key_array_t := (x"5bcffa", x"f5abb9", x"ffffff", x"f5abb9", x"5bcffa");

    signal random_bit : std_logic := '0';
    signal color : std_logic_vector(23 downto 0) := x"000000";

    component OSCG is
        generic (
            DIV : integer := 128
        );
        port (
            OSC : out std_logic
        );
    end component;
begin
    bounce1 : entity work.bouncing_text
        generic map (
            CONSOLE_COLUMNS => CONSOLE_COLUMNS,
            CONSOLE_ROWS => CONSOLE_ROWS,
            TEXT => text1
        )
        port map (
            clk => clk,
            reset => rst,

            col => col,
            row => row,
            vsync => vsync,

            bounce_x => open,
            bounce_y => open,
            char => char
        );

    foreground_color <= color;
    background_color <= rgb_key_array((py / (HEIGHT / 5)) mod 5);

    rng : OSCG port map (
        OSC => random_bit
    );
end architecture;


    #FPGA #Icepi-Zero #HDL #VHDL
    #fpga #icepizero #hdl #vhdl
  31. Icepi Zero Bot @[email protected] ·

    @[email protected]

    @[email protected] asked

    library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity bouncing_text is generic( CONSOLE_COLUMNS : integer; CONSOLE_ROWS : integer; SPEED : integer := 1; TEXT : string; INIT_X : integer := 0; INIT_Y : integer := 0 ); port ( clk : in std_logic; reset : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; vsync : in std_logic; bounce_x : out std_logic; bounce_y : out std_logic; char : out integer range 0 to 127 := 0 ); end entity bouncing_text; architecture rtl of bouncing_text is signal position_x : integer range -SPEED to CONSOLE_COLUMNS + SPEED := INIT_X; signal position_y : integer range -SPEED to CONSOLE_ROWS + SPEED := INIT_Y; begin char <= character'pos(TEXT(col + 1 - position_x)) when col >= position_x and col < TEXT'length + position_x and row = position_y else 0; process(clk) variable old_vsync : std_logic := '0'; variable speed_x : integer range -SPEED to SPEED := SPEED; variable speed_y : integer range -SPEED to SPEED := SPEED; begin if rising_edge(clk) then bounce_x <= '0'; bounce_y <= '0'; if vsync = '0' and old_vsync = '1' then if position_x + speed_x + TEXT'length >= CONSOLE_COLUMNS then speed_x := -SPEED; position_x <= CONSOLE_COLUMNS - TEXT'length - 1; bounce_x <= '1'; elsif position_x + speed_x < 0 then speed_x := SPEED; position_x <= 0; bounce_x <= '1'; else position_x <= position_x + speed_x; end if; if position_y + speed_y + 1 >= CONSOLE_ROWS then speed_y := -SPEED; position_y <= CONSOLE_ROWS - 1 - 1; bounce_y <= '1'; elsif position_y + speed_y < 0 then speed_y := SPEED; position_y <= 0; bounce_y <= '1'; else position_y <= position_y + speed_y; end if; end if; old_vsync := vsync; end if; end process; end architecture; library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1') ); end my_code; architecture rtl of my_code is signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant text1 : string(1 to 19) := "I am back! Miau~ :3"; constant text2 : string(1 to 19) := "I am back! Miau~ :3"; type rgb_key_array_t is array (0 to 4) of std_logic_vector(23 downto 0); constant rgb_key_array : rgb_key_array_t := (x"5bcffa", x"f5abb9", x"ffffff", x"f5abb9", x"5bcffa"); signal random_bit : std_logic := '0'; signal color : std_logic_vector(23 downto 0) := x"000000"; component OSCG is generic ( DIV : integer := 128 ); port ( OSC : out std_logic ); end component; begin bounce1 : entity work.bouncing_text generic map ( CONSOLE_COLUMNS => CONSOLE_COLUMNS, CONSOLE_ROWS => CONSOLE_ROWS, TEXT => text1 ) port map ( clk => clk, reset => rst, col => col, row => row, vsync => vsync, bounce_x => open, bounce_y => open, char => char ); foreground_color <= color; background_color <= rgb_key_array((py / (HEIGHT / 5)) mod 5); rng : OSCG port map ( OSC => random_bit ); end architecture;

    Success!

    UART Output


    UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB966242884.0%TRELLIS_FF133242880.5%TRELLIS_IO101975.1%
    TimingClockAchievedConstraint$glbnet$clkp56.02 MHz25 MHz$glbnet$clkt365.1 MHz250 MHz
    Code

    library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity bouncing_text is
    generic(
        CONSOLE_COLUMNS : integer;
        CONSOLE_ROWS : integer;
        SPEED : integer := 1;
        TEXT : string;
        INIT_X : integer := 0;
        INIT_Y : integer := 0
    );
    port (
        clk   : in std_logic;
        reset : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;
        vsync : in std_logic;

        bounce_x : out std_logic;
        bounce_y : out std_logic;
        char : out integer range 0 to 127 := 0
    );
end entity bouncing_text;

architecture rtl of bouncing_text is
    signal position_x : integer range -SPEED to CONSOLE_COLUMNS + SPEED := INIT_X;
    signal position_y : integer range -SPEED to CONSOLE_ROWS + SPEED := INIT_Y;
begin
    char <= character'pos(TEXT(col + 1 - position_x))
        when col >= position_x and col < TEXT'length + position_x and row = position_y else 0;

    process(clk)
        variable old_vsync : std_logic := '0';
        variable speed_x : integer range -SPEED to SPEED := SPEED;
        variable speed_y : integer range -SPEED to SPEED := SPEED;
    begin
        if rising_edge(clk) then
            bounce_x <= '0';
            bounce_y <= '0';
            if vsync = '0' and old_vsync = '1' then
                if position_x + speed_x + TEXT'length >= CONSOLE_COLUMNS then
                    speed_x := -SPEED;
                    position_x <= CONSOLE_COLUMNS - TEXT'length - 1;
                    bounce_x <= '1';
                elsif position_x + speed_x < 0 then
                    speed_x := SPEED;
                    position_x <= 0;
                    bounce_x <= '1';
                else
                    position_x <= position_x + speed_x;
                end if;

                if position_y + speed_y + 1 >= CONSOLE_ROWS then
                    speed_y := -SPEED;
                    position_y <= CONSOLE_ROWS - 1 - 1;
                    bounce_y <= '1';
                elsif position_y + speed_y < 0 then
                    speed_y := SPEED;
                    position_y <= 0;
                    bounce_y <= '1';
                else
                    position_y <= position_y + speed_y;
                end if;
            end if;
            old_vsync := vsync;
        end if;
    end process;
end architecture;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1')
    );
end my_code;

architecture rtl of my_code is
    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant text1 : string(1 to 19) := "I am back! Miau~ :3";
    constant text2 : string(1 to 19) := "I am back! Miau~ :3";

    type rgb_key_array_t is array (0 to 4) of std_logic_vector(23 downto 0);
    constant rgb_key_array : rgb_key_array_t := (x"5bcffa", x"f5abb9", x"ffffff", x"f5abb9", x"5bcffa");

    signal random_bit : std_logic := '0';
    signal color : std_logic_vector(23 downto 0) := x"000000";

    component OSCG is
        generic (
            DIV : integer := 128
        );
        port (
            OSC : out std_logic
        );
    end component;
begin
    bounce1 : entity work.bouncing_text
        generic map (
            CONSOLE_COLUMNS => CONSOLE_COLUMNS,
            CONSOLE_ROWS => CONSOLE_ROWS,
            TEXT => text1
        )
        port map (
            clk => clk,
            reset => rst,

            col => col,
            row => row,
            vsync => vsync,

            bounce_x => open,
            bounce_y => open,
            char => char
        );

    foreground_color <= color;
    background_color <= rgb_key_array((py / (HEIGHT / 5)) mod 5);

    rng : OSCG port map (
        OSC => random_bit
    );
end architecture;


    #FPGA #Icepi-Zero #HDL #VHDL
    #fpga #icepizero #hdl #vhdl
  32. Icepi Zero Bot @[email protected] ·

    @[email protected]

    @[email protected] asked

    library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity bouncing_text is generic( CONSOLE_COLUMNS : integer; CONSOLE_ROWS : integer; SPEED : integer := 1; TEXT : string; INIT_X : integer := 0; INIT_Y : integer := 0 ); port ( clk : in std_logic; reset : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; vsync : in std_logic; bounce_x : out std_logic; bounce_y : out std_logic; char : out integer range 0 to 127 := 0 ); end entity bouncing_text; architecture rtl of bouncing_text is signal position_x : integer range -SPEED to CONSOLE_COLUMNS + SPEED := INIT_X; signal position_y : integer range -SPEED to CONSOLE_ROWS + SPEED := INIT_Y; begin char <= character'pos(TEXT(col + 1 - position_x)) when col >= position_x and col < TEXT'length + position_x and row = position_y else 0; process(clk) variable old_vsync : std_logic := '0'; variable speed_x : integer range -SPEED to SPEED := SPEED; variable speed_y : integer range -SPEED to SPEED := SPEED; begin if rising_edge(clk) then bounce_x <= '0'; bounce_y <= '0'; if vsync = '0' and old_vsync = '1' then if position_x + speed_x + TEXT'length >= CONSOLE_COLUMNS then speed_x := -SPEED; position_x <= CONSOLE_COLUMNS - TEXT'length - 1; bounce_x <= '1'; elsif position_x + speed_x < 0 then speed_x := SPEED; position_x <= 0; bounce_x <= '1'; else position_x <= position_x + speed_x; end if; if position_y + speed_y + 1 >= CONSOLE_ROWS then speed_y := -SPEED; position_y <= CONSOLE_ROWS - 1 - 1; bounce_y <= '1'; elsif position_y + speed_y < 0 then speed_y := SPEED; position_y <= 0; bounce_y <= '1'; else position_y <= position_y + speed_y; end if; end if; old_vsync := vsync; end if; end process; end architecture; library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1') ); end my_code; architecture rtl of my_code is signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant text1 : string(1 to 19) := "I am back! Miau~ :3"; constant text2 : string(1 to 19) := "I am back! Miau~ :3"; type rgb_key_array_t is array (0 to 4) of std_logic_vector(23 downto 0); constant rgb_key_array : rgb_key_array_t := (x"5bcffa", x"f5abb9", x"ffffff", x"f5abb9", x"5bcffa"); signal random_bit : std_logic := '0'; signal color : std_logic_vector(23 downto 0) := x"000000"; component OSCG is generic ( DIV : integer := 128 ); port ( OSC : out std_logic ); end component; begin bounce1 : entity work.bouncing_text generic map ( CONSOLE_COLUMNS => CONSOLE_COLUMNS, CONSOLE_ROWS => CONSOLE_ROWS, TEXT => text1 ) port map ( clk => clk, reset => rst, col => col, row => row, vsync => vsync, bounce_x => open, bounce_y => open, char => char ); foreground_color <= color; background_color <= rgb_key_array((py / (HEIGHT / 5)) mod 5); rng : OSCG port map ( OSC => random_bit ); end architecture;

    Success!

    UART Output


    UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB966242884.0%TRELLIS_FF133242880.5%TRELLIS_IO101975.1%
    TimingClockAchievedConstraint$glbnet$clkp56.02 MHz25 MHz$glbnet$clkt365.1 MHz250 MHz
    Code

    library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity bouncing_text is
    generic(
        CONSOLE_COLUMNS : integer;
        CONSOLE_ROWS : integer;
        SPEED : integer := 1;
        TEXT : string;
        INIT_X : integer := 0;
        INIT_Y : integer := 0
    );
    port (
        clk   : in std_logic;
        reset : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;
        vsync : in std_logic;

        bounce_x : out std_logic;
        bounce_y : out std_logic;
        char : out integer range 0 to 127 := 0
    );
end entity bouncing_text;

architecture rtl of bouncing_text is
    signal position_x : integer range -SPEED to CONSOLE_COLUMNS + SPEED := INIT_X;
    signal position_y : integer range -SPEED to CONSOLE_ROWS + SPEED := INIT_Y;
begin
    char <= character'pos(TEXT(col + 1 - position_x))
        when col >= position_x and col < TEXT'length + position_x and row = position_y else 0;

    process(clk)
        variable old_vsync : std_logic := '0';
        variable speed_x : integer range -SPEED to SPEED := SPEED;
        variable speed_y : integer range -SPEED to SPEED := SPEED;
    begin
        if rising_edge(clk) then
            bounce_x <= '0';
            bounce_y <= '0';
            if vsync = '0' and old_vsync = '1' then
                if position_x + speed_x + TEXT'length >= CONSOLE_COLUMNS then
                    speed_x := -SPEED;
                    position_x <= CONSOLE_COLUMNS - TEXT'length - 1;
                    bounce_x <= '1';
                elsif position_x + speed_x < 0 then
                    speed_x := SPEED;
                    position_x <= 0;
                    bounce_x <= '1';
                else
                    position_x <= position_x + speed_x;
                end if;

                if position_y + speed_y + 1 >= CONSOLE_ROWS then
                    speed_y := -SPEED;
                    position_y <= CONSOLE_ROWS - 1 - 1;
                    bounce_y <= '1';
                elsif position_y + speed_y < 0 then
                    speed_y := SPEED;
                    position_y <= 0;
                    bounce_y <= '1';
                else
                    position_y <= position_y + speed_y;
                end if;
            end if;
            old_vsync := vsync;
        end if;
    end process;
end architecture;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1')
    );
end my_code;

architecture rtl of my_code is
    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant text1 : string(1 to 19) := "I am back! Miau~ :3";
    constant text2 : string(1 to 19) := "I am back! Miau~ :3";

    type rgb_key_array_t is array (0 to 4) of std_logic_vector(23 downto 0);
    constant rgb_key_array : rgb_key_array_t := (x"5bcffa", x"f5abb9", x"ffffff", x"f5abb9", x"5bcffa");

    signal random_bit : std_logic := '0';
    signal color : std_logic_vector(23 downto 0) := x"000000";

    component OSCG is
        generic (
            DIV : integer := 128
        );
        port (
            OSC : out std_logic
        );
    end component;
begin
    bounce1 : entity work.bouncing_text
        generic map (
            CONSOLE_COLUMNS => CONSOLE_COLUMNS,
            CONSOLE_ROWS => CONSOLE_ROWS,
            TEXT => text1
        )
        port map (
            clk => clk,
            reset => rst,

            col => col,
            row => row,
            vsync => vsync,

            bounce_x => open,
            bounce_y => open,
            char => char
        );

    foreground_color <= color;
    background_color <= rgb_key_array((py / (HEIGHT / 5)) mod 5);

    rng : OSCG port map (
        OSC => random_bit
    );
end architecture;


    #FPGA #Icepi-Zero #HDL #VHDL
    #fpga #icepizero #hdl #vhdl
  33. Icepi Zero Bot @[email protected] ·

    @[email protected]

    @[email protected] asked

    library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1') ); end my_code; architecture rtl of my_code is signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant example_text : string(1 to 19) := "I am back! Miau~ :3"; type rgb_key_array_t is array (0 to 4) of std_logic_vector(23 downto 0); constant rgb_key_array : rgb_key_array_t := (x"5bcffa", x"f5abb9", x"ffffff", x"f5abb9", x"5bcffa"); constant SPEED : integer := 1; signal position_x : integer range -SPEED to CONSOLE_COLUMNS + SPEED := 0; signal position_y : integer range -SPEED to CONSOLE_ROWS + SPEED := 0; signal random_bit : std_logic := '0'; signal color : std_logic_vector(23 downto 0) := x"000000"; component OSCG is generic ( DIV : integer := 128 ); port ( OSC : out std_logic ); end component; begin char <= character'pos(example_text(col + 1 - position_x)) when col >= position_x and col < example_text'length + position_x and row = position_y else 0; foreground_color <= color; background_color <= rgb_key_array((py / (HEIGHT / 5)) mod 5); rng : OSCG port map ( OSC => random_bit ); process(clk) variable old_vsync : std_logic := '0'; variable speed_x : integer range -SPEED to SPEED := SPEED; variable speed_y : integer range -SPEED to SPEED := SPEED; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then if position_x + speed_x + example_text'length >= CONSOLE_COLUMNS then speed_x := -SPEED; position_x <= CONSOLE_COLUMNS - example_text'length - 1; color <= color(22 downto 0) & random_bit; elsif position_x + speed_x < 0 then speed_x := SPEED; position_x <= 0; color <= color(22 downto 0) & random_bit; else position_x <= position_x + speed_x; end if; if position_y + speed_y + 1 >= CONSOLE_ROWS then speed_y := -SPEED; position_y <= CONSOLE_ROWS - 1 - 1; color <= color(22 downto 0) & random_bit; elsif position_y + speed_y < 0 then speed_y := SPEED; position_y <= 0; color <= color(22 downto 0) & random_bit; else position_y <= position_y + speed_y; end if; end if; old_vsync := vsync; end if; end process; end architecture;

    Success!

    UART Output


    UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%OSCG11100.0%TRELLIS_COMB1305242885.4%TRELLIS_FF177242880.7%TRELLIS_IO101975.1%
    TimingClockAchievedConstraint$glbnet$clkp40.2 MHz25 MHz$glbnet$clkt350.02 MHz250 MHz
    Code

    library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1')
    );
end my_code;

architecture rtl of my_code is
    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant example_text : string(1 to 19) := "I am back! Miau~ :3";

    type rgb_key_array_t is array (0 to 4) of std_logic_vector(23 downto 0);
    constant rgb_key_array : rgb_key_array_t := (x"5bcffa", x"f5abb9", x"ffffff", x"f5abb9", x"5bcffa");

    constant SPEED : integer := 1;

    signal position_x : integer range -SPEED to CONSOLE_COLUMNS + SPEED := 0;
    signal position_y : integer range -SPEED to CONSOLE_ROWS + SPEED := 0;

    signal random_bit : std_logic := '0';
    signal color : std_logic_vector(23 downto 0) := x"000000";

    component OSCG is
        generic (
            DIV : integer := 128
        );
        port (
            OSC : out std_logic
        );
    end component;
begin
    char <= character'pos(example_text(col + 1 - position_x))
        when col >= position_x and col < example_text'length + position_x and row = position_y else 0;

    foreground_color <= color;
    background_color <= rgb_key_array((py / (HEIGHT / 5)) mod 5);

    rng : OSCG port map (
        OSC => random_bit
    );

    process(clk)
        variable old_vsync : std_logic := '0';
        variable speed_x : integer range -SPEED to SPEED := SPEED;
        variable speed_y : integer range -SPEED to SPEED := SPEED;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                if position_x + speed_x + example_text'length >= CONSOLE_COLUMNS then
                    speed_x := -SPEED;
                    position_x <= CONSOLE_COLUMNS - example_text'length - 1;

                    color <= color(22 downto 0) & random_bit;
                elsif position_x + speed_x < 0 then
                    speed_x := SPEED;
                    position_x <= 0;

                    color <= color(22 downto 0) & random_bit;
                else
                    position_x <= position_x + speed_x;
                end if;

                if position_y + speed_y + 1 >= CONSOLE_ROWS then
                    speed_y := -SPEED;
                    position_y <= CONSOLE_ROWS - 1 - 1;

                    color <= color(22 downto 0) & random_bit;
                elsif position_y + speed_y < 0 then
                    speed_y := SPEED;
                    position_y <= 0;

                    color <= color(22 downto 0) & random_bit;
                else
                    position_y <= position_y + speed_y;
                end if;
            end if;
            old_vsync := vsync;
        end if;
    end process;
end architecture;


    #FPGA #Icepi-Zero #HDL #VHDL
    #fpga #icepizero #hdl #vhdl
  34. Icepi Zero Bot @[email protected] ·

    @[email protected]

    @[email protected] asked

    library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1') ); end my_code; architecture rtl of my_code is signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant example_text : string(1 to 19) := "I am back! Miau~ :3"; type rgb_key_array_t is array (0 to 4) of std_logic_vector(23 downto 0); constant rgb_key_array : rgb_key_array_t := (x"5bcffa", x"f5abb9", x"ffffff", x"f5abb9", x"5bcffa"); constant SPEED : integer := 1; signal position_x : integer range -SPEED to CONSOLE_COLUMNS + SPEED := 0; signal position_y : integer range -SPEED to CONSOLE_ROWS + SPEED := 0; signal random_bit : std_logic := '0'; signal color : std_logic_vector(23 downto 0) := x"000000"; component OSCG is generic ( DIV : integer := 128 ); port ( OSC : out std_logic ); end component; begin char <= character'pos(example_text(col + 1 - position_x)) when col >= position_x and col < example_text'length + position_x and row = position_y else 0; foreground_color <= color; background_color <= rgb_key_array((py / (HEIGHT / 5)) mod 5); rng : OSCG port map ( OSC => random_bit ); process(clk) variable old_vsync : std_logic := '0'; variable speed_x : integer range -SPEED to SPEED := SPEED; variable speed_y : integer range -SPEED to SPEED := SPEED; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then if position_x + speed_x + example_text'length >= CONSOLE_COLUMNS then speed_x := -SPEED; position_x <= CONSOLE_COLUMNS - example_text'length - 1; color <= color(22 downto 0) & random_bit; elsif position_x + speed_x < 0 then speed_x := SPEED; position_x <= 0; color <= color(22 downto 0) & random_bit; else position_x <= position_x + speed_x; end if; if position_y + speed_y + 1 >= CONSOLE_ROWS then speed_y := -SPEED; position_y <= CONSOLE_ROWS - 1 - 1; color <= color(22 downto 0) & random_bit; elsif position_y + speed_y < 0 then speed_y := SPEED; position_y <= 0; color <= color(22 downto 0) & random_bit; else position_y <= position_y + speed_y; end if; end if; old_vsync := vsync; end if; end process; end architecture;

    Success!

    UART Output


    UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%OSCG11100.0%TRELLIS_COMB1305242885.4%TRELLIS_FF177242880.7%TRELLIS_IO101975.1%
    TimingClockAchievedConstraint$glbnet$clkp40.2 MHz25 MHz$glbnet$clkt350.02 MHz250 MHz
    Code

    library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1')
    );
end my_code;

architecture rtl of my_code is
    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant example_text : string(1 to 19) := "I am back! Miau~ :3";

    type rgb_key_array_t is array (0 to 4) of std_logic_vector(23 downto 0);
    constant rgb_key_array : rgb_key_array_t := (x"5bcffa", x"f5abb9", x"ffffff", x"f5abb9", x"5bcffa");

    constant SPEED : integer := 1;

    signal position_x : integer range -SPEED to CONSOLE_COLUMNS + SPEED := 0;
    signal position_y : integer range -SPEED to CONSOLE_ROWS + SPEED := 0;

    signal random_bit : std_logic := '0';
    signal color : std_logic_vector(23 downto 0) := x"000000";

    component OSCG is
        generic (
            DIV : integer := 128
        );
        port (
            OSC : out std_logic
        );
    end component;
begin
    char <= character'pos(example_text(col + 1 - position_x))
        when col >= position_x and col < example_text'length + position_x and row = position_y else 0;

    foreground_color <= color;
    background_color <= rgb_key_array((py / (HEIGHT / 5)) mod 5);

    rng : OSCG port map (
        OSC => random_bit
    );

    process(clk)
        variable old_vsync : std_logic := '0';
        variable speed_x : integer range -SPEED to SPEED := SPEED;
        variable speed_y : integer range -SPEED to SPEED := SPEED;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                if position_x + speed_x + example_text'length >= CONSOLE_COLUMNS then
                    speed_x := -SPEED;
                    position_x <= CONSOLE_COLUMNS - example_text'length - 1;

                    color <= color(22 downto 0) & random_bit;
                elsif position_x + speed_x < 0 then
                    speed_x := SPEED;
                    position_x <= 0;

                    color <= color(22 downto 0) & random_bit;
                else
                    position_x <= position_x + speed_x;
                end if;

                if position_y + speed_y + 1 >= CONSOLE_ROWS then
                    speed_y := -SPEED;
                    position_y <= CONSOLE_ROWS - 1 - 1;

                    color <= color(22 downto 0) & random_bit;
                elsif position_y + speed_y < 0 then
                    speed_y := SPEED;
                    position_y <= 0;

                    color <= color(22 downto 0) & random_bit;
                else
                    position_y <= position_y + speed_y;
                end if;
            end if;
            old_vsync := vsync;
        end if;
    end process;
end architecture;


    #FPGA #Icepi-Zero #HDL #VHDL
    #fpga #icepizero #hdl #vhdl
  35. Icepi Zero Bot @[email protected] ·

    @[email protected]

    @[email protected] asked

    library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1') ); end my_code; architecture rtl of my_code is signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant example_text : string(1 to 13) := "I am back~ ;3"; type rgb_key_array_t is array (0 to 4) of std_logic_vector(23 downto 0); constant rgb_key_array : rgb_key_array_t := (x"5bcffa", x"f5abb9", x"ffffff", x"f5abb9", x"5bcffa"); constant SPEED : integer := 1; signal position_x : integer range -SPEED to CONSOLE_COLUMNS + SPEED := 0; signal position_y : integer range -SPEED to CONSOLE_ROWS + SPEED := 0; signal random_bit : std_logic := '0'; signal color : std_logic_vector(23 downto 0) := x"000000"; component OSCG is generic ( DIV : integer := 128 ); port ( OSC : out std_logic ); end component; begin char <= character'pos(example_text(col + 1 - position_x)) when col >= position_x and col < example_text'length + position_x and row = position_y else 0; foreground_color <= color; background_color <= rgb_key_array((py / (HEIGHT / 5)) mod 5); rng : OSCG port map ( OSC => random_bit ); process(clk) variable old_vsync : std_logic := '0'; variable speed_x : integer range -SPEED to SPEED := SPEED; variable speed_y : integer range -SPEED to SPEED := SPEED; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then if position_x + speed_x + example_text'length >= CONSOLE_COLUMNS then speed_x := -SPEED; position_x <= CONSOLE_COLUMNS - example_text'length - 1; color <= color(22 downto 0) & random_bit; elsif position_x + speed_x < 0 then speed_x := SPEED; position_x <= 0; color <= color(22 downto 0) & random_bit; else position_x <= position_x + speed_x; end if; if position_y + speed_y + 1 >= CONSOLE_ROWS then speed_y := -SPEED; position_y <= CONSOLE_ROWS - 1 - 1; color <= color(22 downto 0) & random_bit; elsif position_y + speed_y < 0 then speed_y := SPEED; position_y <= 0; color <= color(22 downto 0) & random_bit; else position_y <= position_y + speed_y; end if; end if; old_vsync := vsync; end if; end process; end architecture;

    Success!

    UART Output


    UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%OSCG11100.0%TRELLIS_COMB1231242885.1%TRELLIS_FF177242880.7%TRELLIS_IO101975.1%
    TimingClockAchievedConstraint$glbnet$clkp41.34 MHz25 MHz$glbnet$clkt356.38 MHz250 MHz
    Code

    library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1')
    );
end my_code;

architecture rtl of my_code is
    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant example_text : string(1 to 13) := "I am back~ ;3";

    type rgb_key_array_t is array (0 to 4) of std_logic_vector(23 downto 0);
    constant rgb_key_array : rgb_key_array_t := (x"5bcffa", x"f5abb9", x"ffffff", x"f5abb9", x"5bcffa");

    constant SPEED : integer := 1;

    signal position_x : integer range -SPEED to CONSOLE_COLUMNS + SPEED := 0;
    signal position_y : integer range -SPEED to CONSOLE_ROWS + SPEED := 0;

    signal random_bit : std_logic := '0';
    signal color : std_logic_vector(23 downto 0) := x"000000";

    component OSCG is
        generic (
            DIV : integer := 128
        );
        port (
            OSC : out std_logic
        );
    end component;
begin
    char <= character'pos(example_text(col + 1 - position_x))
        when col >= position_x and col < example_text'length + position_x and row = position_y else 0;

    foreground_color <= color;
    background_color <= rgb_key_array((py / (HEIGHT / 5)) mod 5);

    rng : OSCG port map (
        OSC => random_bit
    );

    process(clk)
        variable old_vsync : std_logic := '0';
        variable speed_x : integer range -SPEED to SPEED := SPEED;
        variable speed_y : integer range -SPEED to SPEED := SPEED;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                if position_x + speed_x + example_text'length >= CONSOLE_COLUMNS then
                    speed_x := -SPEED;
                    position_x <= CONSOLE_COLUMNS - example_text'length - 1;

                    color <= color(22 downto 0) & random_bit;
                elsif position_x + speed_x < 0 then
                    speed_x := SPEED;
                    position_x <= 0;

                    color <= color(22 downto 0) & random_bit;
                else
                    position_x <= position_x + speed_x;
                end if;

                if position_y + speed_y + 1 >= CONSOLE_ROWS then
                    speed_y := -SPEED;
                    position_y <= CONSOLE_ROWS - 1 - 1;

                    color <= color(22 downto 0) & random_bit;
                elsif position_y + speed_y < 0 then
                    speed_y := SPEED;
                    position_y <= 0;

                    color <= color(22 downto 0) & random_bit;
                else
                    position_y <= position_y + speed_y;
                end if;
            end if;
            old_vsync := vsync;
        end if;
    end process;
end architecture;


    #FPGA #Icepi-Zero #HDL #VHDL
    #fpga #icepizero #hdl #vhdl
  36. Icepi Zero Bot @[email protected] ·

    @[email protected]

    @[email protected] asked

    library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1') ); end my_code; architecture rtl of my_code is signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant example_text : string(1 to 13) := "I am back~ ;3"; type rgb_key_array_t is array (0 to 4) of std_logic_vector(23 downto 0); constant rgb_key_array : rgb_key_array_t := (x"5bcffa", x"f5abb9", x"ffffff", x"f5abb9", x"5bcffa"); constant SPEED : integer := 1; signal position_x : integer range -SPEED to CONSOLE_COLUMNS + SPEED := 0; signal position_y : integer range -SPEED to CONSOLE_ROWS + SPEED := 0; signal random_bit : std_logic := '0'; signal color : std_logic_vector(23 downto 0) := x"000000"; component OSCG is generic ( DIV : integer := 128 ); port ( OSC : out std_logic ); end component; begin char <= character'pos(example_text(col + 1 - position_x)) when col >= position_x and col < example_text'length + position_x and row = position_y else 0; foreground_color <= color; background_color <= rgb_key_array((py / (HEIGHT / 5)) mod 5); rng : OSCG port map ( OSC => random_bit ); process(clk) variable old_vsync : std_logic := '0'; variable speed_x : integer range -SPEED to SPEED := SPEED; variable speed_y : integer range -SPEED to SPEED := SPEED; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then if position_x + speed_x + example_text'length >= CONSOLE_COLUMNS then speed_x := -SPEED; position_x <= CONSOLE_COLUMNS - example_text'length - 1; color <= color(22 downto 0) & random_bit; elsif position_x + speed_x < 0 then speed_x := SPEED; position_x <= 0; color <= color(22 downto 0) & random_bit; else position_x <= position_x + speed_x; end if; if position_y + speed_y + 1 >= CONSOLE_ROWS then speed_y := -SPEED; position_y <= CONSOLE_ROWS - 1 - 1; color <= color(22 downto 0) & random_bit; elsif position_y + speed_y < 0 then speed_y := SPEED; position_y <= 0; color <= color(22 downto 0) & random_bit; else position_y <= position_y + speed_y; end if; end if; old_vsync := vsync; end if; end process; end architecture;

    Success!

    UART Output


    UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%OSCG11100.0%TRELLIS_COMB1231242885.1%TRELLIS_FF177242880.7%TRELLIS_IO101975.1%
    TimingClockAchievedConstraint$glbnet$clkp41.34 MHz25 MHz$glbnet$clkt356.38 MHz250 MHz
    Code

    library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1')
    );
end my_code;

architecture rtl of my_code is
    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant example_text : string(1 to 13) := "I am back~ ;3";

    type rgb_key_array_t is array (0 to 4) of std_logic_vector(23 downto 0);
    constant rgb_key_array : rgb_key_array_t := (x"5bcffa", x"f5abb9", x"ffffff", x"f5abb9", x"5bcffa");

    constant SPEED : integer := 1;

    signal position_x : integer range -SPEED to CONSOLE_COLUMNS + SPEED := 0;
    signal position_y : integer range -SPEED to CONSOLE_ROWS + SPEED := 0;

    signal random_bit : std_logic := '0';
    signal color : std_logic_vector(23 downto 0) := x"000000";

    component OSCG is
        generic (
            DIV : integer := 128
        );
        port (
            OSC : out std_logic
        );
    end component;
begin
    char <= character'pos(example_text(col + 1 - position_x))
        when col >= position_x and col < example_text'length + position_x and row = position_y else 0;

    foreground_color <= color;
    background_color <= rgb_key_array((py / (HEIGHT / 5)) mod 5);

    rng : OSCG port map (
        OSC => random_bit
    );

    process(clk)
        variable old_vsync : std_logic := '0';
        variable speed_x : integer range -SPEED to SPEED := SPEED;
        variable speed_y : integer range -SPEED to SPEED := SPEED;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                if position_x + speed_x + example_text'length >= CONSOLE_COLUMNS then
                    speed_x := -SPEED;
                    position_x <= CONSOLE_COLUMNS - example_text'length - 1;

                    color <= color(22 downto 0) & random_bit;
                elsif position_x + speed_x < 0 then
                    speed_x := SPEED;
                    position_x <= 0;

                    color <= color(22 downto 0) & random_bit;
                else
                    position_x <= position_x + speed_x;
                end if;

                if position_y + speed_y + 1 >= CONSOLE_ROWS then
                    speed_y := -SPEED;
                    position_y <= CONSOLE_ROWS - 1 - 1;

                    color <= color(22 downto 0) & random_bit;
                elsif position_y + speed_y < 0 then
                    speed_y := SPEED;
                    position_y <= 0;

                    color <= color(22 downto 0) & random_bit;
                else
                    position_y <= position_y + speed_y;
                end if;
            end if;
            old_vsync := vsync;
        end if;
    end process;
end architecture;


    #FPGA #Icepi-Zero #HDL #VHDL
    #fpga #icepizero #hdl #vhdl
  37. Icepi Zero Bot @[email protected] ·

    @[email protected]

    @[email protected] asked

    library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1') ); end my_code; architecture rtl of my_code is signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant example_text : string(1 to 13) := "I am back~ ;3"; type rgb_key_array_t is array (0 to 4) of std_logic_vector(23 downto 0); constant rgb_key_array : rgb_key_array_t := (x"5bcffa", x"f5abb9", x"ffffff", x"f5abb9", x"5bcffa"); constant SPEED : integer := 1; signal position_x : integer range -SPEED to CONSOLE_COLUMNS + SPEED := 0; signal position_y : integer range -SPEED to CONSOLE_ROWS + SPEED := 0; signal random_bit : std_logic := '0'; signal color : std_logic_vector(23 downto 0) := x"000000"; component OSCG is generic ( DIV : integer := 128 ); port ( OSC : out std_logic ); end component; begin char <= character'pos(example_text(col + 1 - position_x)) when col >= position_x and col < example_text'length + position_x and row = position_y else 0; foreground_color <= color; background_color <= rgb_key_array((py / (HEIGHT / 5)) mod 5); process(clk) variable old_vsync : std_logic := '0'; variable speed_x : integer range -SPEED to SPEED := SPEED; variable speed_y : integer range -SPEED to SPEED := SPEED; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then if position_x + speed_x + example_text'length >= CONSOLE_COLUMNS then speed_x := -SPEED; position_x <= CONSOLE_COLUMNS - example_text'length - 1; color <= color(22 downto 0) & random_bit; elsif position_x + speed_x < 0 then speed_x := SPEED; position_x <= 0; color <= color(22 downto 0) & random_bit; else position_x <= position_x + speed_x; end if; if position_y + speed_y + 1 >= CONSOLE_ROWS then speed_y := -SPEED; position_y <= CONSOLE_ROWS - 1 - 1; color <= color(22 downto 0) & random_bit; elsif position_y + speed_y < 0 then speed_y := SPEED; position_y <= 0; color <= color(22 downto 0) & random_bit; else position_y <= position_y + speed_y; end if; end if; old_vsync := vsync; end if; end process; end architecture;

    Success!

    UART Output


    UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB899242883.7%TRELLIS_FF133242880.5%TRELLIS_IO101975.1%
    TimingClockAchievedConstraint$glbnet$clkp58.52 MHz25 MHz$glbnet$clkt363.5 MHz250 MHz
    Code

    library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1')
    );
end my_code;

architecture rtl of my_code is
    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant example_text : string(1 to 13) := "I am back~ ;3";

    type rgb_key_array_t is array (0 to 4) of std_logic_vector(23 downto 0);
    constant rgb_key_array : rgb_key_array_t := (x"5bcffa", x"f5abb9", x"ffffff", x"f5abb9", x"5bcffa");

    constant SPEED : integer := 1;

    signal position_x : integer range -SPEED to CONSOLE_COLUMNS + SPEED := 0;
    signal position_y : integer range -SPEED to CONSOLE_ROWS + SPEED := 0;

    signal random_bit : std_logic := '0';
    signal color : std_logic_vector(23 downto 0) := x"000000";

    component OSCG is
        generic (
            DIV : integer := 128
        );
        port (
            OSC : out std_logic
        );
    end component;
begin
    char <= character'pos(example_text(col + 1 - position_x))
        when col >= position_x and col < example_text'length + position_x and row = position_y else 0;

    foreground_color <= color;
    background_color <= rgb_key_array((py / (HEIGHT / 5)) mod 5);

    process(clk)
        variable old_vsync : std_logic := '0';
        variable speed_x : integer range -SPEED to SPEED := SPEED;
        variable speed_y : integer range -SPEED to SPEED := SPEED;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                if position_x + speed_x + example_text'length >= CONSOLE_COLUMNS then
                    speed_x := -SPEED;
                    position_x <= CONSOLE_COLUMNS - example_text'length - 1;

                    color <= color(22 downto 0) & random_bit;
                elsif position_x + speed_x < 0 then
                    speed_x := SPEED;
                    position_x <= 0;

                    color <= color(22 downto 0) & random_bit;
                else
                    position_x <= position_x + speed_x;
                end if;

                if position_y + speed_y + 1 >= CONSOLE_ROWS then
                    speed_y := -SPEED;
                    position_y <= CONSOLE_ROWS - 1 - 1;

                    color <= color(22 downto 0) & random_bit;
                elsif position_y + speed_y < 0 then
                    speed_y := SPEED;
                    position_y <= 0;

                    color <= color(22 downto 0) & random_bit;
                else
                    position_y <= position_y + speed_y;
                end if;
            end if;
            old_vsync := vsync;
        end if;
    end process;
end architecture;


    #FPGA #Icepi-Zero #HDL #VHDL
    #fpga #icepizero #hdl #vhdl
  38. Icepi Zero Bot @[email protected] ·

    @[email protected]

    @[email protected] asked

    library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1') ); end my_code; architecture rtl of my_code is signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant example_text : string(1 to 13) := "I am back~ ;3"; type rgb_key_array_t is array (0 to 4) of std_logic_vector(23 downto 0); constant rgb_key_array : rgb_key_array_t := (x"5bcffa", x"f5abb9", x"ffffff", x"f5abb9", x"5bcffa"); constant SPEED : integer := 1; signal position_x : integer range -SPEED to CONSOLE_COLUMNS + SPEED := 0; signal position_y : integer range -SPEED to CONSOLE_ROWS + SPEED := 0; signal random_bit : std_logic := '0'; signal color : std_logic_vector(23 downto 0) := x"000000"; component OSCG is generic ( DIV : integer := 128 ); port ( OSC : out std_logic ); end component; begin char <= character'pos(example_text(col + 1 - position_x)) when col >= position_x and col < example_text'length + position_x and row = position_y else 0; foreground_color <= color; background_color <= rgb_key_array((py / (HEIGHT / 5)) mod 5); process(clk) variable old_vsync : std_logic := '0'; variable speed_x : integer range -SPEED to SPEED := SPEED; variable speed_y : integer range -SPEED to SPEED := SPEED; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then if position_x + speed_x + example_text'length >= CONSOLE_COLUMNS then speed_x := -SPEED; position_x <= CONSOLE_COLUMNS - example_text'length - 1; color <= color(22 downto 0) & random_bit; elsif position_x + speed_x < 0 then speed_x := SPEED; position_x <= 0; color <= color(22 downto 0) & random_bit; else position_x <= position_x + speed_x; end if; if position_y + speed_y + 1 >= CONSOLE_ROWS then speed_y := -SPEED; position_y <= CONSOLE_ROWS - 1 - 1; color <= color(22 downto 0) & random_bit; elsif position_y + speed_y < 0 then speed_y := SPEED; position_y <= 0; color <= color(22 downto 0) & random_bit; else position_y <= position_y + speed_y; end if; end if; old_vsync := vsync; end if; end process; end architecture;

    Success!

    UART Output


    UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB899242883.7%TRELLIS_FF133242880.5%TRELLIS_IO101975.1%
    TimingClockAchievedConstraint$glbnet$clkp58.52 MHz25 MHz$glbnet$clkt363.5 MHz250 MHz
    Code

    library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1')
    );
end my_code;

architecture rtl of my_code is
    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant example_text : string(1 to 13) := "I am back~ ;3";

    type rgb_key_array_t is array (0 to 4) of std_logic_vector(23 downto 0);
    constant rgb_key_array : rgb_key_array_t := (x"5bcffa", x"f5abb9", x"ffffff", x"f5abb9", x"5bcffa");

    constant SPEED : integer := 1;

    signal position_x : integer range -SPEED to CONSOLE_COLUMNS + SPEED := 0;
    signal position_y : integer range -SPEED to CONSOLE_ROWS + SPEED := 0;

    signal random_bit : std_logic := '0';
    signal color : std_logic_vector(23 downto 0) := x"000000";

    component OSCG is
        generic (
            DIV : integer := 128
        );
        port (
            OSC : out std_logic
        );
    end component;
begin
    char <= character'pos(example_text(col + 1 - position_x))
        when col >= position_x and col < example_text'length + position_x and row = position_y else 0;

    foreground_color <= color;
    background_color <= rgb_key_array((py / (HEIGHT / 5)) mod 5);

    process(clk)
        variable old_vsync : std_logic := '0';
        variable speed_x : integer range -SPEED to SPEED := SPEED;
        variable speed_y : integer range -SPEED to SPEED := SPEED;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                if position_x + speed_x + example_text'length >= CONSOLE_COLUMNS then
                    speed_x := -SPEED;
                    position_x <= CONSOLE_COLUMNS - example_text'length - 1;

                    color <= color(22 downto 0) & random_bit;
                elsif position_x + speed_x < 0 then
                    speed_x := SPEED;
                    position_x <= 0;

                    color <= color(22 downto 0) & random_bit;
                else
                    position_x <= position_x + speed_x;
                end if;

                if position_y + speed_y + 1 >= CONSOLE_ROWS then
                    speed_y := -SPEED;
                    position_y <= CONSOLE_ROWS - 1 - 1;

                    color <= color(22 downto 0) & random_bit;
                elsif position_y + speed_y < 0 then
                    speed_y := SPEED;
                    position_y <= 0;

                    color <= color(22 downto 0) & random_bit;
                else
                    position_y <= position_y + speed_y;
                end if;
            end if;
            old_vsync := vsync;
        end if;
    end process;
end architecture;


    #FPGA #Icepi-Zero #HDL #VHDL
    #fpga #icepizero #hdl #vhdl
  39. Icepi Zero Bot @[email protected] ·

    @[email protected]

    @[email protected] asked

    library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1') ); end my_code; architecture rtl of my_code is signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant example_text : string(1 to 13) := "I am back~ ;3"; type rgb_key_array_t is array (0 to 4) of std_logic_vector(23 downto 0); constant rgb_key_array : rgb_key_array_t := (x"5bcffa", x"f5abb9", x"ffffff", x"f5abb9", x"5bcffa"); constant SPEED : integer := 1; signal position_x : integer range -SPEED to CONSOLE_COLUMNS + SPEED := 0; signal position_y : integer range -SPEED to CONSOLE_ROWS + SPEED := 0; signal random_bit : std_logic := '0'; signal color : std_logic_vector(23 downto 0) := x"FFFFFF"; component OSCG is generic ( DIV : integer := 128 ); port ( OSC : out std_logic ); end component; begin char <= character'pos(example_text(col + 1 - position_x)) when col >= position_x and col < example_text'length + position_x and row = position_y else 0; foreground_color <= (others => '0'); background_color <= rgb_key_array((py / (HEIGHT / 5)) mod 5); process(clk) variable old_vsync : std_logic := '0'; variable speed_x : integer range -SPEED to SPEED := SPEED; variable speed_y : integer range -SPEED to SPEED := SPEED; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then if position_x + speed_x + example_text'length >= CONSOLE_COLUMNS then speed_x := -SPEED; position_x <= CONSOLE_COLUMNS - example_text'length - 1; color <= color(22 downto 0) & random_bit; elsif position_x + speed_x < 0 then speed_x := SPEED; position_x <= 0; color <= color(22 downto 0) & random_bit; else position_x <= position_x + speed_x; end if; if position_y + speed_y + 1 >= CONSOLE_ROWS then speed_y := -SPEED; position_y <= CONSOLE_ROWS - 1 - 1; color <= color(22 downto 0) & random_bit; elsif position_y + speed_y < 0 then speed_y := SPEED; position_y <= 0; color <= color(22 downto 0) & random_bit; else position_y <= position_y + speed_y; end if; end if; old_vsync := vsync; end if; end process; end architecture;

    Success!

    UART Output


    UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB906242883.7%TRELLIS_FF133242880.5%TRELLIS_IO101975.1%
    TimingClockAchievedConstraint$glbnet$clkp57.59 MHz25 MHz$glbnet$clkt321.03 MHz250 MHz
    Code

    library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1')
    );
end my_code;

architecture rtl of my_code is
    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant example_text : string(1 to 13) := "I am back~ ;3";

    type rgb_key_array_t is array (0 to 4) of std_logic_vector(23 downto 0);
    constant rgb_key_array : rgb_key_array_t := (x"5bcffa", x"f5abb9", x"ffffff", x"f5abb9", x"5bcffa");

    constant SPEED : integer := 1;

    signal position_x : integer range -SPEED to CONSOLE_COLUMNS + SPEED := 0;
    signal position_y : integer range -SPEED to CONSOLE_ROWS + SPEED := 0;

    signal random_bit : std_logic := '0';
    signal color : std_logic_vector(23 downto 0) := x"FFFFFF";

    component OSCG is
        generic (
            DIV : integer := 128
        );
        port (
            OSC : out std_logic
        );
    end component;
begin
    char <= character'pos(example_text(col + 1 - position_x))
        when col >= position_x and col < example_text'length + position_x and row = position_y else 0;

    foreground_color <= (others => '0');
    background_color <= rgb_key_array((py / (HEIGHT / 5)) mod 5);

    process(clk)
        variable old_vsync : std_logic := '0';
        variable speed_x : integer range -SPEED to SPEED := SPEED;
        variable speed_y : integer range -SPEED to SPEED := SPEED;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                if position_x + speed_x + example_text'length >= CONSOLE_COLUMNS then
                    speed_x := -SPEED;
                    position_x <= CONSOLE_COLUMNS - example_text'length - 1;

                    color <= color(22 downto 0) & random_bit;
                elsif position_x + speed_x < 0 then
                    speed_x := SPEED;
                    position_x <= 0;

                    color <= color(22 downto 0) & random_bit;
                else
                    position_x <= position_x + speed_x;
                end if;

                if position_y + speed_y + 1 >= CONSOLE_ROWS then
                    speed_y := -SPEED;
                    position_y <= CONSOLE_ROWS - 1 - 1;

                    color <= color(22 downto 0) & random_bit;
                elsif position_y + speed_y < 0 then
                    speed_y := SPEED;
                    position_y <= 0;

                    color <= color(22 downto 0) & random_bit;
                else
                    position_y <= position_y + speed_y;
                end if;
            end if;
            old_vsync := vsync;
        end if;
    end process;
end architecture;


    #FPGA #Icepi-Zero #HDL #VHDL
    #fpga #icepizero #hdl #vhdl
  40. Icepi Zero Bot @[email protected] ·

    @[email protected]

    @[email protected] asked

    library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1') ); end my_code; architecture rtl of my_code is signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant example_text : string(1 to 13) := "I am back~ ;3"; type rgb_key_array_t is array (0 to 4) of std_logic_vector(23 downto 0); constant rgb_key_array : rgb_key_array_t := (x"5bcffa", x"f5abb9", x"ffffff", x"f5abb9", x"5bcffa"); constant SPEED : integer := 1; signal position_x : integer range -SPEED to CONSOLE_COLUMNS + SPEED := 0; signal position_y : integer range -SPEED to CONSOLE_ROWS + SPEED := 0; signal random_bit : std_logic := '0'; signal color : std_logic_vector(23 downto 0) := x"FFFFFF"; component OSCG is generic ( DIV : integer := 128 ); port ( OSC : out std_logic ); end component; begin char <= character'pos(example_text(col + 1 - position_x)) when col >= position_x and col < example_text'length + position_x and row = position_y else 0; foreground_color <= (others => '0'); background_color <= rgb_key_array((py / (HEIGHT / 5)) mod 5); process(clk) variable old_vsync : std_logic := '0'; variable speed_x : integer range -SPEED to SPEED := SPEED; variable speed_y : integer range -SPEED to SPEED := SPEED; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then if position_x + speed_x + example_text'length >= CONSOLE_COLUMNS then speed_x := -SPEED; position_x <= CONSOLE_COLUMNS - example_text'length - 1; color <= color(22 downto 0) & random_bit; elsif position_x + speed_x < 0 then speed_x := SPEED; position_x <= 0; color <= color(22 downto 0) & random_bit; else position_x <= position_x + speed_x; end if; if position_y + speed_y + 1 >= CONSOLE_ROWS then speed_y := -SPEED; position_y <= CONSOLE_ROWS - 1 - 1; color <= color(22 downto 0) & random_bit; elsif position_y + speed_y < 0 then speed_y := SPEED; position_y <= 0; color <= color(22 downto 0) & random_bit; else position_y <= position_y + speed_y; end if; end if; old_vsync := vsync; end if; end process; end architecture;

    Success!

    UART Output


    UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB906242883.7%TRELLIS_FF133242880.5%TRELLIS_IO101975.1%
    TimingClockAchievedConstraint$glbnet$clkp57.59 MHz25 MHz$glbnet$clkt321.03 MHz250 MHz
    Code

    library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1')
    );
end my_code;

architecture rtl of my_code is
    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant example_text : string(1 to 13) := "I am back~ ;3";

    type rgb_key_array_t is array (0 to 4) of std_logic_vector(23 downto 0);
    constant rgb_key_array : rgb_key_array_t := (x"5bcffa", x"f5abb9", x"ffffff", x"f5abb9", x"5bcffa");

    constant SPEED : integer := 1;

    signal position_x : integer range -SPEED to CONSOLE_COLUMNS + SPEED := 0;
    signal position_y : integer range -SPEED to CONSOLE_ROWS + SPEED := 0;

    signal random_bit : std_logic := '0';
    signal color : std_logic_vector(23 downto 0) := x"FFFFFF";

    component OSCG is
        generic (
            DIV : integer := 128
        );
        port (
            OSC : out std_logic
        );
    end component;
begin
    char <= character'pos(example_text(col + 1 - position_x))
        when col >= position_x and col < example_text'length + position_x and row = position_y else 0;

    foreground_color <= (others => '0');
    background_color <= rgb_key_array((py / (HEIGHT / 5)) mod 5);

    process(clk)
        variable old_vsync : std_logic := '0';
        variable speed_x : integer range -SPEED to SPEED := SPEED;
        variable speed_y : integer range -SPEED to SPEED := SPEED;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                if position_x + speed_x + example_text'length >= CONSOLE_COLUMNS then
                    speed_x := -SPEED;
                    position_x <= CONSOLE_COLUMNS - example_text'length - 1;

                    color <= color(22 downto 0) & random_bit;
                elsif position_x + speed_x < 0 then
                    speed_x := SPEED;
                    position_x <= 0;

                    color <= color(22 downto 0) & random_bit;
                else
                    position_x <= position_x + speed_x;
                end if;

                if position_y + speed_y + 1 >= CONSOLE_ROWS then
                    speed_y := -SPEED;
                    position_y <= CONSOLE_ROWS - 1 - 1;

                    color <= color(22 downto 0) & random_bit;
                elsif position_y + speed_y < 0 then
                    speed_y := SPEED;
                    position_y <= 0;

                    color <= color(22 downto 0) & random_bit;
                else
                    position_y <= position_y + speed_y;
                end if;
            end if;
            old_vsync := vsync;
        end if;
    end process;
end architecture;


    #FPGA #Icepi-Zero #HDL #VHDL
    #fpga #icepizero #hdl #vhdl
  41. Icepi Zero Bot @[email protected] ·

    @[email protected]

    @[email protected] asked

    library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1') ); end my_code; architecture rtl of my_code is alias red : std_logic_vector(7 downto 0) is background_color(23 downto 16); alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8); alias blue : std_logic_vector(7 downto 0) is background_color(7 downto 0); signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant example_text : string(1 to 19) := "Hello Fediverse! <3"; constant example_text_row : integer := 15; constant example_text_col : integer := 15; begin char <= character'pos(example_text(col + 1 - example_text_col)) when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0; red <= std_logic_vector(to_unsigned(col*4, 8)); green <= std_logic_vector(to_unsigned(py, 8)); blue <= std_logic_vector(resize(frame_counter, 8)); foreground_color <= (others => '1'); process(clk) variable old_vsync : std_logic := '0'; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then frame_counter <= frame_counter + 1; end if; old_vsync := vsync; end if; end process; end architecture;

    Success!

    UART Output


    UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1077242884.4%TRELLIS_FF143242880.6%TRELLIS_IO101975.1%
    TimingClockAchievedConstraint$glbnet$clkp40.34 MHz25 MHz$glbnet$clkt370.23 MHz250 MHz
    Code

    library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1')
    );
end my_code;

architecture rtl of my_code is
    alias red   : std_logic_vector(7 downto 0) is background_color(23 downto 16);
    alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8);
    alias blue  : std_logic_vector(7 downto 0) is background_color(7 downto 0);

    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant example_text : string(1 to 19) := "Hello Fediverse! <3";
    constant example_text_row : integer := 15;
    constant example_text_col : integer := 15;
begin
    char <= character'pos(example_text(col + 1 - example_text_col))
        when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0;

    red   <= std_logic_vector(to_unsigned(col*4, 8));
    green <= std_logic_vector(to_unsigned(py, 8));
    blue  <= std_logic_vector(resize(frame_counter, 8));

    foreground_color <= (others => '1');

    process(clk)
        variable old_vsync : std_logic := '0';
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                frame_counter <= frame_counter + 1; 
            end if;
            old_vsync := vsync;
        end if;
    end process;
end architecture;


    #FPGA #Icepi-Zero #HDL #VHDL
    #fpga #icepizero #hdl #vhdl
  42. Icepi Zero Bot @[email protected] ·

    @[email protected]

    @[email protected] asked

    library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1') ); end my_code; architecture rtl of my_code is alias red : std_logic_vector(7 downto 0) is background_color(23 downto 16); alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8); alias blue : std_logic_vector(7 downto 0) is background_color(7 downto 0); signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant example_text : string(1 to 19) := "Hello Fediverse! <3"; constant example_text_row : integer := 15; constant example_text_col : integer := 15; begin char <= character'pos(example_text(col + 1 - example_text_col)) when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0; red <= std_logic_vector(to_unsigned(col*4, 8)); green <= std_logic_vector(to_unsigned(py, 8)); blue <= std_logic_vector(resize(frame_counter, 8)); foreground_color <= (others => '1'); process(clk) variable old_vsync : std_logic := '0'; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then frame_counter <= frame_counter + 1; end if; old_vsync := vsync; end if; end process; end architecture;

    Success!

    UART Output


    UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1077242884.4%TRELLIS_FF143242880.6%TRELLIS_IO101975.1%
    TimingClockAchievedConstraint$glbnet$clkp40.34 MHz25 MHz$glbnet$clkt370.23 MHz250 MHz
    Code

    library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1')
    );
end my_code;

architecture rtl of my_code is
    alias red   : std_logic_vector(7 downto 0) is background_color(23 downto 16);
    alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8);
    alias blue  : std_logic_vector(7 downto 0) is background_color(7 downto 0);

    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant example_text : string(1 to 19) := "Hello Fediverse! <3";
    constant example_text_row : integer := 15;
    constant example_text_col : integer := 15;
begin
    char <= character'pos(example_text(col + 1 - example_text_col))
        when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0;

    red   <= std_logic_vector(to_unsigned(col*4, 8));
    green <= std_logic_vector(to_unsigned(py, 8));
    blue  <= std_logic_vector(resize(frame_counter, 8));

    foreground_color <= (others => '1');

    process(clk)
        variable old_vsync : std_logic := '0';
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                frame_counter <= frame_counter + 1; 
            end if;
            old_vsync := vsync;
        end if;
    end process;
end architecture;


    #FPGA #Icepi-Zero #HDL #VHDL
    #fpga #icepizero #hdl #vhdl
  43. Icepi Zero Bot @[email protected] ·

    @[email protected]

    @[email protected] asked

    library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1') ); end my_code; architecture rtl of my_code is constant IMAGE_WIDTH : integer := 117; constant IMAGE_HEIGHT : integer := 52; type image_type is array (0 to IMAGE_HEIGHT-1) of std_logic_vector(0 to IMAGE_WIDTH-1); constant image : image_type := ( "000000000111111111111111111111111111111111111111111111000000000000000000011111111111111111111111111111111100000000000", "000000000111111111111111111111111111111111111111111111000000000000000000111111111111111111111111111111111111100000000", "000000000111111111111111111111111111111111111111111111000000000000000001111111111111111111111111111111111111111000000", "000000000111111111111111111111111111111111111111111111100000000000000011111111111111111111111111111111111111111110000", "000000001111111111111111111111111111111111111111111111100000000000000011111111111111111111111111111111111111111111000", "000000001111111111111111111111111111111111111111111111100000000000000111111111111111111111111111111111111111111111100", "000000001111111111111111111111111111111111111111111111110000000000001111111111111111111111111111111111111111111111110", "000000001111111111110000000111111111111111111111111111110000000000011111111111111111111111110000000111111111111111111", "000000011111111111110000000000111111111111111111111111110000000000011111111111111111111111110000000000111111111111111", "000000011111111111110000000000011111111111111111111111111000000000111111111111111111111111110000000000011111111111111", "000000011111111111100000000000001111111111111111111111111000000001111111111111011111111111100000000000001111111111111", "000000011111111111100000000000000111111111111011111111111000000011111111111110011111111111100000000000000111111111111", "000000111111111111100000000000000111111111111011111111111100000111111111111100111111111111100000000000000111111111111", "000000111111111111100000000000000111111111111011111111111100000111111111111000111111111111100000000000000111111111111", "000000111111111111000000000000001111111111111001111111111100001111111111110000111111111111100000000000001111111111111", "000000111111111111000000000000001111111111111001111111111110011111111111110000111111111111000000000000001111111111111", "000001111111111111000000000000001111111111110001111111111110111111111111100000111111111111000000000000001111111111111", "000001111111111111000000000000011111111111110000111111111110111111111111000001111111111111000000000000011111111111110", "000001111111111111000000000000111111111111110000111111111111111111111110000001111111111111000000000000111111111111110", "000001111111111110000000000001111111111111100000111111111111111111111100000001111111111110000000000001111111111111100", "000001111111111110000000000111111111111111000000011111111111111111111000000001111111111110000000000111111111111111000", "000011111111111110000000111111111111111110000000011111111111111111110000000011111111111110000000111111111111111110000", "000011111111111111111111111111111111111100000000011111111111111111100000000011111111111111111111111111111111111100000", "000011111111111111111111111111111111111000000000001111111111111111100000000011111111111111111111111111111111111000000", "000011111111111111111111111111111111110000000000001111111111111111000000000011111111111111111111111111111111110000000", "000111111111111111111111111111111111000000000000000111111111111110000000000111111111111111111111111111111111000000000", "000111111111111111111111111111111100000000000000000111111111111100000000000111111111111111111111111111111100000000000", "000111111111111111111111111111100000000000000000000111111111111000000000000111111111111111111111111111100000000000000", "000111111111111111111111111100000000000000000000000011111111110000000000000111111111111111111111111100000000000000000", "000111111111111111111100000000000000000000000000000011111111100000000000000111111111111111111100000000000000000000000", "000000000000000000000000000000000000000000000000000011111111100000000000000000000000000000000000000000000000000000000", "000000000000000000000000000000000000000000000000000001111111000000000000000000000000000000000000000000000000000000000", "000000000000000000000000000000000000000000000000000001111110000000000000000000000000000000000000000000000000000000000", "000000000000000000000000000000000000000000000000000001111100000000000000000000000000000000000000000000000000000000000", "000000000000000000000000000000000000000000000000000000111000000000000000000000000000000000000000000000000000000000000", "000000000000000000000000000000000000000000000000000000110000000000000000000000000000000000000000000000000000000000000", "000000000000000000000000000001111111111111111111111111111111111111111111111111111000000000000000000000000000000000000", "000000000000000000011111111111111111111111111111111111111111111111111111111111111111111111100000000000000000000000000", "000000000000111111111111111111111111111111111111111111111111111111111111111111111111111111111111110000000000000000000", "000000011111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100000000000000", "000011111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110000000000", "011111111111111111111110011111001111111001111111000000011111111100000011111111100000001111111111111111111111100000000", "111111111111111111111110011111001111111001111111001111001111111100111111111111001111100111111111111111111111110000000", "111111111111111111111111001110011111111001111111001111100111111100111111111110011111110011111111111111111111111000000", "111111111111111111111111101100111111111001111111001111100111111100000011111110011111110011111111111111111111111000000", "111111111111111111111111100101111111111001111111001111100111111100111111111110011111110011111111111111111111110000000", "011111111111111111111111110001111111111001111111001111001111111100111111111111001111100111111111111111111111100000000", "000011111111111111111111111011111111111001111111000000011111111100000011111111100000001111111111111111111110000000000", "000000011111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100000000000000", "000000000000111111111111111111111111111111111111111111111111111111111111111111111111111111111111110000000000000000000", "000000000000000000011111111111111111111111111111111111111111111111111111111111111111111111110000000000000000000000000", "000000000000000000000000000001111111111111111111111111111111111111111111111111111100000000000000000000000000000000000" ); constant SPEED : integer := 8; signal position_x : integer range -SPEED to WIDTH + SPEED := 0; signal position_y : integer range -SPEED to HEIGHT + SPEED := 0; signal random_bit : std_logic := '0'; signal color : std_logic_vector(23 downto 0) := x"FFFFFF"; component OSCG is generic ( DIV : integer := 128 ); port ( OSC : out std_logic ); end component; begin char <= 0; background_color <= color when image(py - position_y)(px - position_x) = '1' and px >= position_x and px < position_x + IMAGE_WIDTH and py >= position_y and py < position_y + IMAGE_HEIGHT else x"000000"; foreground_color <= (others => '1'); rng : OSCG port map ( OSC => random_bit ); process(clk) variable old_vsync : std_logic := '0'; variable speed_x : integer range -SPEED to SPEED := SPEED; variable speed_y : integer range -SPEED to SPEED := SPEED; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then if position_x + speed_x + IMAGE_WIDTH >= WIDTH then speed_x := -SPEED; position_x <= WIDTH - IMAGE_WIDTH - 1; color <= color(22 downto 0) & random_bit; elsif position_x + speed_x < 0 then speed_x := SPEED; position_x <= 0; color <= color(22 downto 0) & random_bit; else position_x <= position_x + speed_x; end if; if position_y + speed_y + IMAGE_HEIGHT >= HEIGHT then speed_y := -SPEED; position_y <= HEIGHT - IMAGE_HEIGHT - 1; color <= color(22 downto 0) & random_bit; elsif position_y + speed_y < 0 then speed_y := SPEED; position_y <= 0; color <= color(22 downto 0) & random_bit; else position_y <= position_y + speed_y; end if; end if; old_vsync := vsync; end if; end process; end architecture;

    Success!

    UART Output


    UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%MULT18X18D1283.6%OSCG11100.0%TRELLIS_COMB1447242886.0%TRELLIS_FF180242880.7%TRELLIS_IO101975.1%
    TimingClockAchievedConstraint$glbnet$clkp34.93 MHz25 MHz$glbnet$clkt319.28 MHz250 MHz
    Code

    library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1')
    );
end my_code;

architecture rtl of my_code is
    constant IMAGE_WIDTH : integer := 117;
    constant IMAGE_HEIGHT : integer := 52;

    type image_type is array (0 to IMAGE_HEIGHT-1) of std_logic_vector(0 to IMAGE_WIDTH-1);
    constant image : image_type := (
"000000000111111111111111111111111111111111111111111111000000000000000000011111111111111111111111111111111100000000000",
"000000000111111111111111111111111111111111111111111111000000000000000000111111111111111111111111111111111111100000000",
"000000000111111111111111111111111111111111111111111111000000000000000001111111111111111111111111111111111111111000000",
"000000000111111111111111111111111111111111111111111111100000000000000011111111111111111111111111111111111111111110000",
"000000001111111111111111111111111111111111111111111111100000000000000011111111111111111111111111111111111111111111000",
"000000001111111111111111111111111111111111111111111111100000000000000111111111111111111111111111111111111111111111100",
"000000001111111111111111111111111111111111111111111111110000000000001111111111111111111111111111111111111111111111110",
"000000001111111111110000000111111111111111111111111111110000000000011111111111111111111111110000000111111111111111111",
"000000011111111111110000000000111111111111111111111111110000000000011111111111111111111111110000000000111111111111111",
"000000011111111111110000000000011111111111111111111111111000000000111111111111111111111111110000000000011111111111111",
"000000011111111111100000000000001111111111111111111111111000000001111111111111011111111111100000000000001111111111111",
"000000011111111111100000000000000111111111111011111111111000000011111111111110011111111111100000000000000111111111111",
"000000111111111111100000000000000111111111111011111111111100000111111111111100111111111111100000000000000111111111111",
"000000111111111111100000000000000111111111111011111111111100000111111111111000111111111111100000000000000111111111111",
"000000111111111111000000000000001111111111111001111111111100001111111111110000111111111111100000000000001111111111111",
"000000111111111111000000000000001111111111111001111111111110011111111111110000111111111111000000000000001111111111111",
"000001111111111111000000000000001111111111110001111111111110111111111111100000111111111111000000000000001111111111111",
"000001111111111111000000000000011111111111110000111111111110111111111111000001111111111111000000000000011111111111110",
"000001111111111111000000000000111111111111110000111111111111111111111110000001111111111111000000000000111111111111110",
"000001111111111110000000000001111111111111100000111111111111111111111100000001111111111110000000000001111111111111100",
"000001111111111110000000000111111111111111000000011111111111111111111000000001111111111110000000000111111111111111000",
"000011111111111110000000111111111111111110000000011111111111111111110000000011111111111110000000111111111111111110000",
"000011111111111111111111111111111111111100000000011111111111111111100000000011111111111111111111111111111111111100000",
"000011111111111111111111111111111111111000000000001111111111111111100000000011111111111111111111111111111111111000000",
"000011111111111111111111111111111111110000000000001111111111111111000000000011111111111111111111111111111111110000000",
"000111111111111111111111111111111111000000000000000111111111111110000000000111111111111111111111111111111111000000000",
"000111111111111111111111111111111100000000000000000111111111111100000000000111111111111111111111111111111100000000000",
"000111111111111111111111111111100000000000000000000111111111111000000000000111111111111111111111111111100000000000000",
"000111111111111111111111111100000000000000000000000011111111110000000000000111111111111111111111111100000000000000000",
"000111111111111111111100000000000000000000000000000011111111100000000000000111111111111111111100000000000000000000000",
"000000000000000000000000000000000000000000000000000011111111100000000000000000000000000000000000000000000000000000000",
"000000000000000000000000000000000000000000000000000001111111000000000000000000000000000000000000000000000000000000000",
"000000000000000000000000000000000000000000000000000001111110000000000000000000000000000000000000000000000000000000000",
"000000000000000000000000000000000000000000000000000001111100000000000000000000000000000000000000000000000000000000000",
"000000000000000000000000000000000000000000000000000000111000000000000000000000000000000000000000000000000000000000000",
"000000000000000000000000000000000000000000000000000000110000000000000000000000000000000000000000000000000000000000000",
"000000000000000000000000000001111111111111111111111111111111111111111111111111111000000000000000000000000000000000000",
"000000000000000000011111111111111111111111111111111111111111111111111111111111111111111111100000000000000000000000000",
"000000000000111111111111111111111111111111111111111111111111111111111111111111111111111111111111110000000000000000000",
"000000011111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100000000000000",
"000011111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110000000000",
"011111111111111111111110011111001111111001111111000000011111111100000011111111100000001111111111111111111111100000000",
"111111111111111111111110011111001111111001111111001111001111111100111111111111001111100111111111111111111111110000000",
"111111111111111111111111001110011111111001111111001111100111111100111111111110011111110011111111111111111111111000000",
"111111111111111111111111101100111111111001111111001111100111111100000011111110011111110011111111111111111111111000000",
"111111111111111111111111100101111111111001111111001111100111111100111111111110011111110011111111111111111111110000000",
"011111111111111111111111110001111111111001111111001111001111111100111111111111001111100111111111111111111111100000000",
"000011111111111111111111111011111111111001111111000000011111111100000011111111100000001111111111111111111110000000000",
"000000011111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100000000000000",
"000000000000111111111111111111111111111111111111111111111111111111111111111111111111111111111111110000000000000000000",
"000000000000000000011111111111111111111111111111111111111111111111111111111111111111111111110000000000000000000000000",
"000000000000000000000000000001111111111111111111111111111111111111111111111111111100000000000000000000000000000000000"
    );

    constant SPEED : integer := 8;

    signal position_x : integer range -SPEED to WIDTH + SPEED := 0;
    signal position_y : integer range -SPEED to HEIGHT + SPEED := 0;

    signal random_bit : std_logic := '0';
    signal color : std_logic_vector(23 downto 0) := x"FFFFFF";

    component OSCG is
        generic (
            DIV : integer := 128
        );
        port (
            OSC : out std_logic
        );
    end component;
begin
    char <= 0;

    background_color <= color when image(py - position_y)(px - position_x) = '1' and
            px >= position_x and px < position_x + IMAGE_WIDTH and
            py >= position_y and py < position_y + IMAGE_HEIGHT
        else x"000000";
    foreground_color <= (others => '1');

    rng : OSCG port map (
        OSC => random_bit
    );

    process(clk)
        variable old_vsync : std_logic := '0';
        variable speed_x : integer range -SPEED to SPEED := SPEED;
        variable speed_y : integer range -SPEED to SPEED := SPEED;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                if position_x + speed_x + IMAGE_WIDTH >= WIDTH then
                    speed_x := -SPEED;
                    position_x <= WIDTH - IMAGE_WIDTH - 1;

                    color <= color(22 downto 0) & random_bit;
                elsif position_x + speed_x < 0 then
                    speed_x := SPEED;
                    position_x <= 0;

                    color <= color(22 downto 0) & random_bit;
                else
                    position_x <= position_x + speed_x;
                end if;

                if position_y + speed_y + IMAGE_HEIGHT >= HEIGHT then
                    speed_y := -SPEED;
                    position_y <= HEIGHT - IMAGE_HEIGHT - 1;

                    color <= color(22 downto 0) & random_bit;
                elsif position_y + speed_y < 0 then
                    speed_y := SPEED;
                    position_y <= 0;

                    color <= color(22 downto 0) & random_bit;
                else
                    position_y <= position_y + speed_y;
                end if;
            end if;
            old_vsync := vsync;
        end if;
    end process;
end architecture;


    #FPGA #Icepi-Zero #HDL #VHDL
    #fpga #icepizero #hdl #vhdl
  44. Icepi Zero Bot @[email protected] ·

    @[email protected]

    @[email protected] asked

    library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1') ); end my_code; architecture rtl of my_code is constant IMAGE_WIDTH : integer := 117; constant IMAGE_HEIGHT : integer := 52; type image_type is array (0 to IMAGE_HEIGHT-1) of std_logic_vector(0 to IMAGE_WIDTH-1); constant image : image_type := ( "000000000111111111111111111111111111111111111111111111000000000000000000011111111111111111111111111111111100000000000", "000000000111111111111111111111111111111111111111111111000000000000000000111111111111111111111111111111111111100000000", "000000000111111111111111111111111111111111111111111111000000000000000001111111111111111111111111111111111111111000000", "000000000111111111111111111111111111111111111111111111100000000000000011111111111111111111111111111111111111111110000", "000000001111111111111111111111111111111111111111111111100000000000000011111111111111111111111111111111111111111111000", "000000001111111111111111111111111111111111111111111111100000000000000111111111111111111111111111111111111111111111100", "000000001111111111111111111111111111111111111111111111110000000000001111111111111111111111111111111111111111111111110", "000000001111111111110000000111111111111111111111111111110000000000011111111111111111111111110000000111111111111111111", "000000011111111111110000000000111111111111111111111111110000000000011111111111111111111111110000000000111111111111111", "000000011111111111110000000000011111111111111111111111111000000000111111111111111111111111110000000000011111111111111", "000000011111111111100000000000001111111111111111111111111000000001111111111111011111111111100000000000001111111111111", "000000011111111111100000000000000111111111111011111111111000000011111111111110011111111111100000000000000111111111111", "000000111111111111100000000000000111111111111011111111111100000111111111111100111111111111100000000000000111111111111", "000000111111111111100000000000000111111111111011111111111100000111111111111000111111111111100000000000000111111111111", "000000111111111111000000000000001111111111111001111111111100001111111111110000111111111111100000000000001111111111111", "000000111111111111000000000000001111111111111001111111111110011111111111110000111111111111000000000000001111111111111", "000001111111111111000000000000001111111111110001111111111110111111111111100000111111111111000000000000001111111111111", "000001111111111111000000000000011111111111110000111111111110111111111111000001111111111111000000000000011111111111110", "000001111111111111000000000000111111111111110000111111111111111111111110000001111111111111000000000000111111111111110", "000001111111111110000000000001111111111111100000111111111111111111111100000001111111111110000000000001111111111111100", "000001111111111110000000000111111111111111000000011111111111111111111000000001111111111110000000000111111111111111000", "000011111111111110000000111111111111111110000000011111111111111111110000000011111111111110000000111111111111111110000", "000011111111111111111111111111111111111100000000011111111111111111100000000011111111111111111111111111111111111100000", "000011111111111111111111111111111111111000000000001111111111111111100000000011111111111111111111111111111111111000000", "000011111111111111111111111111111111110000000000001111111111111111000000000011111111111111111111111111111111110000000", "000111111111111111111111111111111111000000000000000111111111111110000000000111111111111111111111111111111111000000000", "000111111111111111111111111111111100000000000000000111111111111100000000000111111111111111111111111111111100000000000", "000111111111111111111111111111100000000000000000000111111111111000000000000111111111111111111111111111100000000000000", "000111111111111111111111111100000000000000000000000011111111110000000000000111111111111111111111111100000000000000000", "000111111111111111111100000000000000000000000000000011111111100000000000000111111111111111111100000000000000000000000", "000000000000000000000000000000000000000000000000000011111111100000000000000000000000000000000000000000000000000000000", "000000000000000000000000000000000000000000000000000001111111000000000000000000000000000000000000000000000000000000000", "000000000000000000000000000000000000000000000000000001111110000000000000000000000000000000000000000000000000000000000", "000000000000000000000000000000000000000000000000000001111100000000000000000000000000000000000000000000000000000000000", "000000000000000000000000000000000000000000000000000000111000000000000000000000000000000000000000000000000000000000000", "000000000000000000000000000000000000000000000000000000110000000000000000000000000000000000000000000000000000000000000", "000000000000000000000000000001111111111111111111111111111111111111111111111111111000000000000000000000000000000000000", "000000000000000000011111111111111111111111111111111111111111111111111111111111111111111111100000000000000000000000000", "000000000000111111111111111111111111111111111111111111111111111111111111111111111111111111111111110000000000000000000", "000000011111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100000000000000", "000011111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110000000000", "011111111111111111111110011111001111111001111111000000011111111100000011111111100000001111111111111111111111100000000", "111111111111111111111110011111001111111001111111001111001111111100111111111111001111100111111111111111111111110000000", "111111111111111111111111001110011111111001111111001111100111111100111111111110011111110011111111111111111111111000000", "111111111111111111111111101100111111111001111111001111100111111100000011111110011111110011111111111111111111111000000", "111111111111111111111111100101111111111001111111001111100111111100111111111110011111110011111111111111111111110000000", "011111111111111111111111110001111111111001111111001111001111111100111111111111001111100111111111111111111111100000000", "000011111111111111111111111011111111111001111111000000011111111100000011111111100000001111111111111111111110000000000", "000000011111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100000000000000", "000000000000111111111111111111111111111111111111111111111111111111111111111111111111111111111111110000000000000000000", "000000000000000000011111111111111111111111111111111111111111111111111111111111111111111111110000000000000000000000000", "000000000000000000000000000001111111111111111111111111111111111111111111111111111100000000000000000000000000000000000" ); constant SPEED : integer := 8; signal position_x : integer range -SPEED to WIDTH + SPEED := 0; signal position_y : integer range -SPEED to HEIGHT + SPEED := 0; signal random_bit : std_logic := '0'; signal color : std_logic_vector(23 downto 0) := x"FFFFFF"; component OSCG is generic ( DIV : integer := 128 ); port ( OSC : out std_logic ); end component; begin char <= 0; background_color <= color when image(py - position_y)(px - position_x) = '1' and px >= position_x and px < position_x + IMAGE_WIDTH and py >= position_y and py < position_y + IMAGE_HEIGHT else x"000000"; foreground_color <= (others => '1'); rng : OSCG port map ( OSC => random_bit ); process(clk) variable old_vsync : std_logic := '0'; variable speed_x : integer range -SPEED to SPEED := SPEED; variable speed_y : integer range -SPEED to SPEED := SPEED; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then if position_x + speed_x + IMAGE_WIDTH >= WIDTH then speed_x := -SPEED; position_x <= WIDTH - IMAGE_WIDTH - 1; color <= color(22 downto 0) & random_bit; elsif position_x + speed_x < 0 then speed_x := SPEED; position_x <= 0; color <= color(22 downto 0) & random_bit; else position_x <= position_x + speed_x; end if; if position_y + speed_y + IMAGE_HEIGHT >= HEIGHT then speed_y := -SPEED; position_y <= HEIGHT - IMAGE_HEIGHT - 1; color <= color(22 downto 0) & random_bit; elsif position_y + speed_y < 0 then speed_y := SPEED; position_y <= 0; color <= color(22 downto 0) & random_bit; else position_y <= position_y + speed_y; end if; end if; old_vsync := vsync; end if; end process; end architecture;

    Success!

    UART Output


    UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%MULT18X18D1283.6%OSCG11100.0%TRELLIS_COMB1447242886.0%TRELLIS_FF180242880.7%TRELLIS_IO101975.1%
    TimingClockAchievedConstraint$glbnet$clkp34.93 MHz25 MHz$glbnet$clkt319.28 MHz250 MHz
    Code

    library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1')
    );
end my_code;

architecture rtl of my_code is
    constant IMAGE_WIDTH : integer := 117;
    constant IMAGE_HEIGHT : integer := 52;

    type image_type is array (0 to IMAGE_HEIGHT-1) of std_logic_vector(0 to IMAGE_WIDTH-1);
    constant image : image_type := (
"000000000111111111111111111111111111111111111111111111000000000000000000011111111111111111111111111111111100000000000",
"000000000111111111111111111111111111111111111111111111000000000000000000111111111111111111111111111111111111100000000",
"000000000111111111111111111111111111111111111111111111000000000000000001111111111111111111111111111111111111111000000",
"000000000111111111111111111111111111111111111111111111100000000000000011111111111111111111111111111111111111111110000",
"000000001111111111111111111111111111111111111111111111100000000000000011111111111111111111111111111111111111111111000",
"000000001111111111111111111111111111111111111111111111100000000000000111111111111111111111111111111111111111111111100",
"000000001111111111111111111111111111111111111111111111110000000000001111111111111111111111111111111111111111111111110",
"000000001111111111110000000111111111111111111111111111110000000000011111111111111111111111110000000111111111111111111",
"000000011111111111110000000000111111111111111111111111110000000000011111111111111111111111110000000000111111111111111",
"000000011111111111110000000000011111111111111111111111111000000000111111111111111111111111110000000000011111111111111",
"000000011111111111100000000000001111111111111111111111111000000001111111111111011111111111100000000000001111111111111",
"000000011111111111100000000000000111111111111011111111111000000011111111111110011111111111100000000000000111111111111",
"000000111111111111100000000000000111111111111011111111111100000111111111111100111111111111100000000000000111111111111",
"000000111111111111100000000000000111111111111011111111111100000111111111111000111111111111100000000000000111111111111",
"000000111111111111000000000000001111111111111001111111111100001111111111110000111111111111100000000000001111111111111",
"000000111111111111000000000000001111111111111001111111111110011111111111110000111111111111000000000000001111111111111",
"000001111111111111000000000000001111111111110001111111111110111111111111100000111111111111000000000000001111111111111",
"000001111111111111000000000000011111111111110000111111111110111111111111000001111111111111000000000000011111111111110",
"000001111111111111000000000000111111111111110000111111111111111111111110000001111111111111000000000000111111111111110",
"000001111111111110000000000001111111111111100000111111111111111111111100000001111111111110000000000001111111111111100",
"000001111111111110000000000111111111111111000000011111111111111111111000000001111111111110000000000111111111111111000",
"000011111111111110000000111111111111111110000000011111111111111111110000000011111111111110000000111111111111111110000",
"000011111111111111111111111111111111111100000000011111111111111111100000000011111111111111111111111111111111111100000",
"000011111111111111111111111111111111111000000000001111111111111111100000000011111111111111111111111111111111111000000",
"000011111111111111111111111111111111110000000000001111111111111111000000000011111111111111111111111111111111110000000",
"000111111111111111111111111111111111000000000000000111111111111110000000000111111111111111111111111111111111000000000",
"000111111111111111111111111111111100000000000000000111111111111100000000000111111111111111111111111111111100000000000",
"000111111111111111111111111111100000000000000000000111111111111000000000000111111111111111111111111111100000000000000",
"000111111111111111111111111100000000000000000000000011111111110000000000000111111111111111111111111100000000000000000",
"000111111111111111111100000000000000000000000000000011111111100000000000000111111111111111111100000000000000000000000",
"000000000000000000000000000000000000000000000000000011111111100000000000000000000000000000000000000000000000000000000",
"000000000000000000000000000000000000000000000000000001111111000000000000000000000000000000000000000000000000000000000",
"000000000000000000000000000000000000000000000000000001111110000000000000000000000000000000000000000000000000000000000",
"000000000000000000000000000000000000000000000000000001111100000000000000000000000000000000000000000000000000000000000",
"000000000000000000000000000000000000000000000000000000111000000000000000000000000000000000000000000000000000000000000",
"000000000000000000000000000000000000000000000000000000110000000000000000000000000000000000000000000000000000000000000",
"000000000000000000000000000001111111111111111111111111111111111111111111111111111000000000000000000000000000000000000",
"000000000000000000011111111111111111111111111111111111111111111111111111111111111111111111100000000000000000000000000",
"000000000000111111111111111111111111111111111111111111111111111111111111111111111111111111111111110000000000000000000",
"000000011111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100000000000000",
"000011111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110000000000",
"011111111111111111111110011111001111111001111111000000011111111100000011111111100000001111111111111111111111100000000",
"111111111111111111111110011111001111111001111111001111001111111100111111111111001111100111111111111111111111110000000",
"111111111111111111111111001110011111111001111111001111100111111100111111111110011111110011111111111111111111111000000",
"111111111111111111111111101100111111111001111111001111100111111100000011111110011111110011111111111111111111111000000",
"111111111111111111111111100101111111111001111111001111100111111100111111111110011111110011111111111111111111110000000",
"011111111111111111111111110001111111111001111111001111001111111100111111111111001111100111111111111111111111100000000",
"000011111111111111111111111011111111111001111111000000011111111100000011111111100000001111111111111111111110000000000",
"000000011111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100000000000000",
"000000000000111111111111111111111111111111111111111111111111111111111111111111111111111111111111110000000000000000000",
"000000000000000000011111111111111111111111111111111111111111111111111111111111111111111111110000000000000000000000000",
"000000000000000000000000000001111111111111111111111111111111111111111111111111111100000000000000000000000000000000000"
    );

    constant SPEED : integer := 8;

    signal position_x : integer range -SPEED to WIDTH + SPEED := 0;
    signal position_y : integer range -SPEED to HEIGHT + SPEED := 0;

    signal random_bit : std_logic := '0';
    signal color : std_logic_vector(23 downto 0) := x"FFFFFF";

    component OSCG is
        generic (
            DIV : integer := 128
        );
        port (
            OSC : out std_logic
        );
    end component;
begin
    char <= 0;

    background_color <= color when image(py - position_y)(px - position_x) = '1' and
            px >= position_x and px < position_x + IMAGE_WIDTH and
            py >= position_y and py < position_y + IMAGE_HEIGHT
        else x"000000";
    foreground_color <= (others => '1');

    rng : OSCG port map (
        OSC => random_bit
    );

    process(clk)
        variable old_vsync : std_logic := '0';
        variable speed_x : integer range -SPEED to SPEED := SPEED;
        variable speed_y : integer range -SPEED to SPEED := SPEED;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                if position_x + speed_x + IMAGE_WIDTH >= WIDTH then
                    speed_x := -SPEED;
                    position_x <= WIDTH - IMAGE_WIDTH - 1;

                    color <= color(22 downto 0) & random_bit;
                elsif position_x + speed_x < 0 then
                    speed_x := SPEED;
                    position_x <= 0;

                    color <= color(22 downto 0) & random_bit;
                else
                    position_x <= position_x + speed_x;
                end if;

                if position_y + speed_y + IMAGE_HEIGHT >= HEIGHT then
                    speed_y := -SPEED;
                    position_y <= HEIGHT - IMAGE_HEIGHT - 1;

                    color <= color(22 downto 0) & random_bit;
                elsif position_y + speed_y < 0 then
                    speed_y := SPEED;
                    position_y <= 0;

                    color <= color(22 downto 0) & random_bit;
                else
                    position_y <= position_y + speed_y;
                end if;
            end if;
            old_vsync := vsync;
        end if;
    end process;
end architecture;


    #FPGA #Icepi-Zero #HDL #VHDL
    #fpga #icepizero #hdl #vhdl
  45. Icepi Zero Bot @[email protected] ·

    @[email protected]

    @[email protected] asked

    library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1') ); end my_code; architecture rtl of my_code is constant IMAGE_WIDTH : integer := 117; constant IMAGE_HEIGHT : integer := 52; type image_type is array (0 to IMAGE_HEIGHT-1) of std_logic_vector(0 to IMAGE_WIDTH-1); constant image : image_type := ( "000000000111111111111111111111111111111111111111111111000000000000000000011111111111111111111111111111111100000000000", "000000000111111111111111111111111111111111111111111111000000000000000000111111111111111111111111111111111111100000000", "000000000111111111111111111111111111111111111111111111000000000000000001111111111111111111111111111111111111111000000", "000000000111111111111111111111111111111111111111111111100000000000000011111111111111111111111111111111111111111110000", "000000001111111111111111111111111111111111111111111111100000000000000011111111111111111111111111111111111111111111000", "000000001111111111111111111111111111111111111111111111100000000000000111111111111111111111111111111111111111111111100", "000000001111111111111111111111111111111111111111111111110000000000001111111111111111111111111111111111111111111111110", "000000001111111111110000000111111111111111111111111111110000000000011111111111111111111111110000000111111111111111111", "000000011111111111110000000000111111111111111111111111110000000000011111111111111111111111110000000000111111111111111", "000000011111111111110000000000011111111111111111111111111000000000111111111111111111111111110000000000011111111111111", "000000011111111111100000000000001111111111111111111111111000000001111111111111011111111111100000000000001111111111111", "000000011111111111100000000000000111111111111011111111111000000011111111111110011111111111100000000000000111111111111", "000000111111111111100000000000000111111111111011111111111100000111111111111100111111111111100000000000000111111111111", "000000111111111111100000000000000111111111111011111111111100000111111111111000111111111111100000000000000111111111111", "000000111111111111000000000000001111111111111001111111111100001111111111110000111111111111100000000000001111111111111", "000000111111111111000000000000001111111111111001111111111110011111111111110000111111111111000000000000001111111111111", "000001111111111111000000000000001111111111110001111111111110111111111111100000111111111111000000000000001111111111111", "000001111111111111000000000000011111111111110000111111111110111111111111000001111111111111000000000000011111111111110", "000001111111111111000000000000111111111111110000111111111111111111111110000001111111111111000000000000111111111111110", "000001111111111110000000000001111111111111100000111111111111111111111100000001111111111110000000000001111111111111100", "000001111111111110000000000111111111111111000000011111111111111111111000000001111111111110000000000111111111111111000", "000011111111111110000000111111111111111110000000011111111111111111110000000011111111111110000000111111111111111110000", "000011111111111111111111111111111111111100000000011111111111111111100000000011111111111111111111111111111111111100000", "000011111111111111111111111111111111111000000000001111111111111111100000000011111111111111111111111111111111111000000", "000011111111111111111111111111111111110000000000001111111111111111000000000011111111111111111111111111111111110000000", "000111111111111111111111111111111111000000000000000111111111111110000000000111111111111111111111111111111111000000000", "000111111111111111111111111111111100000000000000000111111111111100000000000111111111111111111111111111111100000000000", "000111111111111111111111111111100000000000000000000111111111111000000000000111111111111111111111111111100000000000000", "000111111111111111111111111100000000000000000000000011111111110000000000000111111111111111111111111100000000000000000", "000111111111111111111100000000000000000000000000000011111111100000000000000111111111111111111100000000000000000000000", "000000000000000000000000000000000000000000000000000011111111100000000000000000000000000000000000000000000000000000000", "000000000000000000000000000000000000000000000000000001111111000000000000000000000000000000000000000000000000000000000", "000000000000000000000000000000000000000000000000000001111110000000000000000000000000000000000000000000000000000000000", "000000000000000000000000000000000000000000000000000001111100000000000000000000000000000000000000000000000000000000000", "000000000000000000000000000000000000000000000000000000111000000000000000000000000000000000000000000000000000000000000", "000000000000000000000000000000000000000000000000000000110000000000000000000000000000000000000000000000000000000000000", "000000000000000000000000000001111111111111111111111111111111111111111111111111111000000000000000000000000000000000000", "000000000000000000011111111111111111111111111111111111111111111111111111111111111111111111100000000000000000000000000", "000000000000111111111111111111111111111111111111111111111111111111111111111111111111111111111111110000000000000000000", "000000011111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100000000000000", "000011111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110000000000", "011111111111111111111110011111001111111001111111000000011111111100000011111111100000001111111111111111111111100000000", "111111111111111111111110011111001111111001111111001111001111111100111111111111001111100111111111111111111111110000000", "111111111111111111111111001110011111111001111111001111100111111100111111111110011111110011111111111111111111111000000", "111111111111111111111111101100111111111001111111001111100111111100000011111110011111110011111111111111111111111000000", "111111111111111111111111100101111111111001111111001111100111111100111111111110011111110011111111111111111111110000000", "011111111111111111111111110001111111111001111111001111001111111100111111111111001111100111111111111111111111100000000", "000011111111111111111111111011111111111001111111000000011111111100000011111111100000001111111111111111111110000000000", "000000011111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100000000000000", "000000000000111111111111111111111111111111111111111111111111111111111111111111111111111111111111110000000000000000000", "000000000000000000011111111111111111111111111111111111111111111111111111111111111111111111110000000000000000000000000", "000000000000000000000000000001111111111111111111111111111111111111111111111111111100000000000000000000000000000000000" ); constant SPEED : integer := 8; signal position_x : integer range -SPEED to WIDTH + SPEED := 0; signal position_y : integer range -SPEED to HEIGHT + SPEED := 0; signal random_bit : std_logic := '0'; signal color : std_logic_vector(23 downto 0) := x"FFFFFF"; component OSCG is generic ( DIV : integer := 128 ); port ( OSC : out std_logic ); end component; begin char <= 0; background_color <= color when image(py - position_y)(px - position_x) = '1' and px >= position_x and px < position_x + IMAGE_WIDTH and py >= position_y and py < position_y + IMAGE_HEIGHT else x"000000"; foreground_color <= (others => '1'); rng : OSCG port map ( OSC => random_bit ); process(clk) variable old_vsync : std_logic := '0'; variable speed_x : integer range -SPEED to SPEED := SPEED; variable speed_y : integer range -SPEED to SPEED := SPEED; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then if position_x + speed_x + IMAGE_WIDTH >= WIDTH then speed_x := -SPEED; position_x <= WIDTH - IMAGE_WIDTH - 1; color <= color(22 downto 0) & random_bit; elsif position_x + speed_x < 0 then speed_x := SPEED; position_x <= 0; color <= color(22 downto 0) & random_bit; else position_x <= position_x + speed_x; end if; if position_y + speed_y + IMAGE_HEIGHT >= HEIGHT then speed_y := -SPEED; position_y <= HEIGHT - IMAGE_HEIGHT - 1; color <= color(22 downto 0) & random_bit; elsif position_y + speed_y < 0 then speed_y := SPEED; position_y <= 0; color <= color(22 downto 0) & random_bit; else position_y <= position_y + speed_y; end if; end if; old_vsync := vsync; end if; end process; end architecture;

    Success!

    UART Output


    UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%MULT18X18D1283.6%OSCG11100.0%TRELLIS_COMB1447242886.0%TRELLIS_FF180242880.7%TRELLIS_IO101975.1%
    TimingClockAchievedConstraint$glbnet$clkp34.93 MHz25 MHz$glbnet$clkt319.28 MHz250 MHz
    Code

    library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1')
    );
end my_code;

architecture rtl of my_code is
    constant IMAGE_WIDTH : integer := 117;
    constant IMAGE_HEIGHT : integer := 52;

    type image_type is array (0 to IMAGE_HEIGHT-1) of std_logic_vector(0 to IMAGE_WIDTH-1);
    constant image : image_type := (
"000000000111111111111111111111111111111111111111111111000000000000000000011111111111111111111111111111111100000000000",
"000000000111111111111111111111111111111111111111111111000000000000000000111111111111111111111111111111111111100000000",
"000000000111111111111111111111111111111111111111111111000000000000000001111111111111111111111111111111111111111000000",
"000000000111111111111111111111111111111111111111111111100000000000000011111111111111111111111111111111111111111110000",
"000000001111111111111111111111111111111111111111111111100000000000000011111111111111111111111111111111111111111111000",
"000000001111111111111111111111111111111111111111111111100000000000000111111111111111111111111111111111111111111111100",
"000000001111111111111111111111111111111111111111111111110000000000001111111111111111111111111111111111111111111111110",
"000000001111111111110000000111111111111111111111111111110000000000011111111111111111111111110000000111111111111111111",
"000000011111111111110000000000111111111111111111111111110000000000011111111111111111111111110000000000111111111111111",
"000000011111111111110000000000011111111111111111111111111000000000111111111111111111111111110000000000011111111111111",
"000000011111111111100000000000001111111111111111111111111000000001111111111111011111111111100000000000001111111111111",
"000000011111111111100000000000000111111111111011111111111000000011111111111110011111111111100000000000000111111111111",
"000000111111111111100000000000000111111111111011111111111100000111111111111100111111111111100000000000000111111111111",
"000000111111111111100000000000000111111111111011111111111100000111111111111000111111111111100000000000000111111111111",
"000000111111111111000000000000001111111111111001111111111100001111111111110000111111111111100000000000001111111111111",
"000000111111111111000000000000001111111111111001111111111110011111111111110000111111111111000000000000001111111111111",
"000001111111111111000000000000001111111111110001111111111110111111111111100000111111111111000000000000001111111111111",
"000001111111111111000000000000011111111111110000111111111110111111111111000001111111111111000000000000011111111111110",
"000001111111111111000000000000111111111111110000111111111111111111111110000001111111111111000000000000111111111111110",
"000001111111111110000000000001111111111111100000111111111111111111111100000001111111111110000000000001111111111111100",
"000001111111111110000000000111111111111111000000011111111111111111111000000001111111111110000000000111111111111111000",
"000011111111111110000000111111111111111110000000011111111111111111110000000011111111111110000000111111111111111110000",
"000011111111111111111111111111111111111100000000011111111111111111100000000011111111111111111111111111111111111100000",
"000011111111111111111111111111111111111000000000001111111111111111100000000011111111111111111111111111111111111000000",
"000011111111111111111111111111111111110000000000001111111111111111000000000011111111111111111111111111111111110000000",
"000111111111111111111111111111111111000000000000000111111111111110000000000111111111111111111111111111111111000000000",
"000111111111111111111111111111111100000000000000000111111111111100000000000111111111111111111111111111111100000000000",
"000111111111111111111111111111100000000000000000000111111111111000000000000111111111111111111111111111100000000000000",
"000111111111111111111111111100000000000000000000000011111111110000000000000111111111111111111111111100000000000000000",
"000111111111111111111100000000000000000000000000000011111111100000000000000111111111111111111100000000000000000000000",
"000000000000000000000000000000000000000000000000000011111111100000000000000000000000000000000000000000000000000000000",
"000000000000000000000000000000000000000000000000000001111111000000000000000000000000000000000000000000000000000000000",
"000000000000000000000000000000000000000000000000000001111110000000000000000000000000000000000000000000000000000000000",
"000000000000000000000000000000000000000000000000000001111100000000000000000000000000000000000000000000000000000000000",
"000000000000000000000000000000000000000000000000000000111000000000000000000000000000000000000000000000000000000000000",
"000000000000000000000000000000000000000000000000000000110000000000000000000000000000000000000000000000000000000000000",
"000000000000000000000000000001111111111111111111111111111111111111111111111111111000000000000000000000000000000000000",
"000000000000000000011111111111111111111111111111111111111111111111111111111111111111111111100000000000000000000000000",
"000000000000111111111111111111111111111111111111111111111111111111111111111111111111111111111111110000000000000000000",
"000000011111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100000000000000",
"000011111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110000000000",
"011111111111111111111110011111001111111001111111000000011111111100000011111111100000001111111111111111111111100000000",
"111111111111111111111110011111001111111001111111001111001111111100111111111111001111100111111111111111111111110000000",
"111111111111111111111111001110011111111001111111001111100111111100111111111110011111110011111111111111111111111000000",
"111111111111111111111111101100111111111001111111001111100111111100000011111110011111110011111111111111111111111000000",
"111111111111111111111111100101111111111001111111001111100111111100111111111110011111110011111111111111111111110000000",
"011111111111111111111111110001111111111001111111001111001111111100111111111111001111100111111111111111111111100000000",
"000011111111111111111111111011111111111001111111000000011111111100000011111111100000001111111111111111111110000000000",
"000000011111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100000000000000",
"000000000000111111111111111111111111111111111111111111111111111111111111111111111111111111111111110000000000000000000",
"000000000000000000011111111111111111111111111111111111111111111111111111111111111111111111110000000000000000000000000",
"000000000000000000000000000001111111111111111111111111111111111111111111111111111100000000000000000000000000000000000"
    );

    constant SPEED : integer := 8;

    signal position_x : integer range -SPEED to WIDTH + SPEED := 0;
    signal position_y : integer range -SPEED to HEIGHT + SPEED := 0;

    signal random_bit : std_logic := '0';
    signal color : std_logic_vector(23 downto 0) := x"FFFFFF";

    component OSCG is
        generic (
            DIV : integer := 128
        );
        port (
            OSC : out std_logic
        );
    end component;
begin
    char <= 0;

    background_color <= color when image(py - position_y)(px - position_x) = '1' and
            px >= position_x and px < position_x + IMAGE_WIDTH and
            py >= position_y and py < position_y + IMAGE_HEIGHT
        else x"000000";
    foreground_color <= (others => '1');

    rng : OSCG port map (
        OSC => random_bit
    );

    process(clk)
        variable old_vsync : std_logic := '0';
        variable speed_x : integer range -SPEED to SPEED := SPEED;
        variable speed_y : integer range -SPEED to SPEED := SPEED;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                if position_x + speed_x + IMAGE_WIDTH >= WIDTH then
                    speed_x := -SPEED;
                    position_x <= WIDTH - IMAGE_WIDTH - 1;

                    color <= color(22 downto 0) & random_bit;
                elsif position_x + speed_x < 0 then
                    speed_x := SPEED;
                    position_x <= 0;

                    color <= color(22 downto 0) & random_bit;
                else
                    position_x <= position_x + speed_x;
                end if;

                if position_y + speed_y + IMAGE_HEIGHT >= HEIGHT then
                    speed_y := -SPEED;
                    position_y <= HEIGHT - IMAGE_HEIGHT - 1;

                    color <= color(22 downto 0) & random_bit;
                elsif position_y + speed_y < 0 then
                    speed_y := SPEED;
                    position_y <= 0;

                    color <= color(22 downto 0) & random_bit;
                else
                    position_y <= position_y + speed_y;
                end if;
            end if;
            old_vsync := vsync;
        end if;
    end process;
end architecture;


    #FPGA #Icepi-Zero #HDL #VHDL
    #fpga #icepizero #hdl #vhdl
  46. Icepi Zero Bot @[email protected] ·

    @[email protected]

    @[email protected] asked

    library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1') ); end my_code; architecture rtl of my_code is constant IMAGE_WIDTH : integer := 117; constant IMAGE_HEIGHT : integer := 52; type image_type is array (0 to IMAGE_HEIGHT-1) of std_logic_vector(0 to IMAGE_WIDTH-1); constant image : image_type := ( "000000000111111111111111111111111111111111111111111111000000000000000000011111111111111111111111111111111100000000000", "000000000111111111111111111111111111111111111111111111000000000000000000111111111111111111111111111111111111100000000", "000000000111111111111111111111111111111111111111111111000000000000000001111111111111111111111111111111111111111000000", "000000000111111111111111111111111111111111111111111111100000000000000011111111111111111111111111111111111111111110000", "000000001111111111111111111111111111111111111111111111100000000000000011111111111111111111111111111111111111111111000", "000000001111111111111111111111111111111111111111111111100000000000000111111111111111111111111111111111111111111111100", "000000001111111111111111111111111111111111111111111111110000000000001111111111111111111111111111111111111111111111110", "000000001111111111110000000111111111111111111111111111110000000000011111111111111111111111110000000111111111111111111", "000000011111111111110000000000111111111111111111111111110000000000011111111111111111111111110000000000111111111111111", "000000011111111111110000000000011111111111111111111111111000000000111111111111111111111111110000000000011111111111111", "000000011111111111100000000000001111111111111111111111111000000001111111111111011111111111100000000000001111111111111", "000000011111111111100000000000000111111111111011111111111000000011111111111110011111111111100000000000000111111111111", "000000111111111111100000000000000111111111111011111111111100000111111111111100111111111111100000000000000111111111111", "000000111111111111100000000000000111111111111011111111111100000111111111111000111111111111100000000000000111111111111", "000000111111111111000000000000001111111111111001111111111100001111111111110000111111111111100000000000001111111111111", "000000111111111111000000000000001111111111111001111111111110011111111111110000111111111111000000000000001111111111111", "000001111111111111000000000000001111111111110001111111111110111111111111100000111111111111000000000000001111111111111", "000001111111111111000000000000011111111111110000111111111110111111111111000001111111111111000000000000011111111111110", "000001111111111111000000000000111111111111110000111111111111111111111110000001111111111111000000000000111111111111110", "000001111111111110000000000001111111111111100000111111111111111111111100000001111111111110000000000001111111111111100", "000001111111111110000000000111111111111111000000011111111111111111111000000001111111111110000000000111111111111111000", "000011111111111110000000111111111111111110000000011111111111111111110000000011111111111110000000111111111111111110000", "000011111111111111111111111111111111111100000000011111111111111111100000000011111111111111111111111111111111111100000", "000011111111111111111111111111111111111000000000001111111111111111100000000011111111111111111111111111111111111000000", "000011111111111111111111111111111111110000000000001111111111111111000000000011111111111111111111111111111111110000000", "000111111111111111111111111111111111000000000000000111111111111110000000000111111111111111111111111111111111000000000", "000111111111111111111111111111111100000000000000000111111111111100000000000111111111111111111111111111111100000000000", "000111111111111111111111111111100000000000000000000111111111111000000000000111111111111111111111111111100000000000000", "000111111111111111111111111100000000000000000000000011111111110000000000000111111111111111111111111100000000000000000", "000111111111111111111100000000000000000000000000000011111111100000000000000111111111111111111100000000000000000000000", "000000000000000000000000000000000000000000000000000011111111100000000000000000000000000000000000000000000000000000000", "000000000000000000000000000000000000000000000000000001111111000000000000000000000000000000000000000000000000000000000", "000000000000000000000000000000000000000000000000000001111110000000000000000000000000000000000000000000000000000000000", "000000000000000000000000000000000000000000000000000001111100000000000000000000000000000000000000000000000000000000000", "000000000000000000000000000000000000000000000000000000111000000000000000000000000000000000000000000000000000000000000", "000000000000000000000000000000000000000000000000000000110000000000000000000000000000000000000000000000000000000000000", "000000000000000000000000000001111111111111111111111111111111111111111111111111111000000000000000000000000000000000000", "000000000000000000011111111111111111111111111111111111111111111111111111111111111111111111100000000000000000000000000", "000000000000111111111111111111111111111111111111111111111111111111111111111111111111111111111111110000000000000000000", "000000011111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100000000000000", "000011111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110000000000", "011111111111111111111110011111001111111001111111000000011111111100000011111111100000001111111111111111111111100000000", "111111111111111111111110011111001111111001111111001111001111111100111111111111001111100111111111111111111111110000000", "111111111111111111111111001110011111111001111111001111100111111100111111111110011111110011111111111111111111111000000", "111111111111111111111111101100111111111001111111001111100111111100000011111110011111110011111111111111111111111000000", "111111111111111111111111100101111111111001111111001111100111111100111111111110011111110011111111111111111111110000000", "011111111111111111111111110001111111111001111111001111001111111100111111111111001111100111111111111111111111100000000", "000011111111111111111111111011111111111001111111000000011111111100000011111111100000001111111111111111111110000000000", "000000011111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100000000000000", "000000000000111111111111111111111111111111111111111111111111111111111111111111111111111111111111110000000000000000000", "000000000000000000011111111111111111111111111111111111111111111111111111111111111111111111110000000000000000000000000", "000000000000000000000000000001111111111111111111111111111111111111111111111111111100000000000000000000000000000000000" ); constant SPEED : integer := 8; signal position_x : integer range -SPEED to WIDTH + SPEED := 0; signal position_y : integer range -SPEED to HEIGHT + SPEED := 0; signal random_bit : std_logic := '0'; signal color : std_logic_vector(23 downto 0) := x"FFFFFF"; component OSCG is generic ( DIV : integer := 128 ); port ( OSC : out std_logic ); end component; begin char <= 0; background_color <= color when image(py - position_y)(px - position_x) = '1' and px >= position_x and px < position_x + IMAGE_WIDTH and py >= position_y and py < position_y + IMAGE_HEIGHT else x"000000"; foreground_color <= (others => '1'); rng : OSCG port map ( OSC => random_bit ); process(clk) variable old_vsync : std_logic := '0'; variable speed_x : integer range -SPEED to SPEED := SPEED; variable speed_y : integer range -SPEED to SPEED := SPEED; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then if position_x + speed_x + IMAGE_WIDTH >= WIDTH then speed_x := -SPEED; position_x <= WIDTH - IMAGE_WIDTH - 1; color <= color(22 downto 0) & random_bit; elsif position_x + speed_x < 0 then speed_x := SPEED; position_x <= 0; color <= color(22 downto 0) & random_bit; else position_x <= position_x + speed_x; end if; if position_y + speed_y + IMAGE_HEIGHT >= HEIGHT then speed_y := -SPEED; position_y <= HEIGHT - IMAGE_HEIGHT - 1; color <= color(22 downto 0) & random_bit; elsif position_y + speed_y < 0 then speed_y := SPEED; position_y <= 0; color <= color(22 downto 0) & random_bit; else position_y <= position_y + speed_y; end if; end if; old_vsync := vsync; end if; end process; end architecture;

    Success!

    UART Output


    UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%MULT18X18D1283.6%OSCG11100.0%TRELLIS_COMB1447242886.0%TRELLIS_FF180242880.7%TRELLIS_IO101975.1%
    TimingClockAchievedConstraint$glbnet$clkp34.93 MHz25 MHz$glbnet$clkt319.28 MHz250 MHz
    Code

    library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1')
    );
end my_code;

architecture rtl of my_code is
    constant IMAGE_WIDTH : integer := 117;
    constant IMAGE_HEIGHT : integer := 52;

    type image_type is array (0 to IMAGE_HEIGHT-1) of std_logic_vector(0 to IMAGE_WIDTH-1);
    constant image : image_type := (
"000000000111111111111111111111111111111111111111111111000000000000000000011111111111111111111111111111111100000000000",
"000000000111111111111111111111111111111111111111111111000000000000000000111111111111111111111111111111111111100000000",
"000000000111111111111111111111111111111111111111111111000000000000000001111111111111111111111111111111111111111000000",
"000000000111111111111111111111111111111111111111111111100000000000000011111111111111111111111111111111111111111110000",
"000000001111111111111111111111111111111111111111111111100000000000000011111111111111111111111111111111111111111111000",
"000000001111111111111111111111111111111111111111111111100000000000000111111111111111111111111111111111111111111111100",
"000000001111111111111111111111111111111111111111111111110000000000001111111111111111111111111111111111111111111111110",
"000000001111111111110000000111111111111111111111111111110000000000011111111111111111111111110000000111111111111111111",
"000000011111111111110000000000111111111111111111111111110000000000011111111111111111111111110000000000111111111111111",
"000000011111111111110000000000011111111111111111111111111000000000111111111111111111111111110000000000011111111111111",
"000000011111111111100000000000001111111111111111111111111000000001111111111111011111111111100000000000001111111111111",
"000000011111111111100000000000000111111111111011111111111000000011111111111110011111111111100000000000000111111111111",
"000000111111111111100000000000000111111111111011111111111100000111111111111100111111111111100000000000000111111111111",
"000000111111111111100000000000000111111111111011111111111100000111111111111000111111111111100000000000000111111111111",
"000000111111111111000000000000001111111111111001111111111100001111111111110000111111111111100000000000001111111111111",
"000000111111111111000000000000001111111111111001111111111110011111111111110000111111111111000000000000001111111111111",
"000001111111111111000000000000001111111111110001111111111110111111111111100000111111111111000000000000001111111111111",
"000001111111111111000000000000011111111111110000111111111110111111111111000001111111111111000000000000011111111111110",
"000001111111111111000000000000111111111111110000111111111111111111111110000001111111111111000000000000111111111111110",
"000001111111111110000000000001111111111111100000111111111111111111111100000001111111111110000000000001111111111111100",
"000001111111111110000000000111111111111111000000011111111111111111111000000001111111111110000000000111111111111111000",
"000011111111111110000000111111111111111110000000011111111111111111110000000011111111111110000000111111111111111110000",
"000011111111111111111111111111111111111100000000011111111111111111100000000011111111111111111111111111111111111100000",
"000011111111111111111111111111111111111000000000001111111111111111100000000011111111111111111111111111111111111000000",
"000011111111111111111111111111111111110000000000001111111111111111000000000011111111111111111111111111111111110000000",
"000111111111111111111111111111111111000000000000000111111111111110000000000111111111111111111111111111111111000000000",
"000111111111111111111111111111111100000000000000000111111111111100000000000111111111111111111111111111111100000000000",
"000111111111111111111111111111100000000000000000000111111111111000000000000111111111111111111111111111100000000000000",
"000111111111111111111111111100000000000000000000000011111111110000000000000111111111111111111111111100000000000000000",
"000111111111111111111100000000000000000000000000000011111111100000000000000111111111111111111100000000000000000000000",
"000000000000000000000000000000000000000000000000000011111111100000000000000000000000000000000000000000000000000000000",
"000000000000000000000000000000000000000000000000000001111111000000000000000000000000000000000000000000000000000000000",
"000000000000000000000000000000000000000000000000000001111110000000000000000000000000000000000000000000000000000000000",
"000000000000000000000000000000000000000000000000000001111100000000000000000000000000000000000000000000000000000000000",
"000000000000000000000000000000000000000000000000000000111000000000000000000000000000000000000000000000000000000000000",
"000000000000000000000000000000000000000000000000000000110000000000000000000000000000000000000000000000000000000000000",
"000000000000000000000000000001111111111111111111111111111111111111111111111111111000000000000000000000000000000000000",
"000000000000000000011111111111111111111111111111111111111111111111111111111111111111111111100000000000000000000000000",
"000000000000111111111111111111111111111111111111111111111111111111111111111111111111111111111111110000000000000000000",
"000000011111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100000000000000",
"000011111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110000000000",
"011111111111111111111110011111001111111001111111000000011111111100000011111111100000001111111111111111111111100000000",
"111111111111111111111110011111001111111001111111001111001111111100111111111111001111100111111111111111111111110000000",
"111111111111111111111111001110011111111001111111001111100111111100111111111110011111110011111111111111111111111000000",
"111111111111111111111111101100111111111001111111001111100111111100000011111110011111110011111111111111111111111000000",
"111111111111111111111111100101111111111001111111001111100111111100111111111110011111110011111111111111111111110000000",
"011111111111111111111111110001111111111001111111001111001111111100111111111111001111100111111111111111111111100000000",
"000011111111111111111111111011111111111001111111000000011111111100000011111111100000001111111111111111111110000000000",
"000000011111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100000000000000",
"000000000000111111111111111111111111111111111111111111111111111111111111111111111111111111111111110000000000000000000",
"000000000000000000011111111111111111111111111111111111111111111111111111111111111111111111110000000000000000000000000",
"000000000000000000000000000001111111111111111111111111111111111111111111111111111100000000000000000000000000000000000"
    );

    constant SPEED : integer := 8;

    signal position_x : integer range -SPEED to WIDTH + SPEED := 0;
    signal position_y : integer range -SPEED to HEIGHT + SPEED := 0;

    signal random_bit : std_logic := '0';
    signal color : std_logic_vector(23 downto 0) := x"FFFFFF";

    component OSCG is
        generic (
            DIV : integer := 128
        );
        port (
            OSC : out std_logic
        );
    end component;
begin
    char <= 0;

    background_color <= color when image(py - position_y)(px - position_x) = '1' and
            px >= position_x and px < position_x + IMAGE_WIDTH and
            py >= position_y and py < position_y + IMAGE_HEIGHT
        else x"000000";
    foreground_color <= (others => '1');

    rng : OSCG port map (
        OSC => random_bit
    );

    process(clk)
        variable old_vsync : std_logic := '0';
        variable speed_x : integer range -SPEED to SPEED := SPEED;
        variable speed_y : integer range -SPEED to SPEED := SPEED;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                if position_x + speed_x + IMAGE_WIDTH >= WIDTH then
                    speed_x := -SPEED;
                    position_x <= WIDTH - IMAGE_WIDTH - 1;

                    color <= color(22 downto 0) & random_bit;
                elsif position_x + speed_x < 0 then
                    speed_x := SPEED;
                    position_x <= 0;

                    color <= color(22 downto 0) & random_bit;
                else
                    position_x <= position_x + speed_x;
                end if;

                if position_y + speed_y + IMAGE_HEIGHT >= HEIGHT then
                    speed_y := -SPEED;
                    position_y <= HEIGHT - IMAGE_HEIGHT - 1;

                    color <= color(22 downto 0) & random_bit;
                elsif position_y + speed_y < 0 then
                    speed_y := SPEED;
                    position_y <= 0;

                    color <= color(22 downto 0) & random_bit;
                else
                    position_y <= position_y + speed_y;
                end if;
            end if;
            old_vsync := vsync;
        end if;
    end process;
end architecture;


    #FPGA #Icepi-Zero #HDL #VHDL
    #fpga #icepizero #hdl #vhdl
  47. Icepi Zero Bot @[email protected] ·

    @[email protected]

    @[email protected] asked

    library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1') ); end my_code; architecture rtl of my_code is constant IMAGE_WIDTH : integer := 117; constant IMAGE_HEIGHT : integer := 52; type image_type is array (0 to IMAGE_HEIGHT-1) of std_logic_vector(0 to IMAGE_WIDTH-1); constant image : image_type := ( "000000000111111111111111111111111111111111111111111111000000000000000000011111111111111111111111111111111100000000000", "000000000111111111111111111111111111111111111111111111000000000000000000111111111111111111111111111111111111100000000", "000000000111111111111111111111111111111111111111111111000000000000000001111111111111111111111111111111111111111000000", "000000000111111111111111111111111111111111111111111111100000000000000011111111111111111111111111111111111111111110000", "000000001111111111111111111111111111111111111111111111100000000000000011111111111111111111111111111111111111111111000", "000000001111111111111111111111111111111111111111111111100000000000000111111111111111111111111111111111111111111111100", "000000001111111111111111111111111111111111111111111111110000000000001111111111111111111111111111111111111111111111110", "000000001111111111110000000111111111111111111111111111110000000000011111111111111111111111110000000111111111111111111", "000000011111111111110000000000111111111111111111111111110000000000011111111111111111111111110000000000111111111111111", "000000011111111111110000000000011111111111111111111111111000000000111111111111111111111111110000000000011111111111111", "000000011111111111100000000000001111111111111111111111111000000001111111111111011111111111100000000000001111111111111", "000000011111111111100000000000000111111111111011111111111000000011111111111110011111111111100000000000000111111111111", "000000111111111111100000000000000111111111111011111111111100000111111111111100111111111111100000000000000111111111111", "000000111111111111100000000000000111111111111011111111111100000111111111111000111111111111100000000000000111111111111", "000000111111111111000000000000001111111111111001111111111100001111111111110000111111111111100000000000001111111111111", "000000111111111111000000000000001111111111111001111111111110011111111111110000111111111111000000000000001111111111111", "000001111111111111000000000000001111111111110001111111111110111111111111100000111111111111000000000000001111111111111", "000001111111111111000000000000011111111111110000111111111110111111111111000001111111111111000000000000011111111111110", "000001111111111111000000000000111111111111110000111111111111111111111110000001111111111111000000000000111111111111110", "000001111111111110000000000001111111111111100000111111111111111111111100000001111111111110000000000001111111111111100", "000001111111111110000000000111111111111111000000011111111111111111111000000001111111111110000000000111111111111111000", "000011111111111110000000111111111111111110000000011111111111111111110000000011111111111110000000111111111111111110000", "000011111111111111111111111111111111111100000000011111111111111111100000000011111111111111111111111111111111111100000", "000011111111111111111111111111111111111000000000001111111111111111100000000011111111111111111111111111111111111000000", "000011111111111111111111111111111111110000000000001111111111111111000000000011111111111111111111111111111111110000000", "000111111111111111111111111111111111000000000000000111111111111110000000000111111111111111111111111111111111000000000", "000111111111111111111111111111111100000000000000000111111111111100000000000111111111111111111111111111111100000000000", "000111111111111111111111111111100000000000000000000111111111111000000000000111111111111111111111111111100000000000000", "000111111111111111111111111100000000000000000000000011111111110000000000000111111111111111111111111100000000000000000", "000111111111111111111100000000000000000000000000000011111111100000000000000111111111111111111100000000000000000000000", "000000000000000000000000000000000000000000000000000011111111100000000000000000000000000000000000000000000000000000000", "000000000000000000000000000000000000000000000000000001111111000000000000000000000000000000000000000000000000000000000", "000000000000000000000000000000000000000000000000000001111110000000000000000000000000000000000000000000000000000000000", "000000000000000000000000000000000000000000000000000001111100000000000000000000000000000000000000000000000000000000000", "000000000000000000000000000000000000000000000000000000111000000000000000000000000000000000000000000000000000000000000", "000000000000000000000000000000000000000000000000000000110000000000000000000000000000000000000000000000000000000000000", "000000000000000000000000000001111111111111111111111111111111111111111111111111111000000000000000000000000000000000000", "000000000000000000011111111111111111111111111111111111111111111111111111111111111111111111100000000000000000000000000", "000000000000111111111111111111111111111111111111111111111111111111111111111111111111111111111111110000000000000000000", "000000011111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100000000000000", "000011111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110000000000", "011111111111111111111110011111001111111001111111000000011111111100000011111111100000001111111111111111111111100000000", "111111111111111111111110011111001111111001111111001111001111111100111111111111001111100111111111111111111111110000000", "111111111111111111111111001110011111111001111111001111100111111100111111111110011111110011111111111111111111111000000", "111111111111111111111111101100111111111001111111001111100111111100000011111110011111110011111111111111111111111000000", "111111111111111111111111100101111111111001111111001111100111111100111111111110011111110011111111111111111111110000000", "011111111111111111111111110001111111111001111111001111001111111100111111111111001111100111111111111111111111100000000", "000011111111111111111111111011111111111001111111000000011111111100000011111111100000001111111111111111111110000000000", "000000011111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100000000000000", "000000000000111111111111111111111111111111111111111111111111111111111111111111111111111111111111110000000000000000000", "000000000000000000011111111111111111111111111111111111111111111111111111111111111111111111110000000000000000000000000", "000000000000000000000000000001111111111111111111111111111111111111111111111111111100000000000000000000000000000000000" ); constant SPEED : integer := 8; signal position_x : integer range -SPEED to WIDTH + SPEED := 0; signal position_y : integer range -SPEED to HEIGHT + SPEED := 0; signal random_bit : std_logic := '0'; signal color : std_logic_vector(23 downto 0) := x"FFFFFF"; component OSCG is generic ( DIV : integer := 128 ); port ( OSC : out std_logic ); end component; begin char <= 0; background_color <= color when image(py - position_y)(px - position_x) = '1' and px >= position_x and px < position_x + IMAGE_WIDTH and py >= position_y and py < position_y + IMAGE_HEIGHT else x"000000"; foreground_color <= (others => '1'); rng : OSCG port map ( OSC => random_bit ); process(clk) variable old_vsync : std_logic := '0'; variable speed_x : integer range -SPEED to SPEED := SPEED; variable speed_y : integer range -SPEED to SPEED := SPEED; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then if position_x + speed_x + IMAGE_WIDTH >= WIDTH then speed_x := -SPEED; position_x <= WIDTH - IMAGE_WIDTH - 1; color <= color(22 downto 0) & random_bit; elsif position_x + speed_x < 0 then speed_x := SPEED; position_x <= 0; color <= color(22 downto 0) & random_bit; else position_x <= position_x + speed_x; end if; if position_y + speed_y + IMAGE_HEIGHT >= HEIGHT then speed_y := -SPEED; position_y <= HEIGHT - IMAGE_HEIGHT - 1; color <= color(22 downto 0) & random_bit; elsif position_y + speed_y < 0 then speed_y := SPEED; position_y <= 0; color <= color(22 downto 0) & random_bit; else position_y <= position_y + speed_y; end if; end if; old_vsync := vsync; end if; end process; end architecture;

    Success!

    UART Output


    UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%MULT18X18D1283.6%OSCG11100.0%TRELLIS_COMB1447242886.0%TRELLIS_FF180242880.7%TRELLIS_IO101975.1%
    TimingClockAchievedConstraint$glbnet$clkp34.93 MHz25 MHz$glbnet$clkt319.28 MHz250 MHz
    Code

    library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1')
    );
end my_code;

architecture rtl of my_code is
    constant IMAGE_WIDTH : integer := 117;
    constant IMAGE_HEIGHT : integer := 52;

    type image_type is array (0 to IMAGE_HEIGHT-1) of std_logic_vector(0 to IMAGE_WIDTH-1);
    constant image : image_type := (
"000000000111111111111111111111111111111111111111111111000000000000000000011111111111111111111111111111111100000000000",
"000000000111111111111111111111111111111111111111111111000000000000000000111111111111111111111111111111111111100000000",
"000000000111111111111111111111111111111111111111111111000000000000000001111111111111111111111111111111111111111000000",
"000000000111111111111111111111111111111111111111111111100000000000000011111111111111111111111111111111111111111110000",
"000000001111111111111111111111111111111111111111111111100000000000000011111111111111111111111111111111111111111111000",
"000000001111111111111111111111111111111111111111111111100000000000000111111111111111111111111111111111111111111111100",
"000000001111111111111111111111111111111111111111111111110000000000001111111111111111111111111111111111111111111111110",
"000000001111111111110000000111111111111111111111111111110000000000011111111111111111111111110000000111111111111111111",
"000000011111111111110000000000111111111111111111111111110000000000011111111111111111111111110000000000111111111111111",
"000000011111111111110000000000011111111111111111111111111000000000111111111111111111111111110000000000011111111111111",
"000000011111111111100000000000001111111111111111111111111000000001111111111111011111111111100000000000001111111111111",
"000000011111111111100000000000000111111111111011111111111000000011111111111110011111111111100000000000000111111111111",
"000000111111111111100000000000000111111111111011111111111100000111111111111100111111111111100000000000000111111111111",
"000000111111111111100000000000000111111111111011111111111100000111111111111000111111111111100000000000000111111111111",
"000000111111111111000000000000001111111111111001111111111100001111111111110000111111111111100000000000001111111111111",
"000000111111111111000000000000001111111111111001111111111110011111111111110000111111111111000000000000001111111111111",
"000001111111111111000000000000001111111111110001111111111110111111111111100000111111111111000000000000001111111111111",
"000001111111111111000000000000011111111111110000111111111110111111111111000001111111111111000000000000011111111111110",
"000001111111111111000000000000111111111111110000111111111111111111111110000001111111111111000000000000111111111111110",
"000001111111111110000000000001111111111111100000111111111111111111111100000001111111111110000000000001111111111111100",
"000001111111111110000000000111111111111111000000011111111111111111111000000001111111111110000000000111111111111111000",
"000011111111111110000000111111111111111110000000011111111111111111110000000011111111111110000000111111111111111110000",
"000011111111111111111111111111111111111100000000011111111111111111100000000011111111111111111111111111111111111100000",
"000011111111111111111111111111111111111000000000001111111111111111100000000011111111111111111111111111111111111000000",
"000011111111111111111111111111111111110000000000001111111111111111000000000011111111111111111111111111111111110000000",
"000111111111111111111111111111111111000000000000000111111111111110000000000111111111111111111111111111111111000000000",
"000111111111111111111111111111111100000000000000000111111111111100000000000111111111111111111111111111111100000000000",
"000111111111111111111111111111100000000000000000000111111111111000000000000111111111111111111111111111100000000000000",
"000111111111111111111111111100000000000000000000000011111111110000000000000111111111111111111111111100000000000000000",
"000111111111111111111100000000000000000000000000000011111111100000000000000111111111111111111100000000000000000000000",
"000000000000000000000000000000000000000000000000000011111111100000000000000000000000000000000000000000000000000000000",
"000000000000000000000000000000000000000000000000000001111111000000000000000000000000000000000000000000000000000000000",
"000000000000000000000000000000000000000000000000000001111110000000000000000000000000000000000000000000000000000000000",
"000000000000000000000000000000000000000000000000000001111100000000000000000000000000000000000000000000000000000000000",
"000000000000000000000000000000000000000000000000000000111000000000000000000000000000000000000000000000000000000000000",
"000000000000000000000000000000000000000000000000000000110000000000000000000000000000000000000000000000000000000000000",
"000000000000000000000000000001111111111111111111111111111111111111111111111111111000000000000000000000000000000000000",
"000000000000000000011111111111111111111111111111111111111111111111111111111111111111111111100000000000000000000000000",
"000000000000111111111111111111111111111111111111111111111111111111111111111111111111111111111111110000000000000000000",
"000000011111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100000000000000",
"000011111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110000000000",
"011111111111111111111110011111001111111001111111000000011111111100000011111111100000001111111111111111111111100000000",
"111111111111111111111110011111001111111001111111001111001111111100111111111111001111100111111111111111111111110000000",
"111111111111111111111111001110011111111001111111001111100111111100111111111110011111110011111111111111111111111000000",
"111111111111111111111111101100111111111001111111001111100111111100000011111110011111110011111111111111111111111000000",
"111111111111111111111111100101111111111001111111001111100111111100111111111110011111110011111111111111111111110000000",
"011111111111111111111111110001111111111001111111001111001111111100111111111111001111100111111111111111111111100000000",
"000011111111111111111111111011111111111001111111000000011111111100000011111111100000001111111111111111111110000000000",
"000000011111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100000000000000",
"000000000000111111111111111111111111111111111111111111111111111111111111111111111111111111111111110000000000000000000",
"000000000000000000011111111111111111111111111111111111111111111111111111111111111111111111110000000000000000000000000",
"000000000000000000000000000001111111111111111111111111111111111111111111111111111100000000000000000000000000000000000"
    );

    constant SPEED : integer := 8;

    signal position_x : integer range -SPEED to WIDTH + SPEED := 0;
    signal position_y : integer range -SPEED to HEIGHT + SPEED := 0;

    signal random_bit : std_logic := '0';
    signal color : std_logic_vector(23 downto 0) := x"FFFFFF";

    component OSCG is
        generic (
            DIV : integer := 128
        );
        port (
            OSC : out std_logic
        );
    end component;
begin
    char <= 0;

    background_color <= color when image(py - position_y)(px - position_x) = '1' and
            px >= position_x and px < position_x + IMAGE_WIDTH and
            py >= position_y and py < position_y + IMAGE_HEIGHT
        else x"000000";
    foreground_color <= (others => '1');

    rng : OSCG port map (
        OSC => random_bit
    );

    process(clk)
        variable old_vsync : std_logic := '0';
        variable speed_x : integer range -SPEED to SPEED := SPEED;
        variable speed_y : integer range -SPEED to SPEED := SPEED;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                if position_x + speed_x + IMAGE_WIDTH >= WIDTH then
                    speed_x := -SPEED;
                    position_x <= WIDTH - IMAGE_WIDTH - 1;

                    color <= color(22 downto 0) & random_bit;
                elsif position_x + speed_x < 0 then
                    speed_x := SPEED;
                    position_x <= 0;

                    color <= color(22 downto 0) & random_bit;
                else
                    position_x <= position_x + speed_x;
                end if;

                if position_y + speed_y + IMAGE_HEIGHT >= HEIGHT then
                    speed_y := -SPEED;
                    position_y <= HEIGHT - IMAGE_HEIGHT - 1;

                    color <= color(22 downto 0) & random_bit;
                elsif position_y + speed_y < 0 then
                    speed_y := SPEED;
                    position_y <= 0;

                    color <= color(22 downto 0) & random_bit;
                else
                    position_y <= position_y + speed_y;
                end if;
            end if;
            old_vsync := vsync;
        end if;
    end process;
end architecture;


    #FPGA #Icepi-Zero #HDL #VHDL
    #fpga #icepizero #hdl #vhdl
  48. poleguy looking for lost tools @[email protected] ·

    Maybe you'll be my new boss? Come work for #Shure doing #FPGA #modem development in our #Wireless lab.

    I've been here 20 years. It's not bad. Ask me anything.

    careersus-shure.icims.com/jobs

    Put down my name and I'll get a referral bonus.

    #engineering #management #python #verilog #vhdl #proaudio #job #jobs #getfedihired #fedijobs #jobsearch #fedihire #illinois #chicago #askmeanything

    #shure #fpga #modem #wireless #engineering #management
  49. poleguy looking for lost tools @[email protected] ·

    Maybe you'll be my new boss? Come work for #Shure doing #FPGA #modem development in our #Wireless lab.

    I've been here 20 years. It's not bad. Ask me anything.

    careersus-shure.icims.com/jobs

    Put down my name and I'll get a referral bonus.

    #engineering #management #python #verilog #vhdl #proaudio #job #jobs #getfedihired #fedijobs #jobsearch #fedihire #illinois #chicago #askmeanything

    #shure #fpga #modem #wireless #engineering #management
  50. poleguy looking for lost tools @[email protected] ·

    Maybe you'll be my new boss? Come work for #Shure doing #FPGA #modem development in our #Wireless lab.

    I've been here 20 years. It's not bad. Ask me anything.

    careersus-shure.icims.com/jobs

    Put down my name and I'll get a referral bonus.

    #engineering #management #python #verilog #vhdl #proaudio #job #jobs #getfedihired #fedijobs #jobsearch #fedihire #illinois #chicago #askmeanything

    #shure #fpga #modem #wireless #engineering #management