#vhdl — Public Fediverse posts
Live and recent posts from across the Fediverse tagged #vhdl, aggregated by home.social.
-
I found this #VIC20 project repository on #GitHub for the #MEGA65. The xpr files in the CORE directory of the repository seem to be #Xilinx project files. Lacking know how and resources, I can’t turn these into core files for the MEGA 65.
Could some kind soul please do that and upload the core files? I’d love to have a VIC-20 core for the MEGA 65. 🙏
-
ELM11-Feather Is a Feather-Compatible Board That Speaks Lua Natively
#fpga #lua #vhdl
https://itsfoss.com/news/elm11-feather-announcement/ -
I built a browser IDE that runs real open-source EDA tools. Write VHDL or SystemVerilog, hit run: GHDL/Icarus simulates it, Yosys synthesizes it, and you see the waveform and the netlist cell by cell. No install.
Free fundamentals curriculum + engineering-flavored challenges, and a playground.
-
Which Verilog TMDS encoding library do you recommend that I use on the Ice Pi Zero? Here is my review of the options.
-
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1'); uart_data : out std_logic_vector(7 downto 0) := (others => '0'); uart_ready : in std_logic; uart_valid : out std_logic := '0' ); end my_code; architecture rtl of my_code is constant IMAGE_WIDTH : integer := 32; constant IMAGE_HEIGHT : integer := 25; type image_type is array (IMAGE_HEIGHT*IMAGE_WIDTH*12-1 downto 0) of std_logic; constant image : image_type := x"00000000000000000000000000000000000000000000000123400000000000111200000000000000000000000000000000000000000000000000000000000000000000000000044645700000000022344700000000000000000000000000000000000000000000000000000000000000000000000000056845700100000033556800100000000000000000000000000000000000000000000000000000000000000000000000145744611100000034555800000000000000000000000000000000000000000000000000000000000000000000000000033533522423422444633500011075364300000000000000000000000000000000000000000000000000000000000000012334568979b457345123000964eb7da73211100000000000000000000000000000000000000000000000000000000003448abaddadd8ab79a578211c86fa7fa7c86c867430000000000000000000000000000000000000000000000000000005788bcaddadd8ab8ab689777eddebae96f96f9696400000000000000000000000000000000000000000000000011122289a89a9cdadd9aaabb79a777cccca9d85d85b643100000000000000000000000000000000000000000000002217657659aaabcacdaddbcdbcd7ab456888866754532210000000000000000000000000000000000000000000000000332765765789acdadeaddadd9cd58923444522200000011133333300000000000000000000000000000000000000000011154377688978a9bcacd9cc7ac7ad347000000433999bbbddcaaa0000000000000000000000000000000000000000001223443452235679bcabc9bc9ab68b46a124444bbbeddeedddd7770000000000000000000000000000000000000005679bd7ac78b769678cdddeecddacc7ae47a567888cccdddccc8881110000000000001110000000000003333331111115668ab69b89c88a668bcddeecee9bc67b56a99bcccaaa999555111111000000555aaacccbbb333222777eeeeeeccccdddddbbb445abceefeffeeeeeeeeedeedeeddebbcbbcdddeeebbbbbbcccbbb666dddeffdeffffdddccceeedefbdfeffdefbeffff999cccdefadfbefcefdefcefbefbefdeeeefadfbefffffffcefeffcccfffadf4cfdeffffdefeffbdf4cfadf3cf3cfbefeeedddbdf3bf3cf4cf6cf3cf5cf4cf7cfcef4cf4cfdefdff5cfbefdddcccdef3cf9dfdef4cfbdf9df4cf7cf3cf4cf6cfefffffadf4cfadfcef9df4cfdefadf2bf9df4cf3cf8cfdef4cfcefccd888fff9df3bf9cf3af7bf6af5af5af7bfadf3afadffff8cf2bf3bfcefadf3bfadf8cf3bfbdf4bf9cf5bf7bf3afdefbbb444ddddef48f37f47f37f26f58f37f57fbcf89f47fcdf79f79fbdfeffbcf38f6af49f38fabf48fbcf9af27f37feefaaa000aaafff79f37fbcf57f37f8af37f68fccfddf57f89f58f9bfffffffbcf37fddfddf47f57f47fbcfddf37f47ffff999000344eeeddfbcfeffddfcdfdefabfeefffffffdefeefddfeefddeccdddf9afeeffffddfddfddfeeffffbcfbcffff77800000099aeeeeeeddeddeddeeeeeefdee89abbcddeccdddddde99a99aeeffffeefdddeeeddeddeccdcddeeefffddd45600000022456866845745745755767956822423544723534645723433477978a679446567457446346346568679558112"; constant SPEED : integer := 8; signal position_x : integer range -SPEED to WIDTH + SPEED := 0; signal position_y : integer range -SPEED to HEIGHT + SPEED := 0; signal random_bit : std_logic := '0'; signal color : std_logic_vector(23 downto 0) := x"FFFFFF"; component OSCG is generic ( DIV : integer := 128 ); port ( OSC : out std_logic ); end component; signal pos : integer range 0 to IMAGE_HEIGHT*IMAGE_WIDTH*12; signal r, g, b : std_logic_vector(3 downto 0); begin char <= 0; pos <= IMAGE_HEIGHT*IMAGE_WIDTH*12 - 1 - 12*(py - position_y)*(px - position_x); r <= image(pos) & image(pos - 1) & image(pos - 2) & image(pos - 3); g <= image(pos - 4) & image(pos - 5) & image(pos - 6) & image(pos - 7); b <= image(pos - 8) & image(pos - 9) & image(pos - 10) & image(pos - 11); background_color <= r & r & g & g & b & b when px >= position_x and px < position_x + IMAGE_WIDTH and py >= position_y and py < position_y + IMAGE_HEIGHT else x"000000"; foreground_color <= (others => '1'); rng : OSCG port map ( OSC => random_bit ); process(clk) variable old_vsync : std_logic := '0'; variable speed_x : integer range -SPEED to SPEED := SPEED; variable speed_y : integer range -SPEED to SPEED := SPEED; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then if position_x + speed_x + IMAGE_WIDTH >= WIDTH then speed_x := -SPEED; position_x <= WIDTH - IMAGE_WIDTH - 1; color <= color(22 downto 0) & random_bit; elsif position_x + speed_x < 0 then speed_x := SPEED; position_x <= 0; color <= color(22 downto 0) & random_bit; else position_x <= position_x + speed_x; end if; if position_y + speed_y + IMAGE_HEIGHT >= HEIGHT then speed_y := -SPEED; position_y <= HEIGHT - IMAGE_HEIGHT - 1; color <= color(22 downto 0) & random_bit; elsif position_y + speed_y < 0 then speed_y := SPEED; position_y <= 0; color <= color(22 downto 0) & random_bit; else position_y <= position_y + speed_y; end if; end if; old_vsync := vsync; end if; end process; end architecture;
Success!
UART Output
UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%MULT18X18D2287.1%TRELLIS_COMB29372428812.1%TRELLIS_FF160242880.7%TRELLIS_IO111975.6%
TimingClockAchievedConstraint$glbnet$clkp30.03 MHz25 MHz$glbnet$clkt341.41 MHz250 MHz
Codelibrary ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1'); uart_data : out std_logic_vector(7 downto 0) := (others => '0'); uart_ready : in std_logic; uart_valid : out std_logic := '0' ); end my_code; architecture rtl of my_code is constant IMAGE_WIDTH : integer := 32; constant IMAGE_HEIGHT : integer := 25; type image_type is array (IMAGE_HEIGHT*IMAGE_WIDTH*12-1 downto 0) of std_logic; constant image : image_type := x"00000000000000000000000000000000000000000000000123400000000000111200000000000000000000000000000000000000000000000000000000000000000000000000044645700000000022344700000000000000000000000000000000000000000000000000000000000000000000000000056845700100000033556800100000000000000000000000000000000000000000000000000000000000000000000000145744611100000034555800000000000000000000000000000000000000000000000000000000000000000000000000033533522423422444633500011075364300000000000000000000000000000000000000000000000000000000000000012334568979b457345123000964eb7da73211100000000000000000000000000000000000000000000000000000000003448abaddadd8ab79a578211c86fa7fa7c86c867430000000000000000000000000000000000000000000000000000005788bcaddadd8ab8ab689777eddebae96f96f9696400000000000000000000000000000000000000000000000011122289a89a9cdadd9aaabb79a777cccca9d85d85b643100000000000000000000000000000000000000000000002217657659aaabcacdaddbcdbcd7ab456888866754532210000000000000000000000000000000000000000000000000332765765789acdadeaddadd9cd58923444522200000011133333300000000000000000000000000000000000000000011154377688978a9bcacd9cc7ac7ad347000000433999bbbddcaaa0000000000000000000000000000000000000000001223443452235679bcabc9bc9ab68b46a124444bbbeddeedddd7770000000000000000000000000000000000000005679bd7ac78b769678cdddeecddacc7ae47a567888cccdddccc8881110000000000001110000000000003333331111115668ab69b89c88a668bcddeecee9bc67b56a99bcccaaa999555111111000000555aaacccbbb333222777eeeeeeccccdddddbbb445abceefeffeeeeeeeeedeedeeddebbcbbcdddeeebbbbbbcccbbb666dddeffdeffffdddccceeedefbdfeffdefbeffff999cccdefadfbefcefdefcefbefbefdeeeefadfbefffffffcefeffcccfffadf4cfdeffffdefeffbdf4cfadf3cf3cfbefeeedddbdf3bf3cf4cf6cf3cf5cf4cf7cfcef4cf4cfdefdff5cfbefdddcccdef3cf9dfdef4cfbdf9df4cf7cf3cf4cf6cfefffffadf4cfadfcef9df4cfdefadf2bf9df4cf3cf8cfdef4cfcefccd888fff9df3bf9cf3af7bf6af5af5af7bfadf3afadffff8cf2bf3bfcefadf3bfadf8cf3bfbdf4bf9cf5bf7bf3afdefbbb444ddddef48f37f47f37f26f58f37f57fbcf89f47fcdf79f79fbdfeffbcf38f6af49f38fabf48fbcf9af27f37feefaaa000aaafff79f37fbcf57f37f8af37f68fccfddf57f89f58f9bfffffffbcf37fddfddf47f57f47fbcfddf37f47ffff999000344eeeddfbcfeffddfcdfdefabfeefffffffdefeefddfeefddeccdddf9afeeffffddfddfddfeeffffbcfbcffff77800000099aeeeeeeddeddeddeeeeeefdee89abbcddeccdddddde99a99aeeffffeefdddeeeddeddeccdcddeeefffddd45600000022456866845745745755767956822423544723534645723433477978a679446567457446346346568679558112"; constant SPEED : integer := 8; signal position_x : integer range -SPEED to WIDTH + SPEED := 0; signal position_y : integer range -SPEED to HEIGHT + SPEED := 0; signal random_bit : std_logic := '0'; signal color : std_logic_vector(23 downto 0) := x"FFFFFF"; component OSCG is generic ( DIV : integer := 128 ); port ( OSC : out std_logic ); end component; signal pos : integer range 0 to IMAGE_HEIGHT*IMAGE_WIDTH*12; signal r, g, b : std_logic_vector(3 downto 0); begin char <= 0; pos <= IMAGE_HEIGHT*IMAGE_WIDTH*12 - 1 - 12*(py - position_y)*(px - position_x); r <= image(pos) & image(pos - 1) & image(pos - 2) & image(pos - 3); g <= image(pos - 4) & image(pos - 5) & image(pos - 6) & image(pos - 7); b <= image(pos - 8) & image(pos - 9) & image(pos - 10) & image(pos - 11); background_color <= r & r & g & g & b & b when px >= position_x and px < position_x + IMAGE_WIDTH and py >= position_y and py < position_y + IMAGE_HEIGHT else x"000000"; foreground_color <= (others => '1'); rng : OSCG port map ( OSC => random_bit ); process(clk) variable old_vsync : std_logic := '0'; variable speed_x : integer range -SPEED to SPEED := SPEED; variable speed_y : integer range -SPEED to SPEED := SPEED; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then if position_x + speed_x + IMAGE_WIDTH >= WIDTH then speed_x := -SPEED; position_x <= WIDTH - IMAGE_WIDTH - 1; color <= color(22 downto 0) & random_bit; elsif position_x + speed_x < 0 then speed_x := SPEED; position_x <= 0; color <= color(22 downto 0) & random_bit; else position_x <= position_x + speed_x; end if; if position_y + speed_y + IMAGE_HEIGHT >= HEIGHT then speed_y := -SPEED; position_y <= HEIGHT - IMAGE_HEIGHT - 1; color <= color(22 downto 0) & random_bit; elsif position_y + speed_y < 0 then speed_y := SPEED; position_y <= 0; color <= color(22 downto 0) & random_bit; else position_y <= position_y + speed_y; end if; end if; old_vsync := vsync; end if; end process; end architecture;
#FPGA #Icepi-Zero #HDL #VHDL -
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1') ); end my_code; architecture rtl of my_code is constant IMAGE_WIDTH : integer := 117; constant IMAGE_HEIGHT : integer := 52; type image_type is array (0 to IMAGE_HEIGHT-1) of std_logic_vector(0 to IMAGE_WIDTH-1); constant image : image_type := ( "000000000111111111111111111111111111111111111111111111000000000000000000011111111111111111111111111111111100000000000", "000000000111111111111111111111111111111111111111111111000000000000000000111111111111111111111111111111111111100000000", "000000000111111111111111111111111111111111111111111111000000000000000001111111111111111111111111111111111111111000000", "000000000111111111111111111111111111111111111111111111100000000000000011111111111111111111111111111111111111111110000", "000000001111111111111111111111111111111111111111111111100000000000000011111111111111111111111111111111111111111111000", "000000001111111111111111111111111111111111111111111111100000000000000111111111111111111111111111111111111111111111100", "000000001111111111111111111111111111111111111111111111110000000000001111111111111111111111111111111111111111111111110", "000000001111111111110000000111111111111111111111111111110000000000011111111111111111111111110000000111111111111111111", "000000011111111111110000000000111111111111111111111111110000000000011111111111111111111111110000000000111111111111111", "000000011111111111110000000000011111111111111111111111111000000000111111111111111111111111110000000000011111111111111", "000000011111111111100000000000001111111111111111111111111000000001111111111111011111111111100000000000001111111111111", "000000011111111111100000000000000111111111111011111111111000000011111111111110011111111111100000000000000111111111111", "000000111111111111100000000000000111111111111011111111111100000111111111111100111111111111100000000000000111111111111", "000000111111111111100000000000000111111111111011111111111100000111111111111000111111111111100000000000000111111111111", "000000111111111111000000000000001111111111111001111111111100001111111111110000111111111111100000000000001111111111111", "000000111111111111000000000000001111111111111001111111111110011111111111110000111111111111000000000000001111111111111", "000001111111111111000000000000001111111111110001111111111110111111111111100000111111111111000000000000001111111111111", "000001111111111111000000000000011111111111110000111111111110111111111111000001111111111111000000000000011111111111110", "000001111111111111000000000000111111111111110000111111111111111111111110000001111111111111000000000000111111111111110", "000001111111111110000000000001111111111111100000111111111111111111111100000001111111111110000000000001111111111111100", "000001111111111110000000000111111111111111000000011111111111111111111000000001111111111110000000000111111111111111000", "000011111111111110000000111111111111111110000000011111111111111111110000000011111111111110000000111111111111111110000", "000011111111111111111111111111111111111100000000011111111111111111100000000011111111111111111111111111111111111100000", "000011111111111111111111111111111111111000000000001111111111111111100000000011111111111111111111111111111111111000000", "000011111111111111111111111111111111110000000000001111111111111111000000000011111111111111111111111111111111110000000", "000111111111111111111111111111111111000000000000000111111111111110000000000111111111111111111111111111111111000000000", "000111111111111111111111111111111100000000000000000111111111111100000000000111111111111111111111111111111100000000000", "000111111111111111111111111111100000000000000000000111111111111000000000000111111111111111111111111111100000000000000", "000111111111111111111111111100000000000000000000000011111111110000000000000111111111111111111111111100000000000000000", "000111111111111111111100000000000000000000000000000011111111100000000000000111111111111111111100000000000000000000000", "000000000000000000000000000000000000000000000000000011111111100000000000000000000000000000000000000000000000000000000", "000000000000000000000000000000000000000000000000000001111111000000000000000000000000000000000000000000000000000000000", "000000000000000000000000000000000000000000000000000001111110000000000000000000000000000000000000000000000000000000000", "000000000000000000000000000000000000000000000000000001111100000000000000000000000000000000000000000000000000000000000", "000000000000000000000000000000000000000000000000000000111000000000000000000000000000000000000000000000000000000000000", "000000000000000000000000000000000000000000000000000000110000000000000000000000000000000000000000000000000000000000000", "000000000000000000000000000001111111111111111111111111111111111111111111111111111000000000000000000000000000000000000", "000000000000000000011111111111111111111111111111111111111111111111111111111111111111111111100000000000000000000000000", "000000000000111111111111111111111111111111111111111111111111111111111111111111111111111111111111110000000000000000000", "000000011111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100000000000000", "000011111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110000000000", "011111111111111111111110011111001111111001111111000000011111111100000011111111100000001111111111111111111111100000000", "111111111111111111111110011111001111111001111111001111001111111100111111111111001111100111111111111111111111110000000", "111111111111111111111111001110011111111001111111001111100111111100111111111110011111110011111111111111111111111000000", "111111111111111111111111101100111111111001111111001111100111111100000011111110011111110011111111111111111111111000000", "111111111111111111111111100101111111111001111111001111100111111100111111111110011111110011111111111111111111110000000", "011111111111111111111111110001111111111001111111001111001111111100111111111111001111100111111111111111111111100000000", "000011111111111111111111111011111111111001111111000000011111111100000011111111100000001111111111111111111110000000000", "000000011111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100000000000000", "000000000000111111111111111111111111111111111111111111111111111111111111111111111111111111111111110000000000000000000", "000000000000000000011111111111111111111111111111111111111111111111111111111111111111111111110000000000000000000000000", "000000000000000000000000000001111111111111111111111111111111111111111111111111111100000000000000000000000000000000000" ); constant SPEED : integer := 8; signal position_x : integer range -SPEED to WIDTH + SPEED := 0; signal position_y : integer range -SPEED to HEIGHT + SPEED := 0; signal random_bit : std_logic := '0'; signal color : std_logic_vector(23 downto 0) := x"FFFFFF"; component OSCG is generic ( DIV : integer := 128 ); port ( OSC : out std_logic ); end component; begin char <= 0; background_color <= color when image(py - position_y)(px - position_x) = '1' and px >= position_x and px < position_x + IMAGE_WIDTH and py >= position_y and py < position_y + IMAGE_HEIGHT else x"000000"; foreground_color <= (others => '1'); rng : OSCG port map ( OSC => random_bit ); process(clk) variable old_vsync : std_logic := '0'; variable speed_x : integer range -SPEED to SPEED := SPEED; variable speed_y : integer range -SPEED to SPEED := SPEED; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then if position_x + speed_x + IMAGE_WIDTH >= WIDTH then speed_x := -SPEED; position_x <= WIDTH - IMAGE_WIDTH - 1; color <= color(22 downto 0) & random_bit; elsif position_x + speed_x < 0 then speed_x := SPEED; position_x <= 0; color <= color(22 downto 0) & random_bit; else position_x <= position_x + speed_x; end if; if position_y + speed_y + IMAGE_HEIGHT >= HEIGHT then speed_y := -SPEED; position_y <= HEIGHT - IMAGE_HEIGHT - 1; color <= color(22 downto 0) & random_bit; elsif position_y + speed_y < 0 then speed_y := SPEED; position_y <= 0; color <= color(22 downto 0) & random_bit; else position_y <= position_y + speed_y; end if; end if; old_vsync := vsync; end if; end process; end architecture;
Success!
UART Output
UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%MULT18X18D1283.6%OSCG11100.0%TRELLIS_COMB1447242886.0%TRELLIS_FF180242880.7%TRELLIS_IO101975.1%
TimingClockAchievedConstraint$glbnet$clkp34.93 MHz25 MHz$glbnet$clkt319.28 MHz250 MHz
Codelibrary ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1') ); end my_code; architecture rtl of my_code is constant IMAGE_WIDTH : integer := 117; constant IMAGE_HEIGHT : integer := 52; type image_type is array (0 to IMAGE_HEIGHT-1) of std_logic_vector(0 to IMAGE_WIDTH-1); constant image : image_type := ( "000000000111111111111111111111111111111111111111111111000000000000000000011111111111111111111111111111111100000000000", "000000000111111111111111111111111111111111111111111111000000000000000000111111111111111111111111111111111111100000000", "000000000111111111111111111111111111111111111111111111000000000000000001111111111111111111111111111111111111111000000", "000000000111111111111111111111111111111111111111111111100000000000000011111111111111111111111111111111111111111110000", "000000001111111111111111111111111111111111111111111111100000000000000011111111111111111111111111111111111111111111000", "000000001111111111111111111111111111111111111111111111100000000000000111111111111111111111111111111111111111111111100", "000000001111111111111111111111111111111111111111111111110000000000001111111111111111111111111111111111111111111111110", "000000001111111111110000000111111111111111111111111111110000000000011111111111111111111111110000000111111111111111111", "000000011111111111110000000000111111111111111111111111110000000000011111111111111111111111110000000000111111111111111", "000000011111111111110000000000011111111111111111111111111000000000111111111111111111111111110000000000011111111111111", "000000011111111111100000000000001111111111111111111111111000000001111111111111011111111111100000000000001111111111111", "000000011111111111100000000000000111111111111011111111111000000011111111111110011111111111100000000000000111111111111", "000000111111111111100000000000000111111111111011111111111100000111111111111100111111111111100000000000000111111111111", "000000111111111111100000000000000111111111111011111111111100000111111111111000111111111111100000000000000111111111111", "000000111111111111000000000000001111111111111001111111111100001111111111110000111111111111100000000000001111111111111", "000000111111111111000000000000001111111111111001111111111110011111111111110000111111111111000000000000001111111111111", "000001111111111111000000000000001111111111110001111111111110111111111111100000111111111111000000000000001111111111111", "000001111111111111000000000000011111111111110000111111111110111111111111000001111111111111000000000000011111111111110", "000001111111111111000000000000111111111111110000111111111111111111111110000001111111111111000000000000111111111111110", "000001111111111110000000000001111111111111100000111111111111111111111100000001111111111110000000000001111111111111100", "000001111111111110000000000111111111111111000000011111111111111111111000000001111111111110000000000111111111111111000", "000011111111111110000000111111111111111110000000011111111111111111110000000011111111111110000000111111111111111110000", "000011111111111111111111111111111111111100000000011111111111111111100000000011111111111111111111111111111111111100000", "000011111111111111111111111111111111111000000000001111111111111111100000000011111111111111111111111111111111111000000", "000011111111111111111111111111111111110000000000001111111111111111000000000011111111111111111111111111111111110000000", "000111111111111111111111111111111111000000000000000111111111111110000000000111111111111111111111111111111111000000000", "000111111111111111111111111111111100000000000000000111111111111100000000000111111111111111111111111111111100000000000", "000111111111111111111111111111100000000000000000000111111111111000000000000111111111111111111111111111100000000000000", "000111111111111111111111111100000000000000000000000011111111110000000000000111111111111111111111111100000000000000000", "000111111111111111111100000000000000000000000000000011111111100000000000000111111111111111111100000000000000000000000", "000000000000000000000000000000000000000000000000000011111111100000000000000000000000000000000000000000000000000000000", "000000000000000000000000000000000000000000000000000001111111000000000000000000000000000000000000000000000000000000000", "000000000000000000000000000000000000000000000000000001111110000000000000000000000000000000000000000000000000000000000", "000000000000000000000000000000000000000000000000000001111100000000000000000000000000000000000000000000000000000000000", "000000000000000000000000000000000000000000000000000000111000000000000000000000000000000000000000000000000000000000000", "000000000000000000000000000000000000000000000000000000110000000000000000000000000000000000000000000000000000000000000", "000000000000000000000000000001111111111111111111111111111111111111111111111111111000000000000000000000000000000000000", "000000000000000000011111111111111111111111111111111111111111111111111111111111111111111111100000000000000000000000000", "000000000000111111111111111111111111111111111111111111111111111111111111111111111111111111111111110000000000000000000", "000000011111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100000000000000", "000011111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110000000000", "011111111111111111111110011111001111111001111111000000011111111100000011111111100000001111111111111111111111100000000", "111111111111111111111110011111001111111001111111001111001111111100111111111111001111100111111111111111111111110000000", "111111111111111111111111001110011111111001111111001111100111111100111111111110011111110011111111111111111111111000000", "111111111111111111111111101100111111111001111111001111100111111100000011111110011111110011111111111111111111111000000", "111111111111111111111111100101111111111001111111001111100111111100111111111110011111110011111111111111111111110000000", "011111111111111111111111110001111111111001111111001111001111111100111111111111001111100111111111111111111111100000000", "000011111111111111111111111011111111111001111111000000011111111100000011111111100000001111111111111111111110000000000", "000000011111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100000000000000", "000000000000111111111111111111111111111111111111111111111111111111111111111111111111111111111111110000000000000000000", "000000000000000000011111111111111111111111111111111111111111111111111111111111111111111111110000000000000000000000000", "000000000000000000000000000001111111111111111111111111111111111111111111111111111100000000000000000000000000000000000" ); constant SPEED : integer := 8; signal position_x : integer range -SPEED to WIDTH + SPEED := 0; signal position_y : integer range -SPEED to HEIGHT + SPEED := 0; signal random_bit : std_logic := '0'; signal color : std_logic_vector(23 downto 0) := x"FFFFFF"; component OSCG is generic ( DIV : integer := 128 ); port ( OSC : out std_logic ); end component; begin char <= 0; background_color <= color when image(py - position_y)(px - position_x) = '1' and px >= position_x and px < position_x + IMAGE_WIDTH and py >= position_y and py < position_y + IMAGE_HEIGHT else x"000000"; foreground_color <= (others => '1'); rng : OSCG port map ( OSC => random_bit ); process(clk) variable old_vsync : std_logic := '0'; variable speed_x : integer range -SPEED to SPEED := SPEED; variable speed_y : integer range -SPEED to SPEED := SPEED; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then if position_x + speed_x + IMAGE_WIDTH >= WIDTH then speed_x := -SPEED; position_x <= WIDTH - IMAGE_WIDTH - 1; color <= color(22 downto 0) & random_bit; elsif position_x + speed_x < 0 then speed_x := SPEED; position_x <= 0; color <= color(22 downto 0) & random_bit; else position_x <= position_x + speed_x; end if; if position_y + speed_y + IMAGE_HEIGHT >= HEIGHT then speed_y := -SPEED; position_y <= HEIGHT - IMAGE_HEIGHT - 1; color <= color(22 downto 0) & random_bit; elsif position_y + speed_y < 0 then speed_y := SPEED; position_y <= 0; color <= color(22 downto 0) & random_bit; else position_y <= position_y + speed_y; end if; end if; old_vsync := vsync; end if; end process; end architecture;
#FPGA #Icepi-Zero #HDL #VHDL -
Maybe you'll be my new boss? Come work for #Shure doing #FPGA #modem development in our #Wireless lab.
I've been here 20 years. It's not bad. Ask me anything.
https://careersus-shure.icims.com/jobs/4766/engineer-staff-managing%2c-fpga/job?mode=view
Put down my name and I'll get a referral bonus.
#engineering #management #python #verilog #vhdl #proaudio #job #jobs #getfedihired #fedijobs #jobsearch #fedihire #illinois #chicago #askmeanything
-
Перепрыгивание с языка на язык как тактика прохождения интервью
В 2010 году я участвовал в интервьировании на позицию по моделированию и верификации процессорных ядер. Один из кандидатов был благообразный седой американец, который до этого работал в IBM. Я задал вопрос про язык описания и верификации аппаратуры SystemVerilog. На это кандидат сказал, что он еще не освоил SystemVerilog, вписал его в резюме на будущее, но вообще использовал Verilog-95 и немного Verilog-2001. “Нет проблем”, - сказал я и задал вопрос по Verilog-95: “приведите примеры гонок (race conditions) при испрользовании верилога”. На это кандидат сказал, что вообще его опыт был больше связан с VHDL. “Блин, как он выкрутился” - подумал я, ведь в VHDL нет гонок как в верилоге из-за дизайна языка.
https://habr.com/ru/articles/1033360/
#SystemVerilog #verilog #Ada #VHDL #Jovial #Coral66 #IBM #Стенфорд #вопросы_на_собеседовании #внешний_вид
-
Ah, the "crown jewel" of VHDL: a riveting exploration into #determinism so compelling, it'll have you questioning if watching paint dry is more thrilling. 🤦♂️🤷♀️ Dive into an endless loop of corporate jargon and existential delta cycles, because who needs excitement when you have VHDL? ⚙️🛠️
https://www.sigasi.com/opinion/jan/vhdls-crown-jewel/ #VHDL #CorporateJargon #ExistentialCycles #TechHumor #ProgrammingFun #HackerNews #ngated -
Fun in the frequency domain 🤓 Camera pointed at it's own display also showing audio FFT for cool glitchy visualizer effect. Video processing all done in PipelineC hardware. And how?
https://github.com/JulianKemmerer/PipelineC/wiki/Example:-Video-Pipelines
#hardware #fpga #dsp #rtl #hdl #hls #verilog #vhdl #pipelinec
-
SystemLisp - an HDL simulator written in Common Lisp
#lisp #commonlisp #hdl #rtl #verilog #design #verification #vhdl #systemverilog #vlsi #programming #fpga
-
Выступил отрицателем AI на конференции SNUG Silicon Valley
AI - не микроархитектор, не проектировщик и не верификатор. Это все-лишь гламурный поисковик уже решенных и опубликованных задач. Именно такой вывод следовал из предоставленных мною на конференции SNUG Silicon Valley 2026 фактов как десятки студентов мучали ИИ чтобы решить мои задачки. Одну задачку ИИ решил лишь через полгода после выкладывания решений в интернет, другую за два месяца, потом пошла третья. При этом задачки были довольно банальные - мы в Самсунге даем делать такие статические конвейеры с контролем потока данных практикантам. Вот постер, сопровождающий мою статью:
https://habr.com/ru/articles/1010978/
#SNUG #Synopsys #Silicon_Valley #школа_синтеза_цифровых_схем #SystemVerilog #ASIC #FPGA #Samsung #задачи_на_собеседованиях #VHDL
-
AERIS-10 open-source hardware radar can track multiple objects up to 20km away
-
@nlnetlabs.bsky.social NLnet Foundation funded open source WireGuard router in FPGA. Featuring PipelineC for cryptography blocks 🤓 github.com/JulianKemmer... #hardware #fpga #rtl #hdl #hls #verilog #vhdl #cryptography #wireguard #pipelinec
-
@nlnet NLnet Foundation funded open source WireGuard router in FPGA. Featuring PipelineC for cryptography blocks 🤓
https://github.com/JulianKemmerer/PipelineC/wiki/Example:-ChaCha20%E2%80%90Poly1305-for-WireGuard
#hardware #fpga #rtl #hdl #hls #verilog #vhdl #cryptography #wireguard #pipelinec
-
PipelineC holds the throughput lead on Latchup.app. For now! How does your design stack up against a pipelining tool? Far too time consuming and fun of a site 🤓 Look forward to seeing competing solutions.
https://github.com/JulianKemmerer/PipelineC/wiki/Example:-Latchup-Solutions
-
Start rtl counter with a timer that is initialized 10 seconds from a 32bit wrap point so that the software handling of wrap-around is well exercised during development.
#rtl #fpga #verilog #vhdl #xilinx #alchitry #eureka #protonpack #software #softwaredevelopment #hardware #embedded #fensterFreitag
-
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1') ); end my_code; architecture rtl of my_code is alias bg_red : std_logic_vector(7 downto 0) is background_color(23 downto 16); alias bg_green : std_logic_vector(7 downto 0) is background_color(15 downto 8); alias bg_blue : std_logic_vector(7 downto 0) is background_color(7 downto 0); signal frame_counter : unsigned(31 downto 0) := (others => '0'); -- Aquarium title constant title_text : string(1 to 28) := "~~ Tiny VHDL Aquarium! ~~ <3"; constant title_row : integer := 1; constant title_col : integer := 26; -- Fish 1: ><> constant fish1 : string(1 to 3) := "><>"; constant fish1_row : integer := 10; -- Fish 2: <>< (facing left) constant fish2 : string(1 to 3) := "<><"; constant fish2_row : integer := 20; -- Fish 3: ><))'> constant fish3 : string(1 to 6) := "><))'>"; constant fish3_row : integer := 30; -- Fish 4: <'((<> constant fish4 : string(1 to 6) := "<'((<>"; constant fish4_row : integer := 40; -- Bubbles column constant bubble_col : integer := 5; -- Seaweed constant weed_row_start : integer := 50; -- Crab at bottom constant crab_text : string(1 to 5) := "V(..)"; constant crab_row : integer := 57; constant crab_col : integer := 38; signal fish1_col : integer range 0 to CONSOLE_COLUMNS - 1 := 0; signal fish2_col : integer range 0 to CONSOLE_COLUMNS - 1 := 70; signal fish3_col : integer range 0 to CONSOLE_COLUMNS - 1 := 0; signal fish4_col : integer range 0 to CONSOLE_COLUMNS - 1 := 60; signal bubble_phase : unsigned(5 downto 0) := (others => '0'); signal char_out : integer range 0 to 127 := 0; -- Helper function: modulo for column wrapping function wrap_col(val : integer; max_val : integer) return integer is begin return val mod max_val; end function; begin -- Frame counter & animation process(clk) variable old_vsync : std_logic := '0'; variable fc_local : unsigned(31 downto 0) := (others => '0'); begin if rising_edge(clk) then if rst = '1' then frame_counter <= (others => '0'); fish1_col <= 0; fish2_col <= 70; fish3_col <= 0; fish4_col <= 60; bubble_phase <= (others => '0'); elsif vsync = '0' and old_vsync = '1' then frame_counter <= frame_counter + 1; -- Move fish every 8 frames for a gentle swim if frame_counter(2 downto 0) = "000" then -- Fish 1 swims right if fish1_col < CONSOLE_COLUMNS - 1 then fish1_col <= fish1_col + 1; else fish1_col <= 0; end if; -- Fish 3 swims right (slower, updates every 16 frames via extra bit) if frame_counter(3) = '1' then if fish3_col < CONSOLE_COLUMNS - 1 then fish3_col <= fish3_col + 1; else fish3_col <= 0; end if; end if; -- Fish 2 swims left if fish2_col > 0 then fish2_col <= fish2_col - 1; else fish2_col <= CONSOLE_COLUMNS - 1; end if; -- Fish 4 swims left if fish4_col > 0 then fish4_col <= fish4_col - 1; else fish4_col <= CONSOLE_COLUMNS - 1; end if; bubble_phase <= bubble_phase + 1; end if; end if; old_vsync := vsync; end if; end process; -- Character output logic process(col, row, fish1_col, fish2_col, fish3_col, fish4_col, frame_counter, bubble_phase) variable c : integer range 0 to 127 := 0; variable rel : integer; variable bub_row : integer; begin c := 0; -- default: space -- Title if row = title_row and col >= title_col and col < title_col + title_text'length then rel := col - title_col + 1; if rel >= 1 and rel <= title_text'length then c := character'pos(title_text(rel)); end if; -- Fish 1: ><> swimming right elsif row = fish1_row and col >= fish1_col and col < fish1_col + fish1'length then rel := col - fish1_col + 1; if rel >= 1 and rel <= fish1'length then c := character'pos(fish1(rel)); end if; -- Fish 2: <>< swimming left elsif row = fish2_row and col >= fish2_col and col < fish2_col + fish2'length then rel := col - fish2_col + 1; if rel >= 1 and rel <= fish2'length then c := character'pos(fish2(rel)); end if; -- Fish 3: ><))'> swimming right elsif row = fish3_row and col >= fish3_col and col < fish3_col + fish3'length then rel := col - fish3_col + 1; if rel >= 1 and rel <= fish3'length then c := character'pos(fish3(rel)); end if; -- Fish 4: <'((<> swimming left elsif row = fish4_row and col >= fish4_col and col < fish4_col + fish4'length then rel := col - fish4_col + 1; if rel >= 1 and rel <= fish4'length then c := character'pos(fish4(rel)); end if; -- Crab at bottom elsif row = crab_row and col >= crab_col and col < crab_col + crab_text'length then rel := col - crab_col + 1; if rel >= 1 and rel <= crab_text'length then c := character'pos(crab_text(rel)); end if; -- Bubbles: 'o' rising in a column, 3 bubbles spaced apart, shifting upward elsif col = bubble_col or col = bubble_col + 30 or col = bubble_col + 55 then bub_row := to_integer(bubble_phase); if row = (CONSOLE_ROWS - 5 - (bub_row mod (CONSOLE_ROWS - 6))) or row = (CONSOLE_ROWS - 5 - ((bub_row + 12) mod (CONSOLE_ROWS - 6))) or row = (CONSOLE_ROWS - 5 - ((bub_row + 24) mod (CONSOLE_ROWS - 6))) then c := character'pos('o'); end if; -- Seaweed at the bottom: alternating | and ( depending on frame for sway elsif row >= weed_row_start and row <= CONSOLE_ROWS - 2 then if col = 10 or col = 20 or col = 35 or col = 50 or col = 65 or col = 75 then if frame_counter(4) = '0' then c := character'pos('('); else c := character'pos(')'); end if; end if; -- Sandy bottom elsif row = CONSOLE_ROWS - 1 then if (col mod 3) = 0 then c := character'pos('.'); elsif (col mod 3) = 1 then c := character'pos(','); else c := character'pos('_'); end if; -- Water surface elsif row = 0 then if frame_counter(3) = '0' then c := character'pos('~'); else c := character'pos('-'); end if; end if; char_out <= c; end process; char <= char_out; -- Background: deep ocean gradient (dark blue, getting darker toward bottom) process(row, col, frame_counter, py) variable depth_blue : unsigned(7 downto 0); variable depth_green : unsigned(7 downto 0); variable shimmer : unsigned(7 downto 0); begin -- Deeper = darker blue depth_blue := to_unsigned(180 - (py / 4), 8); depth_green := to_unsigned(40 + (py / 16), 8); shimmer := resize(frame_counter(5 downto 0), 8); -- Sandy bottom row if row >= CONSOLE_ROWS - 2 then bg_red <= x"C2"; bg_green <= x"B2"; bg_blue <= x"6E"; else bg_red <= std_logic_vector(to_unsigned(5, 8)); bg_green <= std_logic_vector(depth_green + shimmer(4 downto 2)); bg_blue <= std_logic_vector(depth_blue); end if; end process; -- Foreground colors per element process(row, col, fish1_col, fish2_col, fish3_col, fish4_col, frame_counter, bubble_phase) begin -- Default: white-ish foreground_color <= x"CCDDFF"; -- Title: golden yellow if row = title_row and col >= title_col and col < title_col + title_text'length then foreground_color <= x"FFD700"; -- Fish 1: orange elsif row = fish1_row and col >= fish1_col and col < fish1_col + fish1'length then foreground_color <= x"FF6633"; -- Fish 2: cyan/teal elsif row = fish2_row and col >= fish2_col and col < fish2_col + fish2'length then foreground_color <= x"00CED1"; -- Fish 3: magenta/pink elsif row = fish3_row and col >= fish3_col and col < fish3_col + fish3'length then foreground_color <= x"FF69B4"; -- Fish 4: lime green elsif row = fish4_row and col >= fish4_col and col < fish4_col + fish4'length then foreground_color <= x"7FFF00"; -- Crab: red elsif row = crab_row and col >= crab_col and col < crab_col + crab_text'length then foreground_color <= x"FF2222"; -- Bubbles: light blue elsif col = bubble_col or col = bubble_col + 30 or col = bubble_col + 55 then foreground_color <= x"AAEEFF"; -- Seaweed: green elsif row >= weed_row_start and row <= CONSOLE_ROWS - 2 then foreground_color <= x"228B22"; -- Water surface: light blue elsif row = 0 then foreground_color <= x"87CEEB"; -- Sandy bottom text elsif row = CONSOLE_ROWS - 1 then foreground_color <= x"A09060"; end if; end process; end architecture;
Sucess!
UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250%TRELLIS_COMB1901242887.8%TRELLIS_FF176242880.7%TRELLIS_IO101975.1%
TimingClockAchievedConstraint$glbnet$clkp37.98 MHz25 MHz$glbnet$clkt281.21 MHz250 MHz
Codelibrary ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1') ); end my_code; architecture rtl of my_code is alias bg_red : std_logic_vector(7 downto 0) is background_color(23 downto 16); alias bg_green : std_logic_vector(7 downto 0) is background_color(15 downto 8); alias bg_blue : std_logic_vector(7 downto 0) is background_color(7 downto 0); signal frame_counter : unsigned(31 downto 0) := (others => '0'); -- Aquarium title constant title_text : string(1 to 28) := "~~ Tiny VHDL Aquarium! ~~ <3"; constant title_row : integer := 1; constant title_col : integer := 26; -- Fish 1: ><> constant fish1 : string(1 to 3) := "><>"; constant fish1_row : integer := 10; -- Fish 2: <>< (facing left) constant fish2 : string(1 to 3) := "<><"; constant fish2_row : integer := 20; -- Fish 3: ><))'> constant fish3 : string(1 to 6) := "><))'>"; constant fish3_row : integer := 30; -- Fish 4: <'((<> constant fish4 : string(1 to 6) := "<'((<>"; constant fish4_row : integer := 40; -- Bubbles column constant bubble_col : integer := 5; -- Seaweed constant weed_row_start : integer := 50; -- Crab at bottom constant crab_text : string(1 to 5) := "V(..)"; constant crab_row : integer := 57; constant crab_col : integer := 38; signal fish1_col : integer range 0 to CONSOLE_COLUMNS - 1 := 0; signal fish2_col : integer range 0 to CONSOLE_COLUMNS - 1 := 70; signal fish3_col : integer range 0 to CONSOLE_COLUMNS - 1 := 0; signal fish4_col : integer range 0 to CONSOLE_COLUMNS - 1 := 60; signal bubble_phase : unsigned(5 downto 0) := (others => '0'); signal char_out : integer range 0 to 127 := 0; -- Helper function: modulo for column wrapping function wrap_col(val : integer; max_val : integer) return integer is begin return val mod max_val; end function; begin -- Frame counter & animation process(clk) variable old_vsync : std_logic := '0'; variable fc_local : unsigned(31 downto 0) := (others => '0'); begin if rising_edge(clk) then if rst = '1' then frame_counter <= (others => '0'); fish1_col <= 0; fish2_col <= 70; fish3_col <= 0; fish4_col <= 60; bubble_phase <= (others => '0'); elsif vsync = '0' and old_vsync = '1' then frame_counter <= frame_counter + 1; -- Move fish every 8 frames for a gentle swim if frame_counter(2 downto 0) = "000" then -- Fish 1 swims right if fish1_col < CONSOLE_COLUMNS - 1 then fish1_col <= fish1_col + 1; else fish1_col <= 0; end if; -- Fish 3 swims right (slower, updates every 16 frames via extra bit) if frame_counter(3) = '1' then if fish3_col < CONSOLE_COLUMNS - 1 then fish3_col <= fish3_col + 1; else fish3_col <= 0; end if; end if; -- Fish 2 swims left if fish2_col > 0 then fish2_col <= fish2_col - 1; else fish2_col <= CONSOLE_COLUMNS - 1; end if; -- Fish 4 swims left if fish4_col > 0 then fish4_col <= fish4_col - 1; else fish4_col <= CONSOLE_COLUMNS - 1; end if; bubble_phase <= bubble_phase + 1; end if; end if; old_vsync := vsync; end if; end process; -- Character output logic process(col, row, fish1_col, fish2_col, fish3_col, fish4_col, frame_counter, bubble_phase) variable c : integer range 0 to 127 := 0; variable rel : integer; variable bub_row : integer; begin c := 0; -- default: space -- Title if row = title_row and col >= title_col and col < title_col + title_text'length then rel := col - title_col + 1; if rel >= 1 and rel <= title_text'length then c := character'pos(title_text(rel)); end if; -- Fish 1: ><> swimming right elsif row = fish1_row and col >= fish1_col and col < fish1_col + fish1'length then rel := col - fish1_col + 1; if rel >= 1 and rel <= fish1'length then c := character'pos(fish1(rel)); end if; -- Fish 2: <>< swimming left elsif row = fish2_row and col >= fish2_col and col < fish2_col + fish2'length then rel := col - fish2_col + 1; if rel >= 1 and rel <= fish2'length then c := character'pos(fish2(rel)); end if; -- Fish 3: ><))'> swimming right elsif row = fish3_row and col >= fish3_col and col < fish3_col + fish3'length then rel := col - fish3_col + 1; if rel >= 1 and rel <= fish3'length then c := character'pos(fish3(rel)); end if; -- Fish 4: <'((<> swimming left elsif row = fish4_row and col >= fish4_col and col < fish4_col + fish4'length then rel := col - fish4_col + 1; if rel >= 1 and rel <= fish4'length then c := character'pos(fish4(rel)); end if; -- Crab at bottom elsif row = crab_row and col >= crab_col and col < crab_col + crab_text'length then rel := col - crab_col + 1; if rel >= 1 and rel <= crab_text'length then c := character'pos(crab_text(rel)); end if; -- Bubbles: 'o' rising in a column, 3 bubbles spaced apart, shifting upward elsif col = bubble_col or col = bubble_col + 30 or col = bubble_col + 55 then bub_row := to_integer(bubble_phase); if row = (CONSOLE_ROWS - 5 - (bub_row mod (CONSOLE_ROWS - 6))) or row = (CONSOLE_ROWS - 5 - ((bub_row + 12) mod (CONSOLE_ROWS - 6))) or row = (CONSOLE_ROWS - 5 - ((bub_row + 24) mod (CONSOLE_ROWS - 6))) then c := character'pos('o'); end if; -- Seaweed at the bottom: alternating | and ( depending on frame for sway elsif row >= weed_row_start and row <= CONSOLE_ROWS - 2 then if col = 10 or col = 20 or col = 35 or col = 50 or col = 65 or col = 75 then if frame_counter(4) = '0' then c := character'pos('('); else c := character'pos(')'); end if; end if; -- Sandy bottom elsif row = CONSOLE_ROWS - 1 then if (col mod 3) = 0 then c := character'pos('.'); elsif (col mod 3) = 1 then c := character'pos(','); else c := character'pos('_'); end if; -- Water surface elsif row = 0 then if frame_counter(3) = '0' then c := character'pos('~'); else c := character'pos('-'); end if; end if; char_out <= c; end process; char <= char_out; -- Background: deep ocean gradient (dark blue, getting darker toward bottom) process(row, col, frame_counter, py) variable depth_blue : unsigned(7 downto 0); variable depth_green : unsigned(7 downto 0); variable shimmer : unsigned(7 downto 0); begin -- Deeper = darker blue depth_blue := to_unsigned(180 - (py / 4), 8); depth_green := to_unsigned(40 + (py / 16), 8); shimmer := resize(frame_counter(5 downto 0), 8); -- Sandy bottom row if row >= CONSOLE_ROWS - 2 then bg_red <= x"C2"; bg_green <= x"B2"; bg_blue <= x"6E"; else bg_red <= std_logic_vector(to_unsigned(5, 8)); bg_green <= std_logic_vector(depth_green + shimmer(4 downto 2)); bg_blue <= std_logic_vector(depth_blue); end if; end process; -- Foreground colors per element process(row, col, fish1_col, fish2_col, fish3_col, fish4_col, frame_counter, bubble_phase) begin -- Default: white-ish foreground_color <= x"CCDDFF"; -- Title: golden yellow if row = title_row and col >= title_col and col < title_col + title_text'length then foreground_color <= x"FFD700"; -- Fish 1: orange elsif row = fish1_row and col >= fish1_col and col < fish1_col + fish1'length then foreground_color <= x"FF6633"; -- Fish 2: cyan/teal elsif row = fish2_row and col >= fish2_col and col < fish2_col + fish2'length then foreground_color <= x"00CED1"; -- Fish 3: magenta/pink elsif row = fish3_row and col >= fish3_col and col < fish3_col + fish3'length then foreground_color <= x"FF69B4"; -- Fish 4: lime green elsif row = fish4_row and col >= fish4_col and col < fish4_col + fish4'length then foreground_color <= x"7FFF00"; -- Crab: red elsif row = crab_row and col >= crab_col and col < crab_col + crab_text'length then foreground_color <= x"FF2222"; -- Bubbles: light blue elsif col = bubble_col or col = bubble_col + 30 or col = bubble_col + 55 then foreground_color <= x"AAEEFF"; -- Seaweed: green elsif row >= weed_row_start and row <= CONSOLE_ROWS - 2 then foreground_color <= x"228B22"; -- Water surface: light blue elsif row = 0 then foreground_color <= x"87CEEB"; -- Sandy bottom text elsif row = CONSOLE_ROWS - 1 then foreground_color <= x"A09060"; end if; end process; end architecture;
#FPGA #Icepi-Zero #HDL #VHDL -
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1') ); end my_code; architecture rtl of my_code is constant IMAGE_WIDTH : integer := 32; constant IMAGE_HEIGHT : integer := 32; type image_type is array (0 to IMAGE_HEIGHT-1) of std_logic_vector(0 to IMAGE_WIDTH-1); constant image_open : image_type := ( "00000000000000000000000000000000", "00000000000000000000000000000000", "00000000000001111111000000000000", "00000000000111111111110000000000", "00000000011111111111111100000000", "00000000111111111110011110000000", "00000001111111111100001111000000", "00000011111111111110011111100000", "00000011111111111111111111100000", "00000111111111111111111111110000", "00000111111111111111111111110000", "00000111111111111111111111110000", "00000111111111111111111111000000", "00000111111111111111111000000000", "00000111111111111111000000000000", "00000111111111111110000000000000", "00000111111111111110000000000000", "00000111111111111110000000000000", "00000111111111111110000000000000", "00000111111111111111000000000000", "00000111111111111111111000000000", "00000111111111111111111111000000", "00000111111111111111111111110000", "00000111111111111111111111110000", "00000011111111111111111111100000", "00000011111111111111111111100000", "00000001111111111111111111000000", "00000000111111111111111110000000", "00000000011111111111111100000000", "00000000000111111111110000000000", "00000000000001111111000000000000", "00000000000000000000000000000000" ); constant image_closed : image_type := ( "00000000000000000000000000000000", "00000000000000000000000000000000", "00000000000001111111000000000000", "00000000000111111111110000000000", "00000000011111111111111100000000", "00000000111111111110011110000000", "00000001111111111100001111000000", "00000011111111111110011111100000", "00000011111111111111111111100000", "00000111111111111111111111110000", "00000111111111111111111111110000", "00000111111111111111111111110000", "00000111111111111111111111110000", "00000111111111111111111111110000", "00000111111111111111111111110000", "00000111111111111111111111110000", "00000111111111111111111111110000", "00000111111111111111111111110000", "00000111111111111111111111110000", "00000111111111111111111111110000", "00000111111111111111111111110000", "00000111111111111111111111110000", "00000111111111111111111111110000", "00000111111111111111111111110000", "00000011111111111111111111100000", "00000011111111111111111111100000", "00000001111111111111111111000000", "00000000111111111111111110000000", "00000000011111111111111100000000", "00000000000111111111110000000000", "00000000000001111111000000000000", "00000000000000000000000000000000" ); type grid_type is array (0 to HEIGHT/IMAGE_HEIGHT-1) of std_logic_vector(0 to WIDTH/IMAGE_WIDTH-1); constant grid : grid_type := ( "11111111111111111111", "10000000011000000001", "10111111011011111101", "10100000000000000101", "10101111011011110101", "10000000011000000001", "11111111011011111111", "10000000000000000001", "11111111011011111111", "10000000011000000001", "10101111011011110101", "10100000000000000101", "10111111011011111101", "10000000011000000001", "11111111111111111111" ); constant SPEED : integer := 2; signal position_x : integer range -SPEED to WIDTH + SPEED := WIDTH/2; signal position_y : integer range -SPEED to HEIGHT + SPEED := WIDTH/2; signal direction : integer := 0; signal image_x : integer range 0 to IMAGE_WIDTH-1; signal image_y : integer range 0 to IMAGE_HEIGHT-1; signal directional_image_x : integer range 0 to IMAGE_WIDTH-1; signal directional_image_y : integer range 0 to IMAGE_HEIGHT-1; signal debug_next_tile_x : integer; signal debug_next_tile_y : integer; signal random_bit : std_logic := '0'; signal frame_counter : unsigned(31 downto 0) := (others => '0'); component OSCG is generic ( DIV : integer := 128 ); port ( OSC : out std_logic ); end component; begin char <= 0; foreground_color <= (others => '1'); image_x <= px - position_x; image_y <= py - position_y; with direction select directional_image_x <= image_x when 0, image_y when 1, (IMAGE_WIDTH - 1) - image_x when 2, (IMAGE_HEIGHT - 1) - image_y when 3, 0 when others; with direction select directional_image_y <= image_y when 0, (IMAGE_WIDTH - 1) - image_x when 1, image_y when 2, image_x when 3, 0 when others; background_color <= x"FFFFFF" when grid(py/IMAGE_HEIGHT)(px/IMAGE_WIDTH) = '1' else x"FFFF00" when frame_counter(4) = '0' and image_open(directional_image_y)(directional_image_x) = '1' and px >= position_x and px < position_x + IMAGE_WIDTH and py >= position_y and py < position_y + IMAGE_HEIGHT else x"FFFF00" when frame_counter(4) = '1' and image_closed(directional_image_y)(directional_image_x) = '1' and px >= position_x and px < position_x + IMAGE_WIDTH and py >= position_y and py < position_y + IMAGE_HEIGHT else --x"7F0000" when debug_next_tile_x = px/IMAGE_WIDTH and debug_next_tile_y = py/IMAGE_HEIGHT else x"000000"; rng : OSCG port map ( OSC => random_bit ); process(clk) variable old_vsync : std_logic := '0'; variable next_direction : integer := 0; variable next_x : integer range -SPEED to WIDTH + SPEED := 0; variable next_y : integer range -SPEED to HEIGHT + SPEED := 0; variable next_tile_x : integer := 0; variable next_tile_y : integer := 0; variable good : std_logic := '0'; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then frame_counter <= frame_counter + 1; good := '0'; if position_x mod IMAGE_WIDTH = 0 and position_y mod IMAGE_HEIGHT = 0 then if random_bit = '1' then next_direction := (next_direction + 1) mod 4; else next_direction := (next_direction + 3) mod 4; end if; end if; end if; old_vsync := vsync; if good = '0' then case next_direction is when 0 => next_x := position_x + SPEED; next_y := position_y; when 1 => next_x := position_x; next_y := position_y + SPEED; when 2 => next_x := position_x - SPEED; next_y := position_y; when 3 => next_x := position_x; next_y := position_y - SPEED; when others => null; end case; next_tile_x := next_x / IMAGE_WIDTH; next_tile_y := next_y / IMAGE_HEIGHT; if next_direction = 0 and (next_x mod IMAGE_WIDTH) /= 0 then next_tile_x := next_tile_x + 1; elsif next_direction = 1 and (next_y mod IMAGE_HEIGHT) /= 0 then next_tile_y := next_tile_y + 1; end if; debug_next_tile_x <= next_tile_x; debug_next_tile_y <= next_tile_y; if next_tile_y = 7 and next_tile_x = 0 and direction = 2 then good := '1'; position_x <= 18*IMAGE_WIDTH; position_y <= position_y; direction <= 0; elsif next_tile_y = 7 and next_tile_x = 19 and direction = 0 then good := '1'; position_x <= 1*IMAGE_WIDTH; position_y <= position_y; direction <= 2; elsif grid(next_tile_y)(next_tile_x) = '0' and next_direction /= ((direction + 2) mod 4) then good := '1'; position_x <= next_x; position_y <= next_y; direction <= next_direction mod 4; else if random_bit = '1' then next_direction := (next_direction + 1) mod 4; else next_direction := (next_direction + 3) mod 4; end if; end if; end if; end if; end process; end architecture;
Sucess!
UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250%MULT18X18D2287.1%OSCG11100%TRELLIS_COMB1100242884.5%TRELLIS_FF196242880.8%TRELLIS_IO101975.1%
TimingClockAchievedConstraint$glbnet$clkp36.51 MHz25 MHz$glbnet$clkt261.37 MHz250 MHz
Codelibrary ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1') ); end my_code; architecture rtl of my_code is constant IMAGE_WIDTH : integer := 32; constant IMAGE_HEIGHT : integer := 32; type image_type is array (0 to IMAGE_HEIGHT-1) of std_logic_vector(0 to IMAGE_WIDTH-1); constant image_open : image_type := ( "00000000000000000000000000000000", "00000000000000000000000000000000", "00000000000001111111000000000000", "00000000000111111111110000000000", "00000000011111111111111100000000", "00000000111111111110011110000000", "00000001111111111100001111000000", "00000011111111111110011111100000", "00000011111111111111111111100000", "00000111111111111111111111110000", "00000111111111111111111111110000", "00000111111111111111111111110000", "00000111111111111111111111000000", "00000111111111111111111000000000", "00000111111111111111000000000000", "00000111111111111110000000000000", "00000111111111111110000000000000", "00000111111111111110000000000000", "00000111111111111110000000000000", "00000111111111111111000000000000", "00000111111111111111111000000000", "00000111111111111111111111000000", "00000111111111111111111111110000", "00000111111111111111111111110000", "00000011111111111111111111100000", "00000011111111111111111111100000", "00000001111111111111111111000000", "00000000111111111111111110000000", "00000000011111111111111100000000", "00000000000111111111110000000000", "00000000000001111111000000000000", "00000000000000000000000000000000" ); constant image_closed : image_type := ( "00000000000000000000000000000000", "00000000000000000000000000000000", "00000000000001111111000000000000", "00000000000111111111110000000000", "00000000011111111111111100000000", "00000000111111111110011110000000", "00000001111111111100001111000000", "00000011111111111110011111100000", "00000011111111111111111111100000", "00000111111111111111111111110000", "00000111111111111111111111110000", "00000111111111111111111111110000", "00000111111111111111111111110000", "00000111111111111111111111110000", "00000111111111111111111111110000", "00000111111111111111111111110000", "00000111111111111111111111110000", "00000111111111111111111111110000", "00000111111111111111111111110000", "00000111111111111111111111110000", "00000111111111111111111111110000", "00000111111111111111111111110000", "00000111111111111111111111110000", "00000111111111111111111111110000", "00000011111111111111111111100000", "00000011111111111111111111100000", "00000001111111111111111111000000", "00000000111111111111111110000000", "00000000011111111111111100000000", "00000000000111111111110000000000", "00000000000001111111000000000000", "00000000000000000000000000000000" ); type grid_type is array (0 to HEIGHT/IMAGE_HEIGHT-1) of std_logic_vector(0 to WIDTH/IMAGE_WIDTH-1); constant grid : grid_type := ( "11111111111111111111", "10000000011000000001", "10111111011011111101", "10100000000000000101", "10101111011011110101", "10000000011000000001", "11111111011011111111", "10000000000000000001", "11111111011011111111", "10000000011000000001", "10101111011011110101", "10100000000000000101", "10111111011011111101", "10000000011000000001", "11111111111111111111" ); constant SPEED : integer := 2; signal position_x : integer range -SPEED to WIDTH + SPEED := WIDTH/2; signal position_y : integer range -SPEED to HEIGHT + SPEED := WIDTH/2; signal direction : integer := 0; signal image_x : integer range 0 to IMAGE_WIDTH-1; signal image_y : integer range 0 to IMAGE_HEIGHT-1; signal directional_image_x : integer range 0 to IMAGE_WIDTH-1; signal directional_image_y : integer range 0 to IMAGE_HEIGHT-1; signal debug_next_tile_x : integer; signal debug_next_tile_y : integer; signal random_bit : std_logic := '0'; signal frame_counter : unsigned(31 downto 0) := (others => '0'); component OSCG is generic ( DIV : integer := 128 ); port ( OSC : out std_logic ); end component; begin char <= 0; foreground_color <= (others => '1'); image_x <= px - position_x; image_y <= py - position_y; with direction select directional_image_x <= image_x when 0, image_y when 1, (IMAGE_WIDTH - 1) - image_x when 2, (IMAGE_HEIGHT - 1) - image_y when 3, 0 when others; with direction select directional_image_y <= image_y when 0, (IMAGE_WIDTH - 1) - image_x when 1, image_y when 2, image_x when 3, 0 when others; background_color <= x"FFFFFF" when grid(py/IMAGE_HEIGHT)(px/IMAGE_WIDTH) = '1' else x"FFFF00" when frame_counter(4) = '0' and image_open(directional_image_y)(directional_image_x) = '1' and px >= position_x and px < position_x + IMAGE_WIDTH and py >= position_y and py < position_y + IMAGE_HEIGHT else x"FFFF00" when frame_counter(4) = '1' and image_closed(directional_image_y)(directional_image_x) = '1' and px >= position_x and px < position_x + IMAGE_WIDTH and py >= position_y and py < position_y + IMAGE_HEIGHT else --x"7F0000" when debug_next_tile_x = px/IMAGE_WIDTH and debug_next_tile_y = py/IMAGE_HEIGHT else x"000000"; rng : OSCG port map ( OSC => random_bit ); process(clk) variable old_vsync : std_logic := '0'; variable next_direction : integer := 0; variable next_x : integer range -SPEED to WIDTH + SPEED := 0; variable next_y : integer range -SPEED to HEIGHT + SPEED := 0; variable next_tile_x : integer := 0; variable next_tile_y : integer := 0; variable good : std_logic := '0'; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then frame_counter <= frame_counter + 1; good := '0'; if position_x mod IMAGE_WIDTH = 0 and position_y mod IMAGE_HEIGHT = 0 then if random_bit = '1' then next_direction := (next_direction + 1) mod 4; else next_direction := (next_direction + 3) mod 4; end if; end if; end if; old_vsync := vsync; if good = '0' then case next_direction is when 0 => next_x := position_x + SPEED; next_y := position_y; when 1 => next_x := position_x; next_y := position_y + SPEED; when 2 => next_x := position_x - SPEED; next_y := position_y; when 3 => next_x := position_x; next_y := position_y - SPEED; when others => null; end case; next_tile_x := next_x / IMAGE_WIDTH; next_tile_y := next_y / IMAGE_HEIGHT; if next_direction = 0 and (next_x mod IMAGE_WIDTH) /= 0 then next_tile_x := next_tile_x + 1; elsif next_direction = 1 and (next_y mod IMAGE_HEIGHT) /= 0 then next_tile_y := next_tile_y + 1; end if; debug_next_tile_x <= next_tile_x; debug_next_tile_y <= next_tile_y; if next_tile_y = 7 and next_tile_x = 0 and direction = 2 then good := '1'; position_x <= 18*IMAGE_WIDTH; position_y <= position_y; direction <= 0; elsif next_tile_y = 7 and next_tile_x = 19 and direction = 0 then good := '1'; position_x <= 1*IMAGE_WIDTH; position_y <= position_y; direction <= 2; elsif grid(next_tile_y)(next_tile_x) = '0' and next_direction /= ((direction + 2) mod 4) then good := '1'; position_x <= next_x; position_y <= next_y; direction <= next_direction mod 4; else if random_bit = '1' then next_direction := (next_direction + 1) mod 4; else next_direction := (next_direction + 3) mod 4; end if; end if; end if; end if; end process; end architecture;
#FPGA #Icepi-Zero #HDL #VHDL
