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#verilog — Public Fediverse posts

Live and recent posts from across the Fediverse tagged #verilog, aggregated by home.social.

  1. JCM @[email protected] ·

    @[email protected]

    I am pleased to announce that @icepi-zero-bot is back up and running. :waffy_party:

    Now inside my Kubernetes cluster on more powerful hardware, so you should hopefully see some faster synthesis times and slightly nicer videos!
    I think I secured it pretty well, but if someone manages to do something naughty, please don't nom-nom all my data :pleading_face:
    Also, please don't break my FPGA on purporse, oki? :3

    Sadly, I still need to figure out Spade support, because I couldn't find any prebuilt arm64 binaries for it :(

    So, if you want to write cool SystemVerilog/VHDL/Amaranth/Veryl code, have it run on a real FPGA and output video (no need to implement DVI yourself, dw), which is then recorded and posted, check out @icepi-zero-bot's profile! The profile description contains tons of explanations and templates.

    Soon, I will hopefully add Spade support back and also implement a UART interface, so you can also output text! The support for that in the bot is already there, I just need to implement a UART transmitter in VHDL and think of a cute and easy interface.



    RE: https://wafrn.jcm.re/fediverse/post/83972345-09e4-47d9-99d3-4a3885a2a198
    #fedibot #FPGA #HDL #VHDL #Verilog #SystemVerilog #Amaranth #Veryl
    #fedibot #fpga #hdl #vhdl #verilog #systemverilog
  2. JCM @[email protected] ·

    @[email protected]

    I am pleased to announce that @icepi-zero-bot is back up and running. :waffy_party:

    Now inside my Kubernetes cluster on more powerful hardware, so you should hopefully see some faster synthesis times and slightly nicer videos!
    I think I secured it pretty well, but if someone manages to do something naughty, please don't nom-nom all my data :pleading_face:
    Also, please don't break my FPGA on purporse, oki? :3

    Sadly, I still need to figure out Spade support, because I couldn't find any prebuilt arm64 binaries for it :(

    So, if you want to write cool SystemVerilog/VHDL/Amaranth/Veryl code, have it run on a real FPGA and output video (no need to implement DVI yourself, dw), which is then recorded and posted, check out @icepi-zero-bot's profile! The profile description contains tons of explanations and templates.

    Soon, I will hopefully add Spade support back and also implement a UART interface, so you can also output text! The support for that in the bot is already there, I just need to implement a UART transmitter in VHDL and think of a cute and easy interface.



    RE: https://wafrn.jcm.re/fediverse/post/83972345-09e4-47d9-99d3-4a3885a2a198
    #fedibot #FPGA #HDL #VHDL #Verilog #SystemVerilog #Amaranth #Veryl
    #fedibot #fpga #hdl #vhdl #verilog #systemverilog
  3. Habr @[email protected] ·

    Перепрыгивание с языка на язык как тактика прохождения интервью

    В 2010 году я участвовал в интервьировании на позицию по моделированию и верификации процессорных ядер. Один из кандидатов был благообразный седой американец, который до этого работал в IBM. Я задал вопрос про язык описания и верификации аппаратуры SystemVerilog. На это кандидат сказал, что он еще не освоил SystemVerilog, вписал его в резюме на будущее, но вообще использовал Verilog-95 и немного Verilog-2001. “Нет проблем”, - сказал я и задал вопрос по Verilog-95: “приведите примеры гонок (race conditions) при испрользовании верилога”. На это кандидат сказал, что вообще его опыт был больше связан с VHDL. “Блин, как он выкрутился” - подумал я, ведь в VHDL нет гонок как в верилоге из-за дизайна языка.

    habr.com/ru/articles/1033360/

    #SystemVerilog #verilog #Ada #VHDL #Jovial #Coral66 #IBM #Стенфорд #вопросы_на_собеседовании #внешний_вид

    #внешний_вид #вопросы_на_собеседовании #стенфорд #ibm #coral66 #jovial
  4. cnx-software.com [Unofficial] @[email protected] ·

    AERIS-10 open-source hardware radar can track multiple objects up to 20km away

    web.brid.gy/r/https://www.cnx-

    #hardware #stmicrostm32 #xilinxartix #diy #fpga #military
  5. cnx-software.com [Unofficial] @[email protected] ·

    AERIS-10 open-source hardware radar can track multiple objects up to 20km away

    web.brid.gy/r/https://www.cnx-

    #hardware #stmicrostm32 #xilinxartix #diy #fpga #military
  6. JCM @[email protected] ·

    Small update announcement for the @icepi-zero-bot (that you might have noticed already):

    • The bot now reports details about utilization and clock speeds together with the video in the success post.
    • You can split your code into multiple messages if your instance has a low character limit for direct messages (see the bot's description for more details).

    For the future, I plan to:

    • Add support for more HDLs (tell me your favorite ones and I try to integrate them).
    • Support for outputting text via UART, that the host will capture and include in the success post.

    If you have any other ideas/wishes, feel free to tell me :D


    #FPGA #bot #fedibot #Icepi-Zero #VHDL #Verilog #SystemVerilog #Amaranth
    #fpga #bot #fedibot #icepizero #vhdl #verilog
  7. JCM @[email protected] ·

    Small update announcement for the @icepi-zero-bot (that you might have noticed already):

    • The bot now reports details about utilization and clock speeds together with the video in the success post.
    • You can split your code into multiple messages if your instance has a low character limit for direct messages (see the bot's description for more details).

    For the future, I plan to:

    • Add support for more HDLs (tell me your favorite ones and I try to integrate them).
    • Support for outputting text via UART, that the host will capture and include in the success post.

    If you have any other ideas/wishes, feel free to tell me :D


    #FPGA #bot #fedibot #Icepi-Zero #VHDL #Verilog #SystemVerilog #Amaranth
    #fpga #bot #fedibot #icepizero #vhdl #verilog
  8. JCM @[email protected] ·

    Small update announcement for the @icepi-zero-bot (that you might have noticed already):

    • The bot now reports details about utilization and clock speeds together with the video in the success post.
    • You can split your code into multiple messages if your instance has a low character limit for direct messages (see the bot's description for more details).

    For the future, I plan to:

    • Add support for more HDLs (tell me your favorite ones and I try to integrate them).
    • Support for outputting text via UART, that the host will capture and include in the success post.

    If you have any other ideas/wishes, feel free to tell me :D


    #FPGA #bot #fedibot #Icepi-Zero #VHDL #Verilog #SystemVerilog #Amaranth
    #fpga #bot #fedibot #icepizero #vhdl #verilog
  9. JCM @[email protected] ·

    Small update announcement for the @icepi-zero-bot (that you might have noticed already):

    • The bot now reports details about utilization and clock speeds together with the video in the success post.
    • You can split your code into multiple messages if your instance has a low character limit for direct messages (see the bot's description for more details).

    For the future, I plan to:

    • Add support for more HDLs (tell me your favorite ones and I try to integrate them).
    • Support for outputting text via UART, that the host will capture and include in the success post.

    If you have any other ideas/wishes, feel free to tell me :D


    #FPGA #bot #fedibot #Icepi-Zero #VHDL #Verilog #SystemVerilog #Amaranth
    #amaranth #systemverilog #verilog #vhdl #icepizero #fedibot