#verilog — Public Fediverse posts
Live and recent posts from across the Fediverse tagged #verilog, aggregated by home.social.
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Verilog hates you.
If reg [7:0] wptr; and wptr=255 these expressions are completely different:
wptr + 1 == 0
wptr + 1'b1 == 0I blogged about this yet it still caught me out: "Verilog uses the width of the widest operand when evaluating an expression".
The width of 1 is 32 bits because #Verilog.
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🎉 pfDevTools v2.3.0 is out! 🎉
My openFPGA dev environment is back.
Turns out 2.2.0 was very much broken in many ways after a bad refactoring but I hadn't had the chance to revisit it and fix all the bugs. It is now ALL (hopefully) FIXED!
I tested my core and the tutorials I wrote and they now all build fine.
I may be back doing some FPGA stuff soon :)
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Создаем I2C Master Controller на Verilog. Перенос на Zynq 7000 (bare-metal)
После успешной отладки на плате с Cyclone IV пришла пора перенести наработки на плату Zynq Mini c XC7Z020. В этой статье я опишу, каким образом можно организовать вывод нужной нам информации из PS-части Zynq на дисплей который подключен к EMIO на выводах PL. Сделаем обновленный модуль i2c_master_axi который добавляет сверху к уже разработанному ядру поддержку AXI4-Lite Slave, сделаем сборку проекта, подключим их к PS и проверим в bare-metal сценарии. После того как это будет все работать - переходить к Linux уже будет гораздо проще. Всем заинтересованным добро пожаловать под кат!
https://habr.com/ru/companies/beget/articles/1037124/
#zynq7000 #zynqmini #oled #ssd1306 #verilog #baremetal #tutorial #vivado #vitis
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One Open-source Project Daily
Digital logic design tool and simulator
https://github.com/logisim-evolution/logisim-evolution
#1ospd #opensource #circuit #circuits #digitalcircuit #digitalcircuits #digitallogic #digitallogicdesign #education #fpga #logic #logisim #logisimevolution #simulator #timingdiagram #verilog #vhdl -
OK this is pretty cool. A project called DigitalJS can give you a visual layout of all of the logic that'll go into a Verilog design, using Yosys to do the generation. Being able to see what's being ultimately produced helps me, a much more visual person, understand when I've flubbed something that generates too much logic. I already optimized one piece of the display RAM using it. It's at https://digitaljs.tilk.eu/ but you can also run it locally. #fpga #verilog #ulx3s
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Al Williams Tells All in the Logic Simulation Hack Chat - The list of requirements for hosting one of our weekly Hack Chats is pretty short:... - https://hackaday.com/2022/03/04/al-williams-tells-all-in-the-logic-simulation-hack-chat/ #circuitsimulation #hackadaycolumns #digitallogic #hackchat #verilog #asic #fpga #hdl