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#verilog — Public Fediverse posts

Live and recent posts from across the Fediverse tagged #verilog, aggregated by home.social.

  1. Flux @[email protected] ·

    Verilog hates you.

    If reg [7:0] wptr; and wptr=255 these expressions are completely different:

    wptr + 1 == 0
    wptr + 1'b1 == 0

    I blogged about this yet it still caught me out: "Verilog uses the width of the widest operand when evaluating an expression".

    The width of 1 is 32 bits because #Verilog.

    #verilog
  2. Didier Malenfant @[email protected] ·

    🎉 pfDevTools v2.3.0 is out! 🎉

    My openFPGA dev environment is back.

    Turns out 2.2.0 was very much broken in many ways after a bad refactoring but I hadn't had the chance to revisit it and fix all the bugs. It is now ALL (hopefully) FIXED!

    I tested my core and the tutorials I wrote and they now all build fine.

    I may be back doing some FPGA stuff soon :)

    code.malenfant.net/didier/pfDe

    #AnaloguePocket #FPGA #openFPGA #Verilog #IndieDev #GameDev

    #analoguepocket #fpga #openfpga #verilog #indiedev #gamedev
  3. Habr @[email protected] ·

    Создаем I2C Master Controller на Verilog. Перенос на Zynq 7000 (bare-metal)

    После успешной отладки на плате с Cyclone IV пришла пора перенести наработки на плату Zynq Mini c XC7Z020. В этой статье я опишу, каким образом можно организовать вывод нужной нам информации из PS-части Zynq на дисплей который подключен к EMIO на выводах PL. Сделаем обновленный модуль i2c_master_axi который добавляет сверху к уже разработанному ядру поддержку AXI4-Lite Slave, сделаем сборку проекта, подключим их к PS и проверим в bare-metal сценарии. После того как это будет все работать - переходить к Linux уже будет гораздо проще. Всем заинтересованным добро пожаловать под кат!

    habr.com/ru/companies/beget/ar

    #zynq7000 #zynqmini #oled #ssd1306 #verilog #baremetal #tutorial #vivado #vitis

    #vitis #vivado #tutorial #baremetal #verilog #ssd1306
  4. Patrick :neocat_flag_bi: @[email protected] ·

    One Open-source Project Daily

    Digital logic design tool and simulator

    https://github.com/logisim-evolution/logisim-evolution

    #1ospd #opensource #circuit #circuits #digitalcircuit #digitalcircuits #digitallogic #digitallogicdesign #education #fpga #logic #logisim #logisimevolution #simulator #timingdiagram #verilog #vhdl

    #1ospd #opensource #circuit #circuits #digitalcircuit #digitalcircuits
  5. Topaz 🐇 @[email protected] ·

    OK this is pretty cool. A project called DigitalJS can give you a visual layout of all of the logic that'll go into a Verilog design, using Yosys to do the generation. Being able to see what's being ultimately produced helps me, a much more visual person, understand when I've flubbed something that generates too much logic. I already optimized one piece of the display RAM using it. It's at digitaljs.tilk.eu/ but you can also run it locally. #fpga #verilog #ulx3s

    #fpga #verilog #ulx3s
  6. Tommy Þ @[email protected] ·

    I was curious about #Bluespec but I couldn't find even a "blink LED" example, so I finally wrote my own. This doesn't show any of the strengths of Bluespec, but this does blink LEDs (on the #ULX3S #FPGA dev kit). The generated #Verilog looks fine.

    github.com/tommythorn/bluespec

    #bluespec #ulx3s #fpga #verilog
  7. IT News @[email protected] ·

    Al Williams Tells All in the Logic Simulation Hack Chat - The list of requirements for hosting one of our weekly Hack Chats is pretty short:... - hackaday.com/2022/03/04/al-wil #circuitsimulation #hackadaycolumns #digitallogic #hackchat #verilog #asic #fpga #hdl

    #hdl #fpga #asic #verilog #hackchat #digitallogic