#verilog — Public Fediverse posts

Verilog hates you.

If reg [7:0] wptr; and wptr=255 these expressions are completely different:

wptr + 1 == 0
wptr + 1'b1 == 0

I blogged about this yet it still caught me out: "Verilog uses the width of the widest operand when evaluating an expression".

The width of 1 is 32 bits because #Verilog.

🎉 pfDevTools v2.3.0 is out! 🎉

My openFPGA dev environment is back.

Turns out 2.2.0 was very much broken in many ways after a bad refactoring but I hadn't had the chance to revisit it and fix all the bugs. It is now ALL (hopefully) FIXED!

I tested my core and the tutorials I wrote and they now all build fine.

I may be back doing some FPGA stuff soon :)

https://code.malenfant.net/didier/pfDevTools

#AnaloguePocket #FPGA #openFPGA #Verilog #IndieDev #GameDev

One Open-source Project Daily

Digital logic design tool and simulator

https://github.com/logisim-evolution/logisim-evolution

#1ospd #opensource #circuit #circuits #digitalcircuit #digitalcircuits #digitallogic #digitallogicdesign #education #fpga #logic #logisim #logisimevolution #simulator #timingdiagram #verilog #vhdl

Some #Taylor expansion of #sine and #cosine in #Verilog, fixed point arithmetic 🎉

(With a little help from the large parrot machine.)

Al Williams Tells All in the Logic Simulation Hack Chat - The list of requirements for hosting one of our weekly Hack Chats is pretty short:... - https://hackaday.com/2022/03/04/al-williams-tells-all-in-the-logic-simulation-hack-chat/ #circuitsimulation #hackadaycolumns #digitallogic #hackchat #verilog #asic #fpga #hdl