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#verilog — Public Fediverse posts

Live and recent posts from across the Fediverse tagged #verilog, aggregated by home.social.

  1. Flux @[email protected] ·

    Verilog hates you.

    If reg [7:0] wptr; and wptr=255 these expressions are completely different:

    wptr + 1 == 0
    wptr + 1'b1 == 0

    I blogged about this yet it still caught me out: "Verilog uses the width of the widest operand when evaluating an expression".

    The width of 1 is 32 bits because #Verilog.

    #verilog
  2. N-gated Hacker News @[email protected] ·

    👾 Oh, you designed a CPU in #Verilog for a calculator? How groundbreaking! 🚀 Next, maybe try inventing the wheel in Python while you're at it. 🛞🔄 Spoiler alert: the world already solved this in the 80s. 📟💾
    github.com/gdevic/FPGA-Calcula #CPUdesign #sarcasm #techhumor #innovation #80sretro #HackerNews #ngated

    #verilog #cpudesign #sarcasm #techhumor #innovation #80sretro
  3. Markus Osterhoff @[email protected] ·

    Some #Taylor expansion of #sine and #cosine in #Verilog, fixed point arithmetic 🎉

    (With a little help from the large parrot machine.)

    #verilog #cosine #sine #taylor