#verilog — Public Fediverse posts
Live and recent posts from across the Fediverse tagged #verilog, aggregated by home.social.
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Verilog hates you.
If reg [7:0] wptr; and wptr=255 these expressions are completely different:
wptr + 1 == 0
wptr + 1'b1 == 0I blogged about this yet it still caught me out: "Verilog uses the width of the widest operand when evaluating an expression".
The width of 1 is 32 bits because #Verilog.