#verilog — Public Fediverse posts
Live and recent posts from across the Fediverse tagged #verilog, aggregated by home.social.
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Verilog hates you.
If reg [7:0] wptr; and wptr=255 these expressions are completely different:
wptr + 1 == 0
wptr + 1'b1 == 0I blogged about this yet it still caught me out: "Verilog uses the width of the widest operand when evaluating an expression".
The width of 1 is 32 bits because #Verilog.
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👾 Oh, you designed a CPU in #Verilog for a calculator? How groundbreaking! 🚀 Next, maybe try inventing the wheel in Python while you're at it. 🛞🔄 Spoiler alert: the world already solved this in the 80s. 📟💾
https://github.com/gdevic/FPGA-Calculator #CPUdesign #sarcasm #techhumor #innovation #80sretro #HackerNews #ngated -
One Open-source Project Daily
Digital logic design tool and simulator
https://github.com/logisim-evolution/logisim-evolution
#1ospd #opensource #circuit #circuits #digitalcircuit #digitalcircuits #digitallogic #digitallogicdesign #education #fpga #logic #logisim #logisimevolution #simulator #timingdiagram #verilog #vhdl -
Al Williams Tells All in the Logic Simulation Hack Chat - The list of requirements for hosting one of our weekly Hack Chats is pretty short:... - https://hackaday.com/2022/03/04/al-williams-tells-all-in-the-logic-simulation-hack-chat/ #circuitsimulation #hackadaycolumns #digitallogic #hackchat #verilog #asic #fpga #hdl