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#verilog — Public Fediverse posts

Live and recent posts from across the Fediverse tagged #verilog, aggregated by home.social.

  1. Flux @[email protected] ·

    Verilog hates you.

    If reg [7:0] wptr; and wptr=255 these expressions are completely different:

    wptr + 1 == 0
    wptr + 1'b1 == 0

    I blogged about this yet it still caught me out: "Verilog uses the width of the widest operand when evaluating an expression".

    The width of 1 is 32 bits because #Verilog.

    #verilog
  2. Habr @[email protected] ·

    Мост для ко-симуляции в Icarus Verilog и NGSpice

    Автор: Cyberflex (по мотивам реальной разработки бриджа для Ко-симуляции " MixFighter" ) Как мы сделали мост между Icarus Verilog и NGSpice: две разных реализации архитектуры.

    habr.com/ru/articles/1023270/

    #IcarusVerilog #SPICE #NGSPIice #Cosimulation #Mixed_simulation #asic #verilog #netlist

    #netlist #verilog #asic #mixed_simulation #cosimulation #ngspiice