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#verilog — Public Fediverse posts

Live and recent posts from across the Fediverse tagged #verilog, aggregated by home.social.

  1. Verilog hates you.

    If reg [7:0] wptr; and wptr=255 these expressions are completely different:

    wptr + 1 == 0
    wptr + 1'b1 == 0

    I blogged about this yet it still caught me out: "Verilog uses the width of the widest operand when evaluating an expression".

    The width of 1 is 32 bits because #Verilog.

  2. 🎉 pfDevTools v2.3.0 is out! 🎉

    My openFPGA dev environment is back.

    Turns out 2.2.0 was very much broken in many ways after a bad refactoring but I hadn't had the chance to revisit it and fix all the bugs. It is now ALL (hopefully) FIXED!

    I tested my core and the tutorials I wrote and they now all build fine.

    I may be back doing some FPGA stuff soon :)

    code.malenfant.net/didier/pfDe

    #AnaloguePocket #FPGA #openFPGA #Verilog #IndieDev #GameDev

  3. Some #Taylor expansion of #sine and #cosine in #Verilog, fixed point arithmetic 🎉

    (With a little help from the large parrot machine.)