#gtkwave — Public Fediverse posts

Создаем I2C Master Controller на Verilog. Тестируем ядро

По результатам написания прошлой статьи у нас получился объемный модуль для реализации функций низкоуровневого управления шиной I2C, который формирует управление линиями SCL/SDA, поддерживает мониторинг шины, ведет передачу и прием данных. В этой статье я предлагаю организовать полноценное вдумчивое тестирование всего что получилось. Всем заинтересованным - добро пожаловать под кат! 🙂

https://habr.com/ru/companies/beget/articles/1024342/

#verilog #verilator #iverilog #gtkwave #i2c_master_controller #testbench #icarus_verilog

Создаем I2C Master Controller на Verilog. Тестируем ядро

По результатам написания прошлой статьи у нас получился объемный модуль для реализации функций низкоуровневого управления шиной I2C, который формирует управление линиями SCL/SDA, поддерживает мониторинг шины, ведет передачу и прием данных. В этой статье я предлагаю организовать полноценное вдумчивое тестирование всего что получилось. Всем заинтересованным - добро пожаловать под кат! 🙂

https://habr.com/ru/companies/beget/articles/1024342/

#verilog #verilator #iverilog #gtkwave #i2c_master_controller #testbench #icarus_verilog

Создаем I2C Master Controller на Verilog. Тестируем ядро

По результатам написания прошлой статьи у нас получился объемный модуль для реализации функций низкоуровневого управления шиной I2C, который формирует управление линиями SCL/SDA, поддерживает мониторинг шины, ведет передачу и прием данных. В этой статье я предлагаю организовать полноценное вдумчивое тестирование всего что получилось. Всем заинтересованным - добро пожаловать под кат! 🙂

https://habr.com/ru/companies/beget/articles/1024342/

#verilog #verilator #iverilog #gtkwave #i2c_master_controller #testbench #icarus_verilog

Создаем I2C Master Controller на Verilog. Тестируем ядро

По результатам написания прошлой статьи у нас получился объемный модуль для реализации функций низкоуровневого управления шиной I2C, который формирует управление линиями SCL/SDA, поддерживает мониторинг шины, ведет передачу и прием данных. В этой статье я предлагаю организовать полноценное вдумчивое тестирование всего что получилось. Всем заинтересованным - добро пожаловать под кат! 🙂

https://habr.com/ru/companies/beget/articles/1024342/

#verilog #verilator #iverilog #gtkwave #i2c_master_controller #testbench #icarus_verilog

So what can you do with the ability to read arbitrary #FPGA registers out of your design over #UART? Capture time series data (last four #ethernet packet bytes) in your regs and write a little #python script that launches #GTKWave and you have yourself a tiny homemade cross platform logic analyzer thing!
https://github.com/JulianKemmerer/PipelineC/wiki/Example:-Debug-Probes

So what can you do with the ability to read arbitrary #FPGA registers out of your design over #UART? Capture time series data (last four #ethernet packet bytes) in your regs and write a little #python script that launches #GTKWave and you have yourself a tiny homemade cross platform logic analyzer thing!
https://github.com/JulianKemmerer/PipelineC/wiki/Example:-Debug-Probes

So what can you do with the ability to read arbitrary #FPGA registers out of your design over #UART? Capture time series data (last four #ethernet packet bytes) in your regs and write a little #python script that launches #GTKWave and you have yourself a tiny homemade cross platform logic analyzer thing!
https://github.com/JulianKemmerer/PipelineC/wiki/Example:-Debug-Probes

So what can you do with the ability to read arbitrary #FPGA registers out of your design over #UART? Capture time series data (last four #ethernet packet bytes) in your regs and write a little #python script that launches #GTKWave and you have yourself a tiny homemade cross platform logic analyzer thing!
https://github.com/JulianKemmerer/PipelineC/wiki/Example:-Debug-Probes

So what can you do with the ability to read arbitrary #FPGA registers out of your design over #UART? Capture time series data (last four #ethernet packet bytes) in your regs and write a little #python script that launches #GTKWave and you have yourself a tiny homemade cross platform logic analyzer thing!
https://github.com/JulianKemmerer/PipelineC/wiki/Example:-Debug-Probes

Адаптация платы Colorlight 5A-75B для примеров «Школы синтеза цифровых схем»

Привет! Начался новый поток «Школы синтеза цифровых схем» и я хотел бы поделиться своим опытом по адаптации бюджетной платы с ПЛИС для запуска на ней лабораторных работ Школы. Отдельным преимуществом такого решения является возможность использования Open Source маршрута для синтеза и моделирования цифровых схем на базе Yosys и Icarus Verilog. Colorlight 5A-75B не является отладочной платой в привычном понимании этого понятия - будет интересно.

https://habr.com/ru/articles/849592/

#плис #fpga #yosys #lattice #verilog #systemverilog #icarus #gtkwave

Адаптация платы Colorlight 5A-75B для примеров «Школы синтеза цифровых схем»

Привет! Начался новый поток «Школы синтеза цифровых схем» и я хотел бы поделиться своим опытом по адаптации бюджетной платы с ПЛИС для запуска на ней лабораторных работ Школы. Отдельным преимуществом такого решения является возможность использования Open Source маршрута для синтеза и моделирования цифровых схем на базе Yosys и Icarus Verilog. Colorlight 5A-75B не является отладочной платой в привычном понимании этого понятия - будет интересно.

https://habr.com/ru/articles/849592/

#плис #fpga #yosys #lattice #verilog #systemverilog #icarus #gtkwave

Адаптация платы Colorlight 5A-75B для примеров «Школы синтеза цифровых схем»

Привет! Начался новый поток «Школы синтеза цифровых схем» и я хотел бы поделиться своим опытом по адаптации бюджетной платы с ПЛИС для запуска на ней лабораторных работ Школы. Отдельным преимуществом такого решения является возможность использования Open Source маршрута для синтеза и моделирования цифровых схем на базе Yosys и Icarus Verilog. Colorlight 5A-75B не является отладочной платой в привычном понимании этого понятия - будет интересно.

https://habr.com/ru/articles/849592/

#плис #fpga #yosys #lattice #verilog #systemverilog #icarus #gtkwave

@thezoq2 I just tried #surfer for the first time today. Compiled from scratch per the website. I had to file a bug, as it crashes after adding a handful of signals.

I was so hopeful. But for now going back to #gtkwave I'm sad though, because surfer is able to do very simple things like select all the signals at a level and add them to the viewer, whereas gtkwave seems to fight you at every step of the way.

Maybe I need to roll back to a tagged version and rebuild or something. #ghdl #vhdl

@thezoq2 I just tried #surfer for the first time today. Compiled from scratch per the website. I had to file a bug, as it crashes after adding a handful of signals.

I was so hopeful. But for now going back to #gtkwave I'm sad though, because surfer is able to do very simple things like select all the signals at a level and add them to the viewer, whereas gtkwave seems to fight you at every step of the way.

Maybe I need to roll back to a tagged version and rebuild or something. #ghdl #vhdl

@thezoq2 I just tried #surfer for the first time today. Compiled from scratch per the website. I had to file a bug, as it crashes after adding a handful of signals.

I was so hopeful. But for now going back to #gtkwave I'm sad though, because surfer is able to do very simple things like select all the signals at a level and add them to the viewer, whereas gtkwave seems to fight you at every step of the way.

Maybe I need to roll back to a tagged version and rebuild or something. #ghdl #vhdl

@thezoq2 I just tried #surfer for the first time today. Compiled from scratch per the website. I had to file a bug, as it crashes after adding a handful of signals.

I was so hopeful. But for now going back to #gtkwave I'm sad though, because surfer is able to do very simple things like select all the signals at a level and add them to the viewer, whereas gtkwave seems to fight you at every step of the way.

Maybe I need to roll back to a tagged version and rebuild or something. #ghdl #vhdl

@thezoq2 I just tried #surfer for the first time today. Compiled from scratch per the website. I had to file a bug, as it crashes after adding a handful of signals.

I was so hopeful. But for now going back to #gtkwave I'm sad though, because surfer is able to do very simple things like select all the signals at a level and add them to the viewer, whereas gtkwave seems to fight you at every step of the way.

Maybe I need to roll back to a tagged version and rebuild or something. #ghdl #vhdl

Ok so it's still a bit buggy on windows, and ModelSim doesn't play nice.

But combined with #GHDL for open source #VHDL simulation and #gtkwave for wave viewing it's a surprisingly comfortable to set up tool chain, especially on Linux it's all just via package manager and pip~

Now to learn proper file structuring and documenting habits to raise the code quality bar a bit, probably add proper test benches~
Again #TerosHDL helps with built in docs generator <3

Ok so it's still a bit buggy on windows, and ModelSim doesn't play nice.

But combined with #GHDL for open source #VHDL simulation and #gtkwave for wave viewing it's a surprisingly comfortable to set up tool chain, especially on Linux it's all just via package manager and pip~

Now to learn proper file structuring and documenting habits to raise the code quality bar a bit, probably add proper test benches~
Again #TerosHDL helps with built in docs generator <3

Ok so it's still a bit buggy on windows, and ModelSim doesn't play nice.

But combined with #GHDL for open source #VHDL simulation and #gtkwave for wave viewing it's a surprisingly comfortable to set up tool chain, especially on Linux it's all just via package manager and pip~

Now to learn proper file structuring and documenting habits to raise the code quality bar a bit, probably add proper test benches~
Again #TerosHDL helps with built in docs generator <3

Ok so it's still a bit buggy on windows, and ModelSim doesn't play nice.

But combined with #GHDL for open source #VHDL simulation and #gtkwave for wave viewing it's a surprisingly comfortable to set up tool chain, especially on Linux it's all just via package manager and pip~

Now to learn proper file structuring and documenting habits to raise the code quality bar a bit, probably add proper test benches~
Again #TerosHDL helps with built in docs generator <3

In case this this has baffled anyone else for years, under the Edit menu there's a Toggle Hier button and Set Max Heir button that do the trick on 3.3.104 #gtkwave #fpga #vcd #fst

In case this this has baffled anyone else for years, under the Edit menu there's a Toggle Hier button and Set Max Heir button that do the trick on 3.3.104 #gtkwave #fpga #vcd #fst

In case this this has baffled anyone else for years, under the Edit menu there's a Toggle Hier button and Set Max Heir button that do the trick on 3.3.104 #gtkwave #fpga #vcd #fst

In case this this has baffled anyone else for years, under the Edit menu there's a Toggle Hier button and Set Max Heir button that do the trick on 3.3.104 #gtkwave #fpga #vcd #fst

Is there a way in gtkwave to have it display more of a signals hierarchy? In Modelsim you can have it show anywhere from none to the entirety, but I can't figure out how to do that in gtkwave. #fpga #gtkwave #vcd #fst

Is there a way in gtkwave to have it display more of a signals hierarchy? In Modelsim you can have it show anywhere from none to the entirety, but I can't figure out how to do that in gtkwave. #fpga #gtkwave #vcd #fst

Is there a way in gtkwave to have it display more of a signals hierarchy? In Modelsim you can have it show anywhere from none to the entirety, but I can't figure out how to do that in gtkwave. #fpga #gtkwave #vcd #fst

Is there a way in gtkwave to have it display more of a signals hierarchy? In Modelsim you can have it show anywhere from none to the entirety, but I can't figure out how to do that in gtkwave. #fpga #gtkwave #vcd #fst

Why, #gtkwave, why? What don't you like? You see the values from the sim #fpga and you correctly know that they aren't 0. And you seem to know it's a string of bits. What does that leave? Why are you angry/confused by 1s and only in this variable?

Why, #gtkwave, why? What don't you like? You see the values from the sim #fpga and you correctly know that they aren't 0. And you seem to know it's a string of bits. What does that leave? Why are you angry/confused by 1s and only in this variable?

Why, #gtkwave, why? What don't you like? You see the values from the sim #fpga and you correctly know that they aren't 0. And you seem to know it's a string of bits. What does that leave? Why are you angry/confused by 1s and only in this variable?

Why, #gtkwave, why? What don't you like? You see the values from the sim #fpga and you correctly know that they aren't 0. And you seem to know it's a string of bits. What does that leave? Why are you angry/confused by 1s and only in this variable?

Why, #gtkwave, why? What don't you like? You see the values from the sim #fpga and you correctly know that they aren't 0. And you seem to know it's a string of bits. What does that leave? Why are you angry/confused by 1s and only in this variable?

FPGA Starter Videos To Help Soften That Learning Curve - Digi-Key have been producing YouTube videos for a number of years now, and if you ... - https://hackaday.com/2022/02/17/fpga-starter-videos-to-help-soften-that-learning-curve/ #projecttrellis #blackice #icestorm #gtkwave #lattice #mystorm #nextpnr #icarus #ice40 #yosys #fpga #apio