#nextpnr — Public Fediverse posts
Live and recent posts from across the Fediverse tagged #nextpnr, aggregated by home.social.
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I've been playing around with #LiteX and #migen #HDL lately and I think it's finally starting to sink in that you can really just do almost arbitrary amounts of "stuff" per clock (limitations apply, objects in mirror may appear closer etc).
It's really very fun! And between trellis, #yosys and #nextpnr you can just... Do it without begging any vendor for a free copy of an EDA.
I highly recommend it! It's so much fun!
You can make your own SoC with deranged peripherals!
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I've been playing around with #LiteX and #migen #HDL lately and I think it's finally starting to sink in that you can really just do almost arbitrary amounts of "stuff" per clock (limitations apply, objects in mirror may appear closer etc).
It's really very fun! And between trellis, #yosys and #nextpnr you can just... Do it without begging any vendor for a free copy of an EDA.
I highly recommend it! It's so much fun!
You can make your own SoC with deranged peripherals!
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This is a wiki about processing video in real time using microcontrollers, ASICs and FPGAs. The related paper was accepted for the Open Source Hardware Conference in Chemnitz Germany, Nov 24-25 2025.
Comment on the page by replying to this toot. #Introduction
#OSHOP #OpenSource #Hardware #FPGA #Yosys #Nextpnr #Video #Pipelines #Introduction
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@PaulaMaddox Well, I've got the gui tool installed and I see I can start with a demo that echoes data back via the Ft+ V2... that seems like a great start.
Crossing fingers.
I'm not worried about an upload tool much. More about design lock in or other anti-patterns.
I'd love to get experience with #yosys and #nextpnr and maybe this will be my excuse to try.
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@PaulaMaddox Well, I've got the gui tool installed and I see I can start with a demo that echoes data back via the Ft+ V2... that seems like a great start.
Crossing fingers.
I'm not worried about an upload tool much. More about design lock in or other anti-patterns.
I'd love to get experience with #yosys and #nextpnr and maybe this will be my excuse to try.
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We had a very productive #FSD meeting earlier today! Check out what we accomplished: https://www.fsf.org/blogs/licensing/fsd-meeting-recap-2025-02-21 #FreeSoftware #Licensing #nextpnr #Yosys
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We had a very productive #FSD meeting earlier today! Check out what we accomplished: https://www.fsf.org/blogs/licensing/fsd-meeting-recap-2025-02-21 #FreeSoftware #Licensing #nextpnr #Yosys
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I started a project page to document my first FPGA project on a long while, mainly so that I don't forget, but could possibly be useful to others... I'll plan to add subsequent projects and make more progress on this one in the next few weeks and months.
"I bought myself a Radiona ULX3S from CrowdSupply, which includes the 85k Lattice ECP5 FPGA, which can be programmed to simulate the open source 32-bit RISC-V CPU with a completely open source LiteX-yosys-nextpnr, toolchain."
https://blog.bomorgan.io/hobbies/hardware/fpgas/litex-riscv-ecp5-ulx3s/
#riscv #foss #fpga #litex #yosys #nextpnr #linux #crowdsupply #radiona #ulx3s #lattice #ecp5
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I started a project page to document my first FPGA project on a long while, mainly so that I don't forget, but could possibly be useful to others... I'll plan to add subsequent projects and make more progress on this one in the next few weeks and months.
"I bought myself a Radiona ULX3S from CrowdSupply, which includes the 85k Lattice ECP5 FPGA, which can be programmed to simulate the open source 32-bit RISC-V CPU with a completely open source LiteX-yosys-nextpnr, toolchain."
https://blog.bomorgan.io/hobbies/hardware/fpgas/litex-riscv-ecp5-ulx3s/
#riscv #foss #fpga #litex #yosys #nextpnr #linux #crowdsupply #radiona #ulx3s #lattice #ecp5
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Ah, I just realized that the explicit use of LUTs means the inverted wasn't eliminated. By creating a variant cell with inverted input I lost all the inverter LUTs and got at least 48% better performance, thus now at 248.6 MHz. I suspect the fabric limit is better than that, but I don't know how to nudge #nextpnr to give me better routing (I would welcome suggestions).
Repo updated.
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Ah, I just realized that the explicit use of LUTs means the inverted wasn't eliminated. By creating a variant cell with inverted input I lost all the inverter LUTs and got at least 48% better performance, thus now at 248.6 MHz. I suspect the fabric limit is better than that, but I don't know how to nudge #nextpnr to give me better routing (I would welcome suggestions).
Repo updated.
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AHHHH! I finally got a ring oscillator working on #ECP5 with the #Yosys / #Nextpnr tool chain (I’m not complaining, I’m happy they exist and I’m doing something unorthodox)
You have to instantiate the inverters as LUTs directly *AND* you have to build the latest tools yourself (I had two different binaries segfault on the design).
https://github.com/YosysHQ/nextpnr/issues/1194#issuecomment-1684724413
#verilog #fpga #ncl #asynclogic -
#verilog #fpga #yosys #nextpnr Oh no, nextpnr can't handle combinatorial loops? That's going to be a problem. (EDIT: just use —ignore-loops but my (old) nextpnr then segfaults)
I got "ERROR: timing analysis failed due to presence of combinatorial loops, incomplete specification of timing ports, etc." but I don't care about timing analysis so maybe I can work around this?
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@yrabbit
Very exciting! But please take your time with everything, I will be happy to try it out once it's ready 😃️By the way, I would be very interested in your thought process and the steps involved in implementing a new primitive like ELVDS in #apicula + #yosys + #nextpnr .
Maybe someday you could toot about this in detail? -
Great success! I managed to build a working fpga toolchain for #openbsd
GHDL -> #yosys -> #nextpnr -> #icestorm
Updating the yosys port was very straight forward. nextpnr and ghdl can be build without any changes, there is a small patch needed for icestorm. Next step is figuring out how to create ports for ghdl, nextpnr and icestorm
