#ulx3s — Public Fediverse posts

With scroll hardware registers fixed, here’s a demo of draw and display scrolling hardware. #ULX3S #FPGA

With scroll hardware registers fixed, here’s a demo of draw and display scrolling hardware. #ULX3S #FPGA

With scroll hardware registers fixed, here’s a demo of draw and display scrolling hardware. #ULX3S #FPGA

With scroll hardware registers fixed, here’s a demo of draw and display scrolling hardware. #ULX3S #FPGA

At FCCM 2026 I saw a keynote by Onur Mutlu on abusing DRAM chip timings to have them perform vector (row) copies and even or/and/nand computations on entire rows, 'for free' (happens physically through capacitors charge). And this is on current, off-the-shelves DDR3/DDR4 memory!

Well, I've got a bunch of great FPGA boards featuring good old SDRAM chips and ...

It turns out RowClone is possible on older SDRAM chips!

#FPGA #ULX3s #Silice

At FCCM 2026 I saw a keynote by Onur Mutlu on abusing DRAM chip timings to have them perform vector (row) copies and even or/and/nand computations on entire rows, 'for free' (happens physically through capacitors charge). And this is on current, off-the-shelves DDR3/DDR4 memory!

Well, I've got a bunch of great FPGA boards featuring good old SDRAM chips and ...

It turns out RowClone is possible on older SDRAM chips!

#FPGA #ULX3s #Silice

At FCCM 2026 I saw a keynote by Onur Mutlu on abusing DRAM chip timings to have them perform vector (row) copies and even or/and/nand computations on entire rows, 'for free' (happens physically through capacitors charge). And this is on current, off-the-shelves DDR3/DDR4 memory!

Well, I've got a bunch of great FPGA boards featuring good old SDRAM chips and ...

It turns out RowClone is possible on older SDRAM chips!

#FPGA #ULX3s #Silice

At FCCM 2026 I saw a keynote by Onur Mutlu on abusing DRAM chip timings to have them perform vector (row) copies and even or/and/nand computations on entire rows, 'for free' (happens physically through capacitors charge). And this is on current, off-the-shelves DDR3/DDR4 memory!

Well, I've got a bunch of great FPGA boards featuring good old SDRAM chips and ...

It turns out RowClone is possible on older SDRAM chips!

#FPGA #ULX3s #Silice

Working on making PLLs easier to use in #Silice, here testing with a #ulx3s / ECP5 board. Four clocks of same frequency, phased out 90 degrees each. If you are wondering why the clock signals are not perfect ... check the wiring 😅 .

Working on making PLLs easier to use in #Silice, here testing with a #ulx3s / ECP5 board. Four clocks of same frequency, phased out 90 degrees each. If you are wondering why the clock signals are not perfect ... check the wiring 😅 .

Working on making PLLs easier to use in #Silice, here testing with a #ulx3s / ECP5 board. Four clocks of same frequency, phased out 90 degrees each. If you are wondering why the clock signals are not perfect ... check the wiring 😅 .

Working on making PLLs easier to use in #Silice, here testing with a #ulx3s / ECP5 board. Four clocks of same frequency, phased out 90 degrees each. If you are wondering why the clock signals are not perfect ... check the wiring 😅 .

The TMDS clock wasn't meeting timing on #ULX3S. There is so little logic in the clk_pix_5x domain I doubted I could do much. Then I realised each channel shared a small critical ring counter. Giving each colour channel its own added 100 MHz+ to the max frequency! #FPGA 🚀

https://github.com/projf/isle/blob/main/hardware/arch/ecp5/dvi_generator.v

The TMDS clock wasn't meeting timing on #ULX3S. There is so little logic in the clk_pix_5x domain I doubted I could do much. Then I realised each channel shared a small critical ring counter. Giving each colour channel its own added 100 MHz+ to the max frequency! #FPGA 🚀

https://github.com/projf/isle/blob/main/hardware/arch/ecp5/dvi_generator.v

The TMDS clock wasn't meeting timing on #ULX3S. There is so little logic in the clk_pix_5x domain I doubted I could do much. Then I realised each channel shared a small critical ring counter. Giving each colour channel its own added 100 MHz+ to the max frequency! #FPGA 🚀

https://github.com/projf/isle/blob/main/hardware/arch/ecp5/dvi_generator.v

The TMDS clock wasn't meeting timing on #ULX3S. There is so little logic in the clk_pix_5x domain I doubted I could do much. Then I realised each channel shared a small critical ring counter. Giving each colour channel its own added 100 MHz+ to the max frequency! #FPGA 🚀

https://github.com/projf/isle/blob/main/hardware/arch/ecp5/dvi_generator.v

Made some time for 🏝️ Isle.Computer today. Getting the graphics registers working across clock domains so the CPU can double buffer, scroll, adjust transparency etc. #FPGA

Images show RISC-V CPU reading graphics registers in sim and on #ULX3S.

Made some time for 🏝️ Isle.Computer today. Getting the graphics registers working across clock domains so the CPU can double buffer, scroll, adjust transparency etc. #FPGA

Images show RISC-V CPU reading graphics registers in sim and on #ULX3S.

Made some time for 🏝️ Isle.Computer today. Getting the graphics registers working across clock domains so the CPU can double buffer, scroll, adjust transparency etc. #FPGA

Images show RISC-V CPU reading graphics registers in sim and on #ULX3S.

Made some time for 🏝️ Isle.Computer today. Getting the graphics registers working across clock domains so the CPU can double buffer, scroll, adjust transparency etc. #FPGA

Images show RISC-V CPU reading graphics registers in sim and on #ULX3S.

The @RadionaOrg ULX3S hub site now honors device dark mode! Sunglasses no longer needed 😎

I also added a Tiny Tapeout section, as (pending a few Pull Request merges) @latticesemi #ECP5 FPGA support for testing your ASIC design on the #ULX3S is coming to @tinytapeout

The @RadionaOrg ULX3S hub site now honors device dark mode! Sunglasses no longer needed 😎

I also added a Tiny Tapeout section, as (pending a few Pull Request merges) @latticesemi #ECP5 FPGA support for testing your ASIC design on the #ULX3S is coming to @tinytapeout

The @RadionaOrg ULX3S hub site now honors device dark mode! Sunglasses no longer needed 😎

I also added a Tiny Tapeout section, as (pending a few Pull Request merges) @latticesemi #ECP5 FPGA support for testing your ASIC design on the #ULX3S is coming to @tinytapeout

The @RadionaOrg ULX3S hub site now honors device dark mode! Sunglasses no longer needed 😎

I also added a Tiny Tapeout section, as (pending a few Pull Request merges) @latticesemi #ECP5 FPGA support for testing your ASIC design on the #ULX3S is coming to @tinytapeout

You can find the source code on GitHub (I'm considering moving to Codeberg): https://github.com/projf/isle

Includes everything you need for:
* @machdyne Lakritz (Lattice ECP5)
* Digilent Nexys Video (Xilinx XC7)
* Radiona #ULX3S (Lattice ECP5)
* Verilator simulator with SDL (Linux/macOS/Windows)

You can find the source code on GitHub (I'm considering moving to Codeberg): https://github.com/projf/isle

Includes everything you need for:
* @machdyne Lakritz (Lattice ECP5)
* Digilent Nexys Video (Xilinx XC7)
* Radiona #ULX3S (Lattice ECP5)
* Verilator simulator with SDL (Linux/macOS/Windows)

You can find the source code on GitHub (I'm considering moving to Codeberg): https://github.com/projf/isle

Includes everything you need for:
* @machdyne Lakritz (Lattice ECP5)
* Digilent Nexys Video (Xilinx XC7)
* Radiona #ULX3S (Lattice ECP5)
* Verilator simulator with SDL (Linux/macOS/Windows)

You can find the source code on GitHub (I'm considering moving to Codeberg): https://github.com/projf/isle

Includes everything you need for:
* @machdyne Lakritz (Lattice ECP5)
* Digilent Nexys Video (Xilinx XC7)
* Radiona #ULX3S (Lattice ECP5)
* Verilator simulator with SDL (Linux/macOS/Windows)

Board testing in advance of #FPGAFriday. The answer was 42. #ULX3S

Board testing in advance of #FPGAFriday. The answer was 42. #ULX3S

Board testing in advance of #FPGAFriday. The answer was 42. #ULX3S

Board testing in advance of #FPGAFriday. The answer was 42. #ULX3S

And a quick lunchtime shot of 🏝️ Isle.Computer running on #ULX3S.

Simulation may be practical for software dev, but it feels so much better seeing it running on real hardware. This is #riscv asm decoding UTF-8 sent over UART to Isle hardware running on #fpga. Verilog and asm written by hand. 😊

And a quick lunchtime shot of 🏝️ Isle.Computer running on #ULX3S.

Simulation may be practical for software dev, but it feels so much better seeing it running on real hardware. This is #riscv asm decoding UTF-8 sent over UART to Isle hardware running on #fpga. Verilog and asm written by hand. 😊

And a quick lunchtime shot of 🏝️ Isle.Computer running on #ULX3S.

Simulation may be practical for software dev, but it feels so much better seeing it running on real hardware. This is #riscv asm decoding UTF-8 sent over UART to Isle hardware running on #fpga. Verilog and asm written by hand. 😊

And a quick lunchtime shot of 🏝️ Isle.Computer running on #ULX3S.

Simulation may be practical for software dev, but it feels so much better seeing it running on real hardware. This is #riscv asm decoding UTF-8 sent over UART to Isle hardware running on #fpga. Verilog and asm written by hand. 😊

Work on 🏝️ Isle #FPGA computer input chapter continues. Here I’m testing UART with #ULX3S dev board.

Work on 🏝️ Isle #FPGA computer input chapter continues. Here I’m testing UART with #ULX3S dev board.

Work on 🏝️ Isle #FPGA computer input chapter continues. Here I’m testing UART with #ULX3S dev board.

Work on 🏝️ Isle #FPGA computer input chapter continues. Here I’m testing UART with #ULX3S dev board.

You can find the open-source designs and instructions for 🏝️ Isle FPGA computer at: https://github.com/projf/isle

You can run Isle on Linux/Mac/Windows under simulation, and it's really easy to set up.

Plus, there's board support #ULX3S, @machdyne Lakritz, and Digilent Nexys Video.

You can find the open-source designs and instructions for 🏝️ Isle FPGA computer at: https://github.com/projf/isle

You can run Isle on Linux/Mac/Windows under simulation, and it's really easy to set up.

Plus, there's board support #ULX3S, @machdyne Lakritz, and Digilent Nexys Video.

You can find the open-source designs and instructions for 🏝️ Isle FPGA computer at: https://github.com/projf/isle

You can run Isle on Linux/Mac/Windows under simulation, and it's really easy to set up.

Plus, there's board support #ULX3S, @machdyne Lakritz, and Digilent Nexys Video.

You can find the open-source designs and instructions for 🏝️ Isle FPGA computer at: https://github.com/projf/isle

You can run Isle on Linux/Mac/Windows under simulation, and it's really easy to set up.

Plus, there's board support #ULX3S, @machdyne Lakritz, and Digilent Nexys Video.

Isle computer supports @machdyne Lakritz, Digilent Nexys Video, and Radiona #ULX3S.

And it's easy to run Isle's simulation; for example on macOS with brew installed:

brew install verilator sdl2
cd isle/boards/verilator/ch04
make
./obj_dir/ch04 # run sim

Isle computer supports @machdyne Lakritz, Digilent Nexys Video, and Radiona #ULX3S.

And it's easy to run Isle's simulation; for example on macOS with brew installed:

brew install verilator sdl2
cd isle/boards/verilator/ch04
make
./obj_dir/ch04 # run sim

Isle computer supports @machdyne Lakritz, Digilent Nexys Video, and Radiona #ULX3S.

And it's easy to run Isle's simulation; for example on macOS with brew installed:

brew install verilator sdl2
cd isle/boards/verilator/ch04
make
./obj_dir/ch04 # run sim

Isle computer supports @machdyne Lakritz, Digilent Nexys Video, and Radiona #ULX3S.

And it's easy to run Isle's simulation; for example on macOS with brew installed:

brew install verilator sdl2
cd isle/boards/verilator/ch04
make
./obj_dir/ch04 # run sim

Isle.Computer hardware text mode on #ULX3S. With 2x scaling and horizontal offset to centre at 1366x768. I’m getting ready to release the next chapter and hardware designs. #FPGA

Isle.Computer hardware text mode on #ULX3S. With 2x scaling and horizontal offset to centre at 1366x768. I’m getting ready to release the next chapter and hardware designs. #FPGA

Isle.Computer hardware text mode on #ULX3S. With 2x scaling and horizontal offset to centre at 1366x768. I’m getting ready to release the next chapter and hardware designs. #FPGA

Isle.Computer hardware text mode on #ULX3S. With 2x scaling and horizontal offset to centre at 1366x768. I’m getting ready to release the next chapter and hardware designs. #FPGA

@WillFlux

Thanks a lot for the new post! Works perfectly on the #Radiona #ulx3s #fpga

@WillFlux

Thanks a lot for the new post! Works perfectly on the #Radiona #ulx3s #fpga

@WillFlux

Thanks a lot for the new post! Works perfectly on the #Radiona #ulx3s #fpga

@WillFlux

Thanks a lot for the new post! Works perfectly on the #Radiona #ulx3s #fpga

If you have a @machdyne Lakritz, Digilent Nexys Video, or Radiona #ULX3S #FPGA board, please give the latest 🏝️ Isle design a test and let me know how you get on. 🙏

2D drawing blog post: https://projectf.io/isle/2d-drawing.html
FPGA board Support: https://github.com/projf/isle/tree/main/boards

If you have a @machdyne Lakritz, Digilent Nexys Video, or Radiona #ULX3S #FPGA board, please give the latest 🏝️ Isle design a test and let me know how you get on. 🙏

2D drawing blog post: https://projectf.io/isle/2d-drawing.html
FPGA board Support: https://github.com/projf/isle/tree/main/boards

If you have a @machdyne Lakritz, Digilent Nexys Video, or Radiona #ULX3S #FPGA board, please give the latest 🏝️ Isle design a test and let me know how you get on. 🙏

2D drawing blog post: https://projectf.io/isle/2d-drawing.html
FPGA board Support: https://github.com/projf/isle/tree/main/boards

If you have a @machdyne Lakritz, Digilent Nexys Video, or Radiona #ULX3S #FPGA board, please give the latest 🏝️ Isle design a test and let me know how you get on. 🙏

2D drawing blog post: https://projectf.io/isle/2d-drawing.html
FPGA board Support: https://github.com/projf/isle/tree/main/boards