#ulx3s — Public Fediverse posts

At FCCM 2026 I saw a keynote by Onur Mutlu on abusing DRAM chip timings to have them perform vector (row) copies and even or/and/nand computations on entire rows, 'for free' (happens physically through capacitors charge). And this is on current, off-the-shelves DDR3/DDR4 memory!

Well, I've got a bunch of great FPGA boards featuring good old SDRAM chips and ...

It turns out RowClone is possible on older SDRAM chips!

#FPGA #ULX3s #Silice

At FCCM 2026 I saw a keynote by Onur Mutlu on abusing DRAM chip timings to have them perform vector (row) copies and even or/and/nand computations on entire rows, 'for free' (happens physically through capacitors charge). And this is on current, off-the-shelves DDR3/DDR4 memory!

Well, I've got a bunch of great FPGA boards featuring good old SDRAM chips and ...

It turns out RowClone is possible on older SDRAM chips!

#FPGA #ULX3s #Silice

Working on making PLLs easier to use in #Silice, here testing with a #ulx3s / ECP5 board. Four clocks of same frequency, phased out 90 degrees each. If you are wondering why the clock signals are not perfect ... check the wiring 😅 .

Working on making PLLs easier to use in #Silice, here testing with a #ulx3s / ECP5 board. Four clocks of same frequency, phased out 90 degrees each. If you are wondering why the clock signals are not perfect ... check the wiring 😅 .

The TMDS clock wasn't meeting timing on #ULX3S. There is so little logic in the clk_pix_5x domain I doubted I could do much. Then I realised each channel shared a small critical ring counter. Giving each colour channel its own added 100 MHz+ to the max frequency! #FPGA 🚀

https://github.com/projf/isle/blob/main/hardware/arch/ecp5/dvi_generator.v

The TMDS clock wasn't meeting timing on #ULX3S. There is so little logic in the clk_pix_5x domain I doubted I could do much. Then I realised each channel shared a small critical ring counter. Giving each colour channel its own added 100 MHz+ to the max frequency! #FPGA 🚀

https://github.com/projf/isle/blob/main/hardware/arch/ecp5/dvi_generator.v

Made some time for 🏝️ Isle.Computer today. Getting the graphics registers working across clock domains so the CPU can double buffer, scroll, adjust transparency etc. #FPGA

Images show RISC-V CPU reading graphics registers in sim and on #ULX3S.

Made some time for 🏝️ Isle.Computer today. Getting the graphics registers working across clock domains so the CPU can double buffer, scroll, adjust transparency etc. #FPGA

Images show RISC-V CPU reading graphics registers in sim and on #ULX3S.

The @RadionaOrg ULX3S hub site now honors device dark mode! Sunglasses no longer needed 😎

I also added a Tiny Tapeout section, as (pending a few Pull Request merges) @latticesemi #ECP5 FPGA support for testing your ASIC design on the #ULX3S is coming to @tinytapeout

The @RadionaOrg ULX3S hub site now honors device dark mode! Sunglasses no longer needed 😎

I also added a Tiny Tapeout section, as (pending a few Pull Request merges) @latticesemi #ECP5 FPGA support for testing your ASIC design on the #ULX3S is coming to @tinytapeout

You can find the source code on GitHub (I'm considering moving to Codeberg): https://github.com/projf/isle

Includes everything you need for:
* @machdyne Lakritz (Lattice ECP5)
* Digilent Nexys Video (Xilinx XC7)
* Radiona #ULX3S (Lattice ECP5)
* Verilator simulator with SDL (Linux/macOS/Windows)

You can find the source code on GitHub (I'm considering moving to Codeberg): https://github.com/projf/isle

Includes everything you need for:
* @machdyne Lakritz (Lattice ECP5)
* Digilent Nexys Video (Xilinx XC7)
* Radiona #ULX3S (Lattice ECP5)
* Verilator simulator with SDL (Linux/macOS/Windows)

Board testing in advance of #FPGAFriday. The answer was 42. #ULX3S

Board testing in advance of #FPGAFriday. The answer was 42. #ULX3S

And a quick lunchtime shot of 🏝️ Isle.Computer running on #ULX3S.

Simulation may be practical for software dev, but it feels so much better seeing it running on real hardware. This is #riscv asm decoding UTF-8 sent over UART to Isle hardware running on #fpga. Verilog and asm written by hand. 😊

And a quick lunchtime shot of 🏝️ Isle.Computer running on #ULX3S.

Simulation may be practical for software dev, but it feels so much better seeing it running on real hardware. This is #riscv asm decoding UTF-8 sent over UART to Isle hardware running on #fpga. Verilog and asm written by hand. 😊

Work on 🏝️ Isle #FPGA computer input chapter continues. Here I’m testing UART with #ULX3S dev board.

Work on 🏝️ Isle #FPGA computer input chapter continues. Here I’m testing UART with #ULX3S dev board.

You can find the open-source designs and instructions for 🏝️ Isle FPGA computer at: https://github.com/projf/isle

You can run Isle on Linux/Mac/Windows under simulation, and it's really easy to set up.

Plus, there's board support #ULX3S, @machdyne Lakritz, and Digilent Nexys Video.

You can find the open-source designs and instructions for 🏝️ Isle FPGA computer at: https://github.com/projf/isle

You can run Isle on Linux/Mac/Windows under simulation, and it's really easy to set up.

Plus, there's board support #ULX3S, @machdyne Lakritz, and Digilent Nexys Video.

Isle computer supports @machdyne Lakritz, Digilent Nexys Video, and Radiona #ULX3S.

And it's easy to run Isle's simulation; for example on macOS with brew installed:

brew install verilator sdl2
cd isle/boards/verilator/ch04
make
./obj_dir/ch04 # run sim

Isle computer supports @machdyne Lakritz, Digilent Nexys Video, and Radiona #ULX3S.

And it's easy to run Isle's simulation; for example on macOS with brew installed:

brew install verilator sdl2
cd isle/boards/verilator/ch04
make
./obj_dir/ch04 # run sim

Isle.Computer hardware text mode on #ULX3S. With 2x scaling and horizontal offset to centre at 1366x768. I’m getting ready to release the next chapter and hardware designs. #FPGA

Isle.Computer hardware text mode on #ULX3S. With 2x scaling and horizontal offset to centre at 1366x768. I’m getting ready to release the next chapter and hardware designs. #FPGA

@WillFlux

Thanks a lot for the new post! Works perfectly on the #Radiona #ulx3s #fpga

@WillFlux

Thanks a lot for the new post! Works perfectly on the #Radiona #ulx3s #fpga

If you have a @machdyne Lakritz, Digilent Nexys Video, or Radiona #ULX3S #FPGA board, please give the latest 🏝️ Isle design a test and let me know how you get on. 🙏

2D drawing blog post: https://projectf.io/isle/2d-drawing.html
FPGA board Support: https://github.com/projf/isle/tree/main/boards

If you have a @machdyne Lakritz, Digilent Nexys Video, or Radiona #ULX3S #FPGA board, please give the latest 🏝️ Isle design a test and let me know how you get on. 🙏

2D drawing blog post: https://projectf.io/isle/2d-drawing.html
FPGA board Support: https://github.com/projf/isle/tree/main/boards

I am happy to announce the FemtoMSP430, a processor designed with the instruction set of the classic #MSP430, but with a flexible bus interface similar to @BrunoLevy01 #FemtoRV32 including memory busy signaling. The playground contains a phantasy "microcontroller" design for the #ULX3S #FPGA board, interactively running the original #Mecrisp #Forth image for MSP430G2755, enhanced with a text mode on 800x600 video, USB-CDC terminal and a lot of GPIO wires: https://codeberg.org/Mecrisp/FemtoMSP430

I am happy to announce the FemtoMSP430, a processor designed with the instruction set of the classic #MSP430, but with a flexible bus interface similar to @BrunoLevy01 #FemtoRV32 including memory busy signaling. The playground contains a phantasy "microcontroller" design for the #ULX3S #FPGA board, interactively running the original #Mecrisp #Forth image for MSP430G2755, enhanced with a text mode on 800x600 video, USB-CDC terminal and a lot of GPIO wires: https://codeberg.org/Mecrisp/FemtoMSP430

I am happy to announce the FemtoMSP430, a processor designed with the instruction set of the classic #MSP430, but with a flexible bus interface similar to @BrunoLevy01 #FemtoRV32 including memory busy signaling. The playground contains a phantasy "microcontroller" design for the #ULX3S #FPGA board, interactively running the original #Mecrisp #Forth image for MSP430G2755, enhanced with a text mode on 800x600 video, USB-CDC terminal and a lot of GPIO wires: https://codeberg.org/Mecrisp/FemtoMSP430

I am happy to announce the FemtoMSP430, a processor designed with the instruction set of the classic #MSP430, but with a flexible bus interface similar to @BrunoLevy01 #FemtoRV32 including memory busy signaling. The playground contains a phantasy "microcontroller" design for the #ULX3S #FPGA board, interactively running the original #Mecrisp #Forth image for MSP430G2755, enhanced with a text mode on 800x600 video, USB-CDC terminal and a lot of GPIO wires: https://codeberg.org/Mecrisp/FemtoMSP430

I am happy to announce the FemtoMSP430, a processor designed with the instruction set of the classic #MSP430, but with a flexible bus interface similar to @BrunoLevy01 #FemtoRV32 including memory busy signaling. The playground contains a phantasy "microcontroller" design for the #ULX3S #FPGA board, interactively running the original #Mecrisp #Forth image for MSP430G2755, enhanced with a text mode on 800x600 video, USB-CDC terminal and a lot of GPIO wires: https://codeberg.org/Mecrisp/FemtoMSP430

Following @WillFlux Isle Project. I've read and tested chapter 02 in the #radiona #ulx3s #fpga.
Now it's time to revise, study and tinker with it until he publishes the next chapter.
So much fun!!!!
https://projectf.io/isle/fpga-computer.html

I am happy to announce the release of a longwave software defined radio which I designed at work for experiments with #DSP algorithms, running on the #ULX3S #FPGA board. The user interface is based on #Mecrisp #Forth running on the #FemtoRV, and the signal chain contains a pipelined FFT designed by Dan Gisselquist. Many thanks to Ulixxe for their USB-CDC implementation!

https://github.com/mb-sat/ulx3s-longwave-sdr
https://codeberg.org/Mecrisp/ulx3s-longwave-sdr

I am happy to announce the release of a longwave software defined radio which I designed at work for experiments with #DSP algorithms, running on the #ULX3S #FPGA board. The user interface is based on #Mecrisp #Forth running on the #FemtoRV, and the signal chain contains a pipelined FFT designed by Dan Gisselquist. Many thanks to Ulixxe for their USB-CDC implementation!

https://github.com/mb-sat/ulx3s-longwave-sdr
https://codeberg.org/Mecrisp/ulx3s-longwave-sdr

I am happy to announce the release of a longwave software defined radio which I designed at work for experiments with #DSP algorithms, running on the #ULX3S #FPGA board. The user interface is based on #Mecrisp #Forth running on the #FemtoRV, and the signal chain contains a pipelined FFT designed by Dan Gisselquist. Many thanks to Ulixxe for their USB-CDC implementation!

https://github.com/mb-sat/ulx3s-longwave-sdr
https://codeberg.org/Mecrisp/ulx3s-longwave-sdr

I am happy to announce the release of a longwave software defined radio which I designed at work for experiments with #DSP algorithms, running on the #ULX3S #FPGA board. The user interface is based on #Mecrisp #Forth running on the #FemtoRV, and the signal chain contains a pipelined FFT designed by Dan Gisselquist. Many thanks to Ulixxe for their USB-CDC implementation!

https://github.com/mb-sat/ulx3s-longwave-sdr
https://codeberg.org/Mecrisp/ulx3s-longwave-sdr

I am happy to announce the release of a longwave software defined radio which I designed at work for experiments with #DSP algorithms, running on the #ULX3S #FPGA board. The user interface is based on #Mecrisp #Forth running on the #FemtoRV, and the signal chain contains a pipelined FFT designed by Dan Gisselquist. Many thanks to Ulixxe for their USB-CDC implementation!

https://github.com/mb-sat/ulx3s-longwave-sdr
https://codeberg.org/Mecrisp/ulx3s-longwave-sdr

OK this is pretty cool. A project called DigitalJS can give you a visual layout of all of the logic that'll go into a Verilog design, using Yosys to do the generation. Being able to see what's being ultimately produced helps me, a much more visual person, understand when I've flubbed something that generates too much logic. I already optimized one piece of the display RAM using it. It's at https://digitaljs.tilk.eu/ but you can also run it locally. #fpga #verilog #ulx3s

OK this is pretty cool. A project called DigitalJS can give you a visual layout of all of the logic that'll go into a Verilog design, using Yosys to do the generation. Being able to see what's being ultimately produced helps me, a much more visual person, understand when I've flubbed something that generates too much logic. I already optimized one piece of the display RAM using it. It's at https://digitaljs.tilk.eu/ but you can also run it locally. #fpga #verilog #ulx3s

I managed to get a 6502 CPU running on the ULX3S and wrote a 16 color indexed display RAM module for it. The CPU also has access to all the buttons and the LEDs, which are counting up the current low byte of display RAM. Its the most complex bit of Verilog I've written so far. I hope to add basic sound support next, and then I'll have made my own little toy console to mess with. #ulx3s #fpga #6502CPU

I managed to get a 6502 CPU running on the ULX3S and wrote a 16 color indexed display RAM module for it. The CPU also has access to all the buttons and the LEDs, which are counting up the current low byte of display RAM. Its the most complex bit of Verilog I've written so far. I hope to add basic sound support next, and then I'll have made my own little toy console to mess with. #ulx3s #fpga #6502CPU

Ive been having fun breaking out the ULX3S again. I finally managed to write my own code to drive the OLED display and show Topaz on the display, and got a 7 segment Pmod module working (nice). #fpga #ulx3s

Ive been having fun breaking out the ULX3S again. I finally managed to write my own code to drive the OLED display and show Topaz on the display, and got a 7 segment Pmod module working (nice). #fpga #ulx3s

My Earthrise #FPGA drawing engine rendering vector letters on #ULX3S dev board connected to 1024x768 LCD panel via Pimoroni controller board (handles HDMI to FPD-Link LVDS). 🌍

My Earthrise #FPGA drawing engine rendering vector letters on #ULX3S dev board connected to 1024x768 LCD panel via Pimoroni controller board (handles HDMI to FPD-Link LVDS). 🌍

Circle rendering. Nice and smooth, but there’s an issue with rendering at the top of the screen I need to look into. #FPGA #ULX3S

Circle rendering. Nice and smooth, but there’s an issue with rendering at the top of the screen I need to look into. #FPGA #ULX3S

Got a little time over the weekend to experiment a bit with my 2D graphics hardware. #FPGA #ULX3S