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#ulx3s — Public Fediverse posts

Live and recent posts from across the Fediverse tagged #ulx3s, aggregated by home.social.

  1. sylefeb @[email protected] ·

    At FCCM 2026 I saw a keynote by Onur Mutlu on abusing DRAM chip timings to have them perform vector (row) copies and even or/and/nand computations on entire rows, 'for free' (happens physically through capacitors charge). And this is on current, off-the-shelves DDR3/DDR4 memory!

    Well, I've got a bunch of great FPGA boards featuring good old SDRAM chips and ...

    It turns out RowClone is possible on older SDRAM chips!

    #FPGA #ULX3s #Silice

    #fpga #ulx3s #silice
  2. sylefeb @[email protected] ·

    Working on making PLLs easier to use in #Silice, here testing with a #ulx3s / ECP5 board. Four clocks of same frequency, phased out 90 degrees each. If you are wondering why the clock signals are not perfect ... check the wiring 😅 .

    #silice #ulx3s
  3. Goran_Mahovlic @[email protected] ·

    Well, there are for sure more #OpenHW options but than you #ChatGPT for making #ULX3S your first choice!

    #openhw #chatgpt #ulx3s