#ulx3s — Public Fediverse posts

The @RadionaOrg ULX3S hub site now honors device dark mode! Sunglasses no longer needed 😎

I also added a Tiny Tapeout section, as (pending a few Pull Request merges) @latticesemi #ECP5 FPGA support for testing your ASIC design on the #ULX3S is coming to @tinytapeout

The @RadionaOrg ULX3S hub site now honors device dark mode! Sunglasses no longer needed 😎

I also added a Tiny Tapeout section, as (pending a few Pull Request merges) @latticesemi #ECP5 FPGA support for testing your ASIC design on the #ULX3S is coming to @tinytapeout

@WillFlux

Thanks a lot for the new post! Works perfectly on the #Radiona #ulx3s #fpga

@WillFlux

Thanks a lot for the new post! Works perfectly on the #Radiona #ulx3s #fpga

I am happy to announce the FemtoMSP430, a processor designed with the instruction set of the classic #MSP430, but with a flexible bus interface similar to @BrunoLevy01 #FemtoRV32 including memory busy signaling. The playground contains a phantasy "microcontroller" design for the #ULX3S #FPGA board, interactively running the original #Mecrisp #Forth image for MSP430G2755, enhanced with a text mode on 800x600 video, USB-CDC terminal and a lot of GPIO wires: https://codeberg.org/Mecrisp/FemtoMSP430

I am happy to announce the FemtoMSP430, a processor designed with the instruction set of the classic #MSP430, but with a flexible bus interface similar to @BrunoLevy01 #FemtoRV32 including memory busy signaling. The playground contains a phantasy "microcontroller" design for the #ULX3S #FPGA board, interactively running the original #Mecrisp #Forth image for MSP430G2755, enhanced with a text mode on 800x600 video, USB-CDC terminal and a lot of GPIO wires: https://codeberg.org/Mecrisp/FemtoMSP430

I am happy to announce the FemtoMSP430, a processor designed with the instruction set of the classic #MSP430, but with a flexible bus interface similar to @BrunoLevy01 #FemtoRV32 including memory busy signaling. The playground contains a phantasy "microcontroller" design for the #ULX3S #FPGA board, interactively running the original #Mecrisp #Forth image for MSP430G2755, enhanced with a text mode on 800x600 video, USB-CDC terminal and a lot of GPIO wires: https://codeberg.org/Mecrisp/FemtoMSP430

I am happy to announce the FemtoMSP430, a processor designed with the instruction set of the classic #MSP430, but with a flexible bus interface similar to @BrunoLevy01 #FemtoRV32 including memory busy signaling. The playground contains a phantasy "microcontroller" design for the #ULX3S #FPGA board, interactively running the original #Mecrisp #Forth image for MSP430G2755, enhanced with a text mode on 800x600 video, USB-CDC terminal and a lot of GPIO wires: https://codeberg.org/Mecrisp/FemtoMSP430

I am happy to announce the FemtoMSP430, a processor designed with the instruction set of the classic #MSP430, but with a flexible bus interface similar to @BrunoLevy01 #FemtoRV32 including memory busy signaling. The playground contains a phantasy "microcontroller" design for the #ULX3S #FPGA board, interactively running the original #Mecrisp #Forth image for MSP430G2755, enhanced with a text mode on 800x600 video, USB-CDC terminal and a lot of GPIO wires: https://codeberg.org/Mecrisp/FemtoMSP430

Following @WillFlux Isle Project. I've read and tested chapter 02 in the #radiona #ulx3s #fpga.
Now it's time to revise, study and tinker with it until he publishes the next chapter.
So much fun!!!!
https://projectf.io/isle/fpga-computer.html

I am happy to announce the release of a longwave software defined radio which I designed at work for experiments with #DSP algorithms, running on the #ULX3S #FPGA board. The user interface is based on #Mecrisp #Forth running on the #FemtoRV, and the signal chain contains a pipelined FFT designed by Dan Gisselquist. Many thanks to Ulixxe for their USB-CDC implementation!

https://github.com/mb-sat/ulx3s-longwave-sdr
https://codeberg.org/Mecrisp/ulx3s-longwave-sdr

I am happy to announce the release of a longwave software defined radio which I designed at work for experiments with #DSP algorithms, running on the #ULX3S #FPGA board. The user interface is based on #Mecrisp #Forth running on the #FemtoRV, and the signal chain contains a pipelined FFT designed by Dan Gisselquist. Many thanks to Ulixxe for their USB-CDC implementation!

https://github.com/mb-sat/ulx3s-longwave-sdr
https://codeberg.org/Mecrisp/ulx3s-longwave-sdr

I am happy to announce the release of a longwave software defined radio which I designed at work for experiments with #DSP algorithms, running on the #ULX3S #FPGA board. The user interface is based on #Mecrisp #Forth running on the #FemtoRV, and the signal chain contains a pipelined FFT designed by Dan Gisselquist. Many thanks to Ulixxe for their USB-CDC implementation!

https://github.com/mb-sat/ulx3s-longwave-sdr
https://codeberg.org/Mecrisp/ulx3s-longwave-sdr

I am happy to announce the release of a longwave software defined radio which I designed at work for experiments with #DSP algorithms, running on the #ULX3S #FPGA board. The user interface is based on #Mecrisp #Forth running on the #FemtoRV, and the signal chain contains a pipelined FFT designed by Dan Gisselquist. Many thanks to Ulixxe for their USB-CDC implementation!

https://github.com/mb-sat/ulx3s-longwave-sdr
https://codeberg.org/Mecrisp/ulx3s-longwave-sdr

I am happy to announce the release of a longwave software defined radio which I designed at work for experiments with #DSP algorithms, running on the #ULX3S #FPGA board. The user interface is based on #Mecrisp #Forth running on the #FemtoRV, and the signal chain contains a pipelined FFT designed by Dan Gisselquist. Many thanks to Ulixxe for their USB-CDC implementation!

https://github.com/mb-sat/ulx3s-longwave-sdr
https://codeberg.org/Mecrisp/ulx3s-longwave-sdr

I started a project page to document my first FPGA project on a long while, mainly so that I don't forget, but could possibly be useful to others... I'll plan to add subsequent projects and make more progress on this one in the next few weeks and months.

"I bought myself a Radiona ULX3S from CrowdSupply, which includes the 85k Lattice ECP5 FPGA, which can be programmed to simulate the open source 32-bit RISC-V CPU with a completely open source LiteX-yosys-nextpnr, toolchain."

https://blog.bomorgan.io/hobbies/hardware/fpgas/litex-riscv-ecp5-ulx3s/

#riscv #foss #fpga #litex #yosys #nextpnr #linux #crowdsupply #radiona #ulx3s #lattice #ecp5

I started a project page to document my first FPGA project on a long while, mainly so that I don't forget, but could possibly be useful to others... I'll plan to add subsequent projects and make more progress on this one in the next few weeks and months.

"I bought myself a Radiona ULX3S from CrowdSupply, which includes the 85k Lattice ECP5 FPGA, which can be programmed to simulate the open source 32-bit RISC-V CPU with a completely open source LiteX-yosys-nextpnr, toolchain."

https://blog.bomorgan.io/hobbies/hardware/fpgas/litex-riscv-ecp5-ulx3s/

#riscv #foss #fpga #litex #yosys #nextpnr #linux #crowdsupply #radiona #ulx3s #lattice #ecp5

Packing #ULX3S for #Mouser

Packing #ULX3S for #Mouser

Packing #ULX3S for #Mouser

Well, there are for sure more #OpenHW options but than you #ChatGPT for making #ULX3S your first choice!

Well, there are for sure more #OpenHW options but than you #ChatGPT for making #ULX3S your first choice!

Got slack? I've got slaaaaaack! ⏳
#fpga #ulx3s #yosys

I am building a many core #Forth processor on Lattice Semiconductor FPGAs using the open source #Yosys tools. The first products released will be two 4 core processors. 16K* 16 bit words or 10.6K * 24 bit words. Every pair of processors will communicate using 10Kbits of dual port RAM. The processors will run on the $35 #PicoIce and $30 #Upduino boards. Later there will be hundreds of cores on the larger #ULX3S #ECP5 boards.

My climate persona: @UncensoredNews
#fpga #ManyCore #introduction