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#ulx3s — Public Fediverse posts

Live and recent posts from across the Fediverse tagged #ulx3s, aggregated by home.social.

  1. sylefeb @[email protected] ·

    At FCCM 2026 I saw a keynote by Onur Mutlu on abusing DRAM chip timings to have them perform vector (row) copies and even or/and/nand computations on entire rows, 'for free' (happens physically through capacitors charge). And this is on current, off-the-shelves DDR3/DDR4 memory!

    Well, I've got a bunch of great FPGA boards featuring good old SDRAM chips and ...

    It turns out RowClone is possible on older SDRAM chips!

    #FPGA #ULX3s #Silice

    #fpga #ulx3s #silice
  2. sylefeb @[email protected] ·

    At FCCM 2026 I saw a keynote by Onur Mutlu on abusing DRAM chip timings to have them perform vector (row) copies and even or/and/nand computations on entire rows, 'for free' (happens physically through capacitors charge). And this is on current, off-the-shelves DDR3/DDR4 memory!

    Well, I've got a bunch of great FPGA boards featuring good old SDRAM chips and ...

    It turns out RowClone is possible on older SDRAM chips!

    #FPGA #ULX3s #Silice

    #fpga #ulx3s #silice
  3. sylefeb @[email protected] ·

    At FCCM 2026 I saw a keynote by Onur Mutlu on abusing DRAM chip timings to have them perform vector (row) copies and even or/and/nand computations on entire rows, 'for free' (happens physically through capacitors charge). And this is on current, off-the-shelves DDR3/DDR4 memory!

    Well, I've got a bunch of great FPGA boards featuring good old SDRAM chips and ...

    It turns out RowClone is possible on older SDRAM chips!

    #FPGA #ULX3s #Silice

    #fpga #ulx3s #silice
  4. sylefeb @[email protected] ·

    At FCCM 2026 I saw a keynote by Onur Mutlu on abusing DRAM chip timings to have them perform vector (row) copies and even or/and/nand computations on entire rows, 'for free' (happens physically through capacitors charge). And this is on current, off-the-shelves DDR3/DDR4 memory!

    Well, I've got a bunch of great FPGA boards featuring good old SDRAM chips and ...

    It turns out RowClone is possible on older SDRAM chips!

    #FPGA #ULX3s #Silice

    #fpga #ulx3s #silice
  5. sylefeb @[email protected] ·

    At FCCM 2026 I saw a keynote by Onur Mutlu on abusing DRAM chip timings to have them perform vector (row) copies and even or/and/nand computations on entire rows, 'for free' (happens physically through capacitors charge). And this is on current, off-the-shelves DDR3/DDR4 memory!

    Well, I've got a bunch of great FPGA boards featuring good old SDRAM chips and ...

    It turns out RowClone is possible on older SDRAM chips!

    #FPGA #ULX3s #Silice

    #silice #ulx3s #fpga
  6. sylefeb @[email protected] ·

    Working on making PLLs easier to use in #Silice, here testing with a #ulx3s / ECP5 board. Four clocks of same frequency, phased out 90 degrees each. If you are wondering why the clock signals are not perfect ... check the wiring 😅 .

    #silice #ulx3s
  7. sylefeb @[email protected] ·

    Working on making PLLs easier to use in #Silice, here testing with a #ulx3s / ECP5 board. Four clocks of same frequency, phased out 90 degrees each. If you are wondering why the clock signals are not perfect ... check the wiring 😅 .

    #silice #ulx3s
  8. sylefeb @[email protected] ·

    Working on making PLLs easier to use in #Silice, here testing with a #ulx3s / ECP5 board. Four clocks of same frequency, phased out 90 degrees each. If you are wondering why the clock signals are not perfect ... check the wiring 😅 .

    #silice #ulx3s
  9. sylefeb @[email protected] ·

    Working on making PLLs easier to use in #Silice, here testing with a #ulx3s / ECP5 board. Four clocks of same frequency, phased out 90 degrees each. If you are wondering why the clock signals are not perfect ... check the wiring 😅 .

    #silice #ulx3s
  10. sylefeb @[email protected] ·

    Working on making PLLs easier to use in #Silice, here testing with a #ulx3s / ECP5 board. Four clocks of same frequency, phased out 90 degrees each. If you are wondering why the clock signals are not perfect ... check the wiring 😅 .

    #ulx3s #silice
  11. Flux @[email protected] ·

    The TMDS clock wasn't meeting timing on #ULX3S. There is so little logic in the clk_pix_5x domain I doubted I could do much. Then I realised each channel shared a small critical ring counter. Giving each colour channel its own added 100 MHz+ to the max frequency! #FPGA 🚀

    github.com/projf/isle/blob/mai

    #ulx3s #fpga
  12. Flux @[email protected] ·

    The TMDS clock wasn't meeting timing on #ULX3S. There is so little logic in the clk_pix_5x domain I doubted I could do much. Then I realised each channel shared a small critical ring counter. Giving each colour channel its own added 100 MHz+ to the max frequency! #FPGA 🚀

    github.com/projf/isle/blob/mai

    #ulx3s #fpga
  13. Flux @[email protected] ·

    The TMDS clock wasn't meeting timing on #ULX3S. There is so little logic in the clk_pix_5x domain I doubted I could do much. Then I realised each channel shared a small critical ring counter. Giving each colour channel its own added 100 MHz+ to the max frequency! #FPGA 🚀

    github.com/projf/isle/blob/mai

    #ulx3s #fpga
  14. Flux @[email protected] ·

    The TMDS clock wasn't meeting timing on #ULX3S. There is so little logic in the clk_pix_5x domain I doubted I could do much. Then I realised each channel shared a small critical ring counter. Giving each colour channel its own added 100 MHz+ to the max frequency! #FPGA 🚀

    github.com/projf/isle/blob/mai

    #ulx3s #fpga
  15. Flux @[email protected] ·

    The TMDS clock wasn't meeting timing on #ULX3S. There is so little logic in the clk_pix_5x domain I doubted I could do much. Then I realised each channel shared a small critical ring counter. Giving each colour channel its own added 100 MHz+ to the max frequency! #FPGA 🚀

    github.com/projf/isle/blob/mai

    #fpga #ulx3s
  16. Flux @[email protected] ·

    Made some time for 🏝️ Isle.Computer today. Getting the graphics registers working across clock domains so the CPU can double buffer, scroll, adjust transparency etc. #FPGA

    Images show RISC-V CPU reading graphics registers in sim and on #ULX3S.

    #fpga #ulx3s
  17. Flux @[email protected] ·

    Made some time for 🏝️ Isle.Computer today. Getting the graphics registers working across clock domains so the CPU can double buffer, scroll, adjust transparency etc. #FPGA

    Images show RISC-V CPU reading graphics registers in sim and on #ULX3S.

    #fpga #ulx3s
  18. Flux @[email protected] ·

    Made some time for 🏝️ Isle.Computer today. Getting the graphics registers working across clock domains so the CPU can double buffer, scroll, adjust transparency etc. #FPGA

    Images show RISC-V CPU reading graphics registers in sim and on #ULX3S.

    #fpga #ulx3s
  19. Flux @[email protected] ·

    Made some time for 🏝️ Isle.Computer today. Getting the graphics registers working across clock domains so the CPU can double buffer, scroll, adjust transparency etc. #FPGA

    Images show RISC-V CPU reading graphics registers in sim and on #ULX3S.

    #fpga #ulx3s
  20. Flux @[email protected] ·

    Made some time for 🏝️ Isle.Computer today. Getting the graphics registers working across clock domains so the CPU can double buffer, scroll, adjust transparency etc. #FPGA

    Images show RISC-V CPU reading graphics registers in sim and on #ULX3S.

    #ulx3s #fpga
  21. gojimmypi @[email protected] ·

    The @RadionaOrg ULX3S hub site now honors device dark mode! Sunglasses no longer needed 😎

    I also added a Tiny Tapeout section, as (pending a few Pull Request merges) @latticesemi #ECP5 FPGA support for testing your ASIC design on the #ULX3S is coming to @tinytapeout

    #ecp5 #ulx3s
  22. gojimmypi @[email protected] ·

    The @RadionaOrg ULX3S hub site now honors device dark mode! Sunglasses no longer needed 😎

    I also added a Tiny Tapeout section, as (pending a few Pull Request merges) @latticesemi #ECP5 FPGA support for testing your ASIC design on the #ULX3S is coming to @tinytapeout

    #ecp5 #ulx3s
  23. gojimmypi @[email protected] ·

    The @RadionaOrg ULX3S hub site now honors device dark mode! Sunglasses no longer needed 😎

    I also added a Tiny Tapeout section, as (pending a few Pull Request merges) @latticesemi #ECP5 FPGA support for testing your ASIC design on the #ULX3S is coming to @tinytapeout

    #ecp5 #ulx3s
  24. gojimmypi @[email protected] ·

    The @RadionaOrg ULX3S hub site now honors device dark mode! Sunglasses no longer needed 😎

    I also added a Tiny Tapeout section, as (pending a few Pull Request merges) @latticesemi #ECP5 FPGA support for testing your ASIC design on the #ULX3S is coming to @tinytapeout

    #ecp5 #ulx3s
  25. gojimmypi @[email protected] ·

    The @RadionaOrg ULX3S hub site now honors device dark mode! Sunglasses no longer needed 😎

    I also added a Tiny Tapeout section, as (pending a few Pull Request merges) @latticesemi #ECP5 FPGA support for testing your ASIC design on the #ULX3S is coming to @tinytapeout

    #ulx3s #ecp5
  26. Flux @[email protected] ·

    You can find the source code on GitHub (I'm considering moving to Codeberg): github.com/projf/isle

    Includes everything you need for:
    * @machdyne Lakritz (Lattice ECP5)
    * Digilent Nexys Video (Xilinx XC7)
    * Radiona #ULX3S (Lattice ECP5)
    * Verilator simulator with SDL (Linux/macOS/Windows)

    #ulx3s
  27. Flux @[email protected] ·

    You can find the source code on GitHub (I'm considering moving to Codeberg): github.com/projf/isle

    Includes everything you need for:
    * @machdyne Lakritz (Lattice ECP5)
    * Digilent Nexys Video (Xilinx XC7)
    * Radiona #ULX3S (Lattice ECP5)
    * Verilator simulator with SDL (Linux/macOS/Windows)

    #ulx3s
  28. Flux @[email protected] ·

    You can find the source code on GitHub (I'm considering moving to Codeberg): github.com/projf/isle

    Includes everything you need for:
    * @machdyne Lakritz (Lattice ECP5)
    * Digilent Nexys Video (Xilinx XC7)
    * Radiona #ULX3S (Lattice ECP5)
    * Verilator simulator with SDL (Linux/macOS/Windows)

    #ulx3s
  29. Flux @[email protected] ·

    You can find the source code on GitHub (I'm considering moving to Codeberg): github.com/projf/isle

    Includes everything you need for:
    * @machdyne Lakritz (Lattice ECP5)
    * Digilent Nexys Video (Xilinx XC7)
    * Radiona #ULX3S (Lattice ECP5)
    * Verilator simulator with SDL (Linux/macOS/Windows)

    #ulx3s
  30. Flux @[email protected] ·

    You can find the source code on GitHub (I'm considering moving to Codeberg): github.com/projf/isle

    Includes everything you need for:
    * @machdyne Lakritz (Lattice ECP5)
    * Digilent Nexys Video (Xilinx XC7)
    * Radiona #ULX3S (Lattice ECP5)
    * Verilator simulator with SDL (Linux/macOS/Windows)

    #ulx3s
  31. Flux @[email protected] ·

    Board testing in advance of #FPGAFriday. The answer was 42. #ULX3S

    #fpgafriday #ulx3s
  32. Flux @[email protected] ·

    Board testing in advance of #FPGAFriday. The answer was 42. #ULX3S

    #ulx3s #fpgafriday
  33. Flux @[email protected] ·

    Board testing in advance of #FPGAFriday. The answer was 42. #ULX3S

    #fpgafriday #ulx3s
  34. Flux @[email protected] ·

    Board testing in advance of #FPGAFriday. The answer was 42. #ULX3S

    #fpgafriday #ulx3s
  35. Flux @[email protected] ·

    Board testing in advance of #FPGAFriday. The answer was 42. #ULX3S

    #ulx3s #fpgafriday
  36. Flux @[email protected] ·

    And a quick lunchtime shot of 🏝️ Isle.Computer running on #ULX3S.

    Simulation may be practical for software dev, but it feels so much better seeing it running on real hardware. This is #riscv asm decoding UTF-8 sent over UART to Isle hardware running on #fpga. Verilog and asm written by hand. 😊

    #ulx3s #riscv #fpga
  37. Flux @[email protected] ·

    And a quick lunchtime shot of 🏝️ Isle.Computer running on #ULX3S.

    Simulation may be practical for software dev, but it feels so much better seeing it running on real hardware. This is #riscv asm decoding UTF-8 sent over UART to Isle hardware running on #fpga. Verilog and asm written by hand. 😊

    #ulx3s #riscv #fpga
  38. Flux @[email protected] ·

    And a quick lunchtime shot of 🏝️ Isle.Computer running on #ULX3S.

    Simulation may be practical for software dev, but it feels so much better seeing it running on real hardware. This is #riscv asm decoding UTF-8 sent over UART to Isle hardware running on #fpga. Verilog and asm written by hand. 😊

    #ulx3s #riscv #fpga
  39. Flux @[email protected] ·

    And a quick lunchtime shot of 🏝️ Isle.Computer running on #ULX3S.

    Simulation may be practical for software dev, but it feels so much better seeing it running on real hardware. This is #riscv asm decoding UTF-8 sent over UART to Isle hardware running on #fpga. Verilog and asm written by hand. 😊

    #ulx3s #riscv #fpga
  40. Flux @[email protected] ·

    And a quick lunchtime shot of 🏝️ Isle.Computer running on #ULX3S.

    Simulation may be practical for software dev, but it feels so much better seeing it running on real hardware. This is #riscv asm decoding UTF-8 sent over UART to Isle hardware running on #fpga. Verilog and asm written by hand. 😊

    #fpga #riscv #ulx3s
  41. Flux @[email protected] ·

    Work on 🏝️ Isle #FPGA computer input chapter continues. Here I’m testing UART with #ULX3S dev board.

    #fpga #ulx3s
  42. Flux @[email protected] ·

    Work on 🏝️ Isle #FPGA computer input chapter continues. Here I’m testing UART with #ULX3S dev board.

    #fpga #ulx3s
  43. Flux @[email protected] ·

    Work on 🏝️ Isle #FPGA computer input chapter continues. Here I’m testing UART with #ULX3S dev board.

    #fpga #ulx3s
  44. Flux @[email protected] ·

    Work on 🏝️ Isle #FPGA computer input chapter continues. Here I’m testing UART with #ULX3S dev board.

    #fpga #ulx3s
  45. Flux @[email protected] ·

    Work on 🏝️ Isle #FPGA computer input chapter continues. Here I’m testing UART with #ULX3S dev board.

    #ulx3s #fpga
  46. Flux @[email protected] ·

    You can find the open-source designs and instructions for 🏝️ Isle FPGA computer at: github.com/projf/isle

    You can run Isle on Linux/Mac/Windows under simulation, and it's really easy to set up.

    Plus, there's board support #ULX3S, @machdyne Lakritz, and Digilent Nexys Video.

    #ulx3s
  47. Flux @[email protected] ·

    You can find the open-source designs and instructions for 🏝️ Isle FPGA computer at: github.com/projf/isle

    You can run Isle on Linux/Mac/Windows under simulation, and it's really easy to set up.

    Plus, there's board support #ULX3S, @machdyne Lakritz, and Digilent Nexys Video.

    #ulx3s
  48. Flux @[email protected] ·

    You can find the open-source designs and instructions for 🏝️ Isle FPGA computer at: github.com/projf/isle

    You can run Isle on Linux/Mac/Windows under simulation, and it's really easy to set up.

    Plus, there's board support #ULX3S, @machdyne Lakritz, and Digilent Nexys Video.

    #ulx3s
  49. Flux @[email protected] ·

    You can find the open-source designs and instructions for 🏝️ Isle FPGA computer at: github.com/projf/isle

    You can run Isle on Linux/Mac/Windows under simulation, and it's really easy to set up.

    Plus, there's board support #ULX3S, @machdyne Lakritz, and Digilent Nexys Video.

    #ulx3s
  50. Flux @[email protected] ·

    You can find the open-source designs and instructions for 🏝️ Isle FPGA computer at: github.com/projf/isle

    You can run Isle on Linux/Mac/Windows under simulation, and it's really easy to set up.

    Plus, there's board support #ULX3S, @machdyne Lakritz, and Digilent Nexys Video.

    #ulx3s