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#silice — Public Fediverse posts

Live and recent posts from across the Fediverse tagged #silice, aggregated by home.social.

  1. Working on making PLLs easier to use in #Silice, here testing with a #ulx3s / ECP5 board. Four clocks of same frequency, phased out 90 degrees each. If you are wondering why the clock signals are not perfect ... check the wiring 😅 .

  2. #Perseverance a atterri sur #Mars voici 5 ans, durant lesquels les scientifiques de l'IRAP et les ingénieurs du @cnes n'ont cessé de collaborer, en liaison avec leur homologues états-uniens, afin de définir la meilleure trajectoire, les cibles les plus intéressantes. Se sont ensuivis de magnifiques moments de partage, de joie, lors de la découverte de nouveaux #paysages, de #minéraux riches en #carbone, en #silice etc.

    Une formidable épopée, racontée par ses acteurs : cnes.fr/actualites/supercam-5-

  3. Nearing a #Silice main branch update, testing a5k and it still just works! This is a complete hardware implementation of Another World's VM on FPGA, here running on the mighty #mch2022 badge.

    a5k repo + write up: github.com/sylefeb/a5k
    Silice: github.com/sylefeb/Silice/

  4. Congrats @destevez, well deserved for #MaiaSDR !

    Meanwhile @BrunoLevy01 and @sylefeb this might be of interest to you as, during the #SDR Academy conference ( #sdra 2023.sdra.io/ ), they also call for more #FPGA people to submit for next year. A bit like when you Sylvain have presented #Silice to South Indian SDR User Group (SI-SDR-UG) youtu.be/fr4Dst1fQrk?t=10554