#silice — Public Fediverse posts

At FCCM 2026 I saw a keynote by Onur Mutlu on abusing DRAM chip timings to have them perform vector (row) copies and even or/and/nand computations on entire rows, 'for free' (happens physically through capacitors charge). And this is on current, off-the-shelves DDR3/DDR4 memory!

Well, I've got a bunch of great FPGA boards featuring good old SDRAM chips and ...

It turns out RowClone is possible on older SDRAM chips!

#FPGA #ULX3s #Silice

Working on making PLLs easier to use in #Silice, here testing with a #ulx3s / ECP5 board. Four clocks of same frequency, phased out 90 degrees each. If you are wondering why the clock signals are not perfect ... check the wiring 😅 .

This is the basic #Silice VGA test, somewhat of a tradition, I always start there when adding a new board. Who's new in this list ? Yes! Working on integrating the GateMate A1 evaluation board! Stay tuned for more info soon. #CologneChips #GateMate

#Perseverance a atterri sur #Mars voici 5 ans, durant lesquels les scientifiques de l'IRAP et les ingénieurs du @cnes n'ont cessé de collaborer, en liaison avec leur homologues états-uniens, afin de définir la meilleure trajectoire, les cibles les plus intéressantes. Se sont ensuivis de magnifiques moments de partage, de joie, lors de la découverte de nouveaux #paysages, de #minéraux riches en #carbone, en #silice etc.

Une formidable épopée, racontée par ses acteurs : https://cnes.fr/actualites/supercam-5-ans-de-cooperation-scientifique-technique-percer-secrets-de-mars

SILICE: Un sistema abierto y transparente para la información científica en España

📰 Título original: Caminando hacia sistemas de información científica abiertos e independientes: el caso pionero de SILICE

🤖 IA: No es clickbait ✅
👥 Usuarios: No es clickbait ✅

Ver resumen IA completo: https://killbait.com/es/silice-un-sistema-abierto-y-transparente-para-la-informacion-cientifica-en-espana/?redirpost=33164ea3-000c-41d5-a729-94b2bbf93604

#ciencia #accesoabierto #bibliometría #silice

WolFPGA on the icepi-zero! Works great!! (#Wolfenstein raycaster on #FPGA, no CPU, pure graphics, in #Silice)

It is a very neat board, packed with features. Just started to play with it today, but looking forward to explore it further (Silice main branch already has support, check it out!).

Crowd funding still open for a few hours, check it out :
https://www.crowdsupply.com/icy-electronics/icepi-zero

Now I leave the floor to @sylefeb. Next lessons: the #silice language !
https://github.com/sylefeb/Silice

#Silice now has preliminary support for @whitequark YoWASP!
Checkout Silice getting started instructions here:

https://github.com/sylefeb/Silice/blob/draft/GetStarted_YoWASP.md

(draft branch)

pip install yowasp-silice !

[Un système hydrothermal sur #Mars] Dans les roches qui délimitent le cratère d'impact Jézéro, l'ensemble instrumental du rover #Pereverance a détecté la présence de #silice sous différentes formes : de l'opale, de la calcédoine, et du #quartz. Preuve d’une interaction eau-roche datant du tout début de l’histoire de la planète rouge ....

Sachant que les roches siliceuses - l'opale notamment, ont des capacités remarquables à préserver les traces de #vie, ne reste plus qu'à échantillonner ces roches puis à les rapporter sur Terre pour effectuer des analyses exobiologiques plus poussées.

Info+ : https://www.irap.omp.eu/2025/03/du-quartz-decouvert-pour-la-premiere-fois-sur-mars-par-le-robot-perseverance-qui-atteste-danciennes-circulations-deau-sur-la-planete-rouge/

Nearing a #Silice main branch update, testing a5k and it still just works! This is a complete hardware implementation of Another World's VM on FPGA, here running on the mighty #mch2022 badge.

a5k repo + write up: https://github.com/sylefeb/a5k
Silice: https://github.com/sylefeb/Silice/

2/ To me, this is crazy ; when I started on #FPGA and #Silice back in 2018 I never *dreamed* of one day having my own design on silicon. Thanks #tinytapeout, @matthewvenn, and everyone involved who makes this possible!

https://tinytapeout.com/

1/ It freaking works!!! First #ASIC designed with #Silice renders a terrain!!!!! 🎉 🎉 🎉

-> production #couleur #vert Malachite = pierre verte composée de carbonate de #cuivre -> réduite en poudre -> mélangée à résine ou de la graisse pour être appliquée sur les paupières (cf -1900 av. JC).
-> production pigment lapis-lazulli = #bleu égyptien en chauffant #silice avec malachite et carbonate de calcium -> utilisation sur papyrus et poterie.

Chine -> fin des Majiayao (cf 3 300 av JC).

If you feel adventurous and want to try both #tinytapeout (your own ASIC chip!) and #Silice I prepared a template for tt09 (61 days to go!).

https://github.com/sylefeb/tt09-silice-template

Be warned: I am waiting for my tt07 and tt08 designs to come back to realize my mistakes 😅 .

I followed the #tinytapeout approach of doing the entire synthesis in github actions, with Silice seamlessly integrated in the mix. Write your code, commit+push, and get back an ASIC design ready to submit!

#Silice syntax highlight is now available as a vscode extension!

https://marketplace.visualstudio.com/items?itemName=sylefeb.silice

2/ The design is written in #Silice and exported to Verilog, and then synthesized to #ASIC through the amazing #TinyTapeout framework.
The terrain renderer fits on only two tiles, using some tricks 😎. Write-up pending.

https://github.com/sylefeb/Silice

Just updated the hardware #Silice version of HumanShader (https://humanshader.com/) by Inigo Quilez. Inigo made a new animated version just for us #fpga addicts 👍 .

This is racing the beam, pipelined, no CPU. The code is very, very compact so it makes it a great exercise to put in hardware.

Shadertoy: https://www.shadertoy.com/view/4ft3Wn
Silice code: https://github.com/sylefeb/Silice/blob/wip/projects/vga_demo/vga_humanshader.si

3/3 If you are interested the entire classroom is documented in the #Silice repository. Learn about @risc_v SOC design and audio PWM. Have fun designing hardware on #fpga!

https://github.com/sylefeb/Silice/tree/master/learn-silice/classroom/soc_wave_player

1/3 This year again our students @telecomnancy did a great job writing a wave player SOC on #fpga with #Silice! (cc BrunoLevy01)

Also, I can only approve their choice of sound tracks 😋 (in general I got to discover many new music styles, thanks to all for this!)

4/ I added some notes on how each effect was implemented in hardware on #fpga with links to #Silice designs.

https://github.com/sylefeb/gfxcat

1/ My collection of cool little graphics effects, all revisited in simple C with a minimal framework. They run in the browser! (link next)

Made for my #Silice #fpga projects, they should be fun and easy to port on your @risc_v SOC, @Raspberry_Pi project or as a #shader.

How I remade Another World / Out of This World in hardware on the UP5K #fpga. Thread! ⬇️

Detailed write up and full #Silice design release! Includes bitstreams for icebreaker, mch2022, and a bonus board ;)

➡️ https://github.com/sylefeb/a5k

Congrats @destevez, well deserved for #MaiaSDR !

Meanwhile @BrunoLevy01 and @sylefeb this might be of interest to you as, during the #SDR Academy conference ( #sdra https://2023.sdra.io/ ), they also call for more #FPGA people to submit for next year. A bit like when you Sylvain have presented #Silice to South Indian SDR User Group (SI-SDR-UG) https://youtu.be/fr4Dst1fQrk?t=10554

And what do you do with a 1280 LUTs #fpga and 32MB of memory? You run Doom of course!!

This is *very* slow (~0.3 FPS). But it shows that given enough RAM and time, even a small CPU can do a lot!

Uses machydine QQSPI pmod and @tnt fabulous doom-riscv port. The design is in #Silice.

Source code + bitstream in the #Silice repo (wip branch for now). Hope you'll find it useful!

https://github.com/sylefeb/Silice/tree/wip/projects/qpsram

a5k: Another World hardware VM on the ice40 UP5K #fpga (5280 LUTs, 128KB spram), now running and playable on the magnificent #mch2022 badge!

Hard to capture, but it looks great. Really fun to play in this format.

(written in #Silice)

I just refreshed the dedicated repo to match latest #Silice changes.

https://github.com/sylefeb/mch2022-silice/

The #Silice pipeline documentation is nearing completion with the new section on pipelines within algorithms: https://github.com/sylefeb/Silice/blob/draft/learn-silice/Documentation.md#pipelines-in-algorithm

This is a powerful feature that lets you start pipelines in parallel, start them within loops, and have multi-cycle pipeline stages.