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39 results for “BrunoLevy01”
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@yrabbit @BrunoLevy01 I did not know, you are doing great! It seems as you are directly diving from the intro course into leisurely conquering a new arch, discovering sizecoding while at it :-) See you next time at the #Lovebyte demoparty!
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Sharing this I saw on twitter by BrunoLevy01:
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The simple #femtorv-quark takes no more than 200 lines of VERILOG. Yes, it is the complete description of a risc-v processor, that can run C programs compiled with gcc-riscv
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The #FemtoRV Quark, a small #RISCV RV32I core developed by @BrunoLevy01 and me has been implemented in silicon by a team from Brazil:
https://github.com/FelipeFFerreira/ITA-CORESVery happy about that!
See the original processor source here:
https://github.com/BrunoLevy/learn-fpga/blob/master/FemtoRV/RTL/PROCESSOR/femtorv32_quark.v
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Congrats @destevez, well deserved for #MaiaSDR !
Meanwhile @BrunoLevy01 and @sylefeb this might be of interest to you as, during the #SDR Academy conference ( #sdra https://2023.sdra.io/ ), they also call for more #FPGA people to submit for next year. A bit like when you Sylvain have presented #Silice to South Indian SDR User Group (SI-SDR-UG) https://youtu.be/fr4Dst1fQrk?t=10554
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I am happy to announce the FemtoMSP430, a processor designed with the instruction set of the classic #MSP430, but with a flexible bus interface similar to @BrunoLevy01 #FemtoRV32 including memory busy signaling. The playground contains a phantasy "microcontroller" design for the #ULX3S #FPGA board, interactively running the original #Mecrisp #Forth image for MSP430G2755, enhanced with a text mode on 800x600 video, USB-CDC terminal and a lot of GPIO wires: https://codeberg.org/Mecrisp/FemtoMSP430
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Found an excellent walkthrough video https://www.youtube.com/watch?v=8boamDdvD8s for the #FemtoRV-Quark https://github.com/BrunoLevy/learn-fpga/blob/master/FemtoRV/RTL/PROCESSOR/femtorv32_quark.v code! @BrunoLevy01 and me did our very best to make the Verilog source of our #RISCV RV32I processor core readable, and this video explains all the tricks involved in a very nice style with drawings.
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Went with another classic, the dragon statue.
This shows triangulated surface remeshing using a (very basic) #JuliaLang wrapper for @BrunoLevy01 et al.'s fantastic Geogram library (https://github.com/BrunoLevy/geogram).
#GeometryProcessing #Meshing #ComputationalMechanics #ComputationalDesign
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Went with another classic, the dragon statue.
This shows triangulated surface remeshing using a (very basic) #JuliaLang wrapper for @BrunoLevy01 et al.'s fantastic Geogram library (https://github.com/BrunoLevy/geogram).
#GeometryProcessing #Meshing #ComputationalMechanics #ComputationalDesign
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Went with another classic, the dragon statue.
This shows triangulated surface remeshing using a (very basic) #JuliaLang wrapper for @BrunoLevy01 et al.'s fantastic Geogram library (https://github.com/BrunoLevy/geogram).
#GeometryProcessing #Meshing #ComputationalMechanics #ComputationalDesign
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Went with another classic, the dragon statue.
This shows triangulated surface remeshing using a (very basic) #JuliaLang wrapper for @BrunoLevy01 et al.'s fantastic Geogram library (https://github.com/BrunoLevy/geogram).
#GeometryProcessing #Meshing #ComputationalMechanics #ComputationalDesign
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The space mission MAIUS-2 I wrote firmware for since 2019 launched in November 2023, and I am now open for new paid projects! My favourites are #Assembler, #Forth and #Verilog on #FPGA. I am the author of #Mecrisp, a family of optimising Forth compilers (Mecrisp-Ice went to space!), did processor design with @BrunoLevy01 (#FemtoRV Gracilis) and I love #sizecoding challenges (Byte-Athlon Champion in #Lovebyte 2023). Formally, I am Dr. rer. nat. in biophysics with experience in laser spectroscopy.
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Four RV32I @risc_v cores totaling ~333M IPS do work with a 480p frame buffer 🤓. 20 threads, ~software rendering, but focus isn't on CPU core, next up: experiments with custom accelerator pipelines to offload compute 😏 #PipelineC
#FPGA #HDL #RTL #graphics #RISCV Thanks @BrunoLevy01 and friends! -
Under the hood: HUGE Laguerre diagrams (fig 1), used to compute the large sparse matrices (fig 2). Grid 5000/SLICES has nice "pocket calculators" (fig 3), so we played with them and obtained interesting timings (fig 4) on a smaller problem (120 million points). Can we do even better ? More to come.
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Working on Scalable Optimal Transport with R. Mohayaee, C. Dapogny and E. Oudet:
more than 1 billion particles !
➡️ use algebraic multigrid preconditioner (AMGCL)
➡️ rewrite GPU backend: no limit on matrix size, supports multi-GPU !
➡️ Available in OpenNL: https://github.com/BrunoLevy/OpenNL -
This chip is special,
(https://tinytapeout.com/chips/ttsky25b/)- it has designs made by hobbyists
- and, more importantly, it has two #FemtoRV designs in it !!
- these two FemtoRV designs were authored by othersWhat is FemtoRV ? It is a super simple RiscV processor that we designed with @Mecrisp because we were boring during COVID...),
More information here:
https://github.com/BrunoLevy/learn-fpga/I am super excited, can't wait to see whether these 200 lines of VERILOG can be turned into a real Risc-V CPU on a chip !
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I was considering tinkering with #femtorv to make it run on the device, but it seems that others already did it, it is part of the Apicula examples, here:
https://github.com/YosysHQ/apicula/blob/master/examples/femto-riscv-18.v
I'll try that tomorrow (let us call it a day for now) -
The traditional blinky was easy, let us see whether #femtorv flies...
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Now I leave the floor to @sylefeb. Next lessons: the #silice language !
https://github.com/sylefeb/Silice -
I heard it said that cats have several lifes (maybe even more than that if it is Schroedinger's cat), but did you know that it is also the case of #femtorv ?
A project that fits four femtorv's on a Zinq #FPGA and run four games of life with them:
https://hackaday.io/project/191082-multi-gameoflife -
OMG, it is possible to run RUST programs on #femtorv !
Just found @antvangelder''s repo here:
https://github.com/antoinevg/hello-amaranth/blob/main/hello-femtorv/examples/blinky.rs -
Working on a more elementary #femtorv, with a 4-bits ALU (a-la QERV). Goal is to minimize LUT count, minimize number of lines of Verilog and have high maxfreq. Performance will be low (but I do not care !). For now, trying different designs on paper.
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On the left: floorplan of #femtorv-quark on the #ULX3S (85Kluts variant). On the right, floorplan of "Tordboyau", pipelined with branch prediction. The right one is nearly 5 times faster than the left one, because
(but eats-up a larger portion of the ECP5).
Regarding source-code, the left one weights 200 lines (https://github.com/BrunoLevy/learn-fpga/blob/master/FemtoRV/TUTORIALS/FROM_BLINKER_TO_RISCV/step18.v) and the right one around 800 lines (https://github.com/BrunoLevy/TordBoyau/blob/main/TordBoyau5.v) -
Fantastic version of the well-known "donut" demo,
Andy Sloane came out with a super-fast integer-only version (using the CORDIC algorithm):
https://gist.github.com/a1k0n/8ea6516b4946ab36348fb61703dc3194
You can do raytracing with adds and shifts ! (mul is not even needed)
Playing with it a little bit (my version with double-vertical resolution RGB rendering in the terminal)
It is a good test for @risc_v softcores, #fpga pipelined beam surfers and #femtorv ! (cc @sylefeb ) -
@MichaelJBrodeur I have played with both Ice40, ECP5 and Xilinx-based boards, all of them work, and you'll be able to run Episode 1 on everything. Now for Episode 2 (pipeline) the smallest Ice40 FPGAs will be too small.
For episode 1, if you can do a blinky, you can do #femtorv (except if you are smaller than an Ice40 Hx1K) -
learn-fpga, the tutorial to create @risc_v
cores such as #femtorv on #fpga is approaching 2K stars on github !
https://github.com/BrunoLevy/learn-fpga
