#femtorv — Public Fediverse posts
Live and recent posts from across the Fediverse tagged #femtorv, aggregated by home.social.
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One of them was done by @rebelmike and is a SoC based off @BrunoLevy01 's #FemtoRV . This runs nicely (up to 80 MHz even if STA says 50 😅 ) and I was able to get a hello world and a minimal port of #micropython on it .
Another is the @splinedrive KianV uLinux SoC that's on several other TT chips and was quickly adapted by Uri Shaked and myself to the register file.
I however screwed up when doing that ...
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This chip is special,
(https://tinytapeout.com/chips/ttsky25b/)- it has designs made by hobbyists
- and, more importantly, it has two #FemtoRV designs in it !!
- these two FemtoRV designs were authored by othersWhat is FemtoRV ? It is a super simple RiscV processor that we designed with @Mecrisp because we were boring during COVID...),
More information here:
https://github.com/BrunoLevy/learn-fpga/I am super excited, can't wait to see whether these 200 lines of VERILOG can be turned into a real Risc-V CPU on a chip !
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I was considering tinkering with #femtorv to make it run on the device, but it seems that others already did it, it is part of the Apicula examples, here:
https://github.com/YosysHQ/apicula/blob/master/examples/femto-riscv-18.v
I'll try that tomorrow (let us call it a day for now) -
The traditional blinky was easy, let us see whether #femtorv flies...
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I am happy to announce the release of a longwave software defined radio which I designed at work for experiments with #DSP algorithms, running on the #ULX3S #FPGA board. The user interface is based on #Mecrisp #Forth running on the #FemtoRV, and the signal chain contains a pipelined FFT designed by Dan Gisselquist. Many thanks to Ulixxe for their USB-CDC implementation!
https://github.com/mb-sat/ulx3s-longwave-sdr
https://codeberg.org/Mecrisp/ulx3s-longwave-sdr -
@alios Mit dem Gedanken habe ich auch schon einige Male gespielt... Ein möglicher Ansatz wäre: Du schnappst Dir den #FemtoRV Quark und modifizierst ihn so, dass der Programmzähler, wenn die Adresse in einem besonderen IO-Bereich liegt, nicht weiterzählt, und beim Reset mit dem Lesen einer Instruktion von einer solchen speziellen IO-Adresse beginnt.
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I am looking for a #riscv #FPGA soft core which uses large muliplexers to do ALU math in a single clock cycle. It is for the #gatemate FPGA. GateMate has large 8 input multiplexers which only need two layers to choose between 32 registers.
There are so many RISC-V soft cores it is hard to know which one to choose. On smaller FPGAs, some soft cores like the #FemtoRV store the registers in memory, so first they have to load 2 registers.
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Found an excellent walkthrough video https://www.youtube.com/watch?v=8boamDdvD8s for the #FemtoRV-Quark https://github.com/BrunoLevy/learn-fpga/blob/master/FemtoRV/RTL/PROCESSOR/femtorv32_quark.v code! @BrunoLevy01 and me did our very best to make the Verilog source of our #RISCV RV32I processor core readable, and this video explains all the tricks involved in a very nice style with drawings.
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The space mission MAIUS-2 I wrote firmware for since 2019 launched in November 2023, and I am now open for new paid projects! My favourites are #Assembler, #Forth and #Verilog on #FPGA. I am the author of #Mecrisp, a family of optimising Forth compilers (Mecrisp-Ice went to space!), did processor design with @BrunoLevy01 (#FemtoRV Gracilis) and I love #sizecoding challenges (Byte-Athlon Champion in #Lovebyte 2023). Formally, I am Dr. rer. nat. in biophysics with experience in laser spectroscopy.
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I heard it said that cats have several lifes (maybe even more than that if it is Schroedinger's cat), but did you know that it is also the case of #femtorv ?
A project that fits four femtorv's on a Zinq #FPGA and run four games of life with them:
https://hackaday.io/project/191082-multi-gameoflife -
OMG, it is possible to run RUST programs on #femtorv !
Just found @antvangelder''s repo here:
https://github.com/antoinevg/hello-amaranth/blob/main/hello-femtorv/examples/blinky.rs -
Working on a more elementary #femtorv, with a 4-bits ALU (a-la QERV). Goal is to minimize LUT count, minimize number of lines of Verilog and have high maxfreq. Performance will be low (but I do not care !). For now, trying different designs on paper.
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The #FemtoRV Quark, a small #RISCV RV32I core developed by @BrunoLevy01 and me has been implemented in silicon by a team from Brazil:
https://github.com/FelipeFFerreira/ITA-CORESVery happy about that!
See the original processor source here:
https://github.com/BrunoLevy/learn-fpga/blob/master/FemtoRV/RTL/PROCESSOR/femtorv32_quark.v
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On the left: floorplan of #femtorv-quark on the #ULX3S (85Kluts variant). On the right, floorplan of "Tordboyau", pipelined with branch prediction. The right one is nearly 5 times faster than the left one, because
(but eats-up a larger portion of the ECP5).
Regarding source-code, the left one weights 200 lines (https://github.com/BrunoLevy/learn-fpga/blob/master/FemtoRV/TUTORIALS/FROM_BLINKER_TO_RISCV/step18.v) and the right one around 800 lines (https://github.com/BrunoLevy/TordBoyau/blob/main/TordBoyau5.v) -
Fantastic version of the well-known "donut" demo,
Andy Sloane came out with a super-fast integer-only version (using the CORDIC algorithm):
https://gist.github.com/a1k0n/8ea6516b4946ab36348fb61703dc3194
You can do raytracing with adds and shifts ! (mul is not even needed)
Playing with it a little bit (my version with double-vertical resolution RGB rendering in the terminal)
It is a good test for @risc_v softcores, #fpga pipelined beam surfers and #femtorv ! (cc @sylefeb ) -
Sharing this I saw on twitter by BrunoLevy01:
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The simple #femtorv-quark takes no more than 200 lines of VERILOG. Yes, it is the complete description of a risc-v processor, that can run C programs compiled with gcc-riscv
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@MichaelJBrodeur I have played with both Ice40, ECP5 and Xilinx-based boards, all of them work, and you'll be able to run Episode 1 on everything. Now for Episode 2 (pipeline) the smallest Ice40 FPGAs will be too small.
For episode 1, if you can do a blinky, you can do #femtorv (except if you are smaller than an Ice40 Hx1K) -
learn-fpga, the tutorial to create @risc_v
cores such as #femtorv on #fpga is approaching 2K stars on github !
https://github.com/BrunoLevy/learn-fpga -
Tomorrow, @risc_v
meeting at Inria Paris. I will be talking about the learn-fpga project (https://github.com/BrunoLevy/learn-fpga). Everyone can design his own RISC-V softcore on a FPGA, it is easy ! (no more than 200 lines of VERILOG for #femtorv) -
#RISCV softcore #femtorv on #FPGA, using the LiteX system: design your own processor, plug-in SDRAM, framebuffer, SDCard, write some programs.
https://github.com/BrunoLevy/learn-fpga/blob/master/LiteX/README.md -
Port of the 90's ST_NICCC demo (https://www.pouet.net/prod.php?which=1251), running on #femtorv risc-v core
(https://github.com/BrunoLevy/learn-fpga) -
43/N
If you installed Yosys/NextPNR, generated a bitstream, made the little LEDs blink, then you are not that far away from a fully functional microprocessor. Am I joking ? Let me show you: this image is the complete VERILOG for #femtorv (200 lines). -
Could be a great starting point for writing #femtorv episodes 3 (Zicsr) and episode 4 (virtual memory) for a full gentle continuous path from blinker to Unix-capable CPU.
Episodes 1 (minimalistic CPU) and 2 (pipelining) are here:
https://github.com/BrunoLevy/learn-fpga/blob/master/FemtoRV/TUTORIALS/FROM_BLINKER_TO_RISCV/README.md
Help needed ! -
Amazing project by Michael Schröder: minimalistic Unix-like system on a minimalistic processor, in the spirit of #femtorv (but with interrupts and virtual memory !)
https://gitlab.com/x653/xv6-riscv-fpga
... and last but not least, it comes with a 3D-printable case with NeXT vibes, love it ! -
For more fun, you can add a $2 led matrix + MAX7219, and generate additional hardware to drive it. Then your #femtorv processor can say hello to you !