#mecrisp — Public Fediverse posts
Live and recent posts from across the Fediverse tagged #mecrisp, aggregated by home.social.
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I am happy to announce the FemtoMSP430, a processor designed with the instruction set of the classic #MSP430, but with a flexible bus interface similar to @BrunoLevy01 #FemtoRV32 including memory busy signaling. The playground contains a phantasy "microcontroller" design for the #ULX3S #FPGA board, interactively running the original #Mecrisp #Forth image for MSP430G2755, enhanced with a text mode on 800x600 video, USB-CDC terminal and a lot of GPIO wires: https://codeberg.org/Mecrisp/FemtoMSP430
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I am happy to announce the FemtoMSP430, a processor designed with the instruction set of the classic #MSP430, but with a flexible bus interface similar to @BrunoLevy01 #FemtoRV32 including memory busy signaling. The playground contains a phantasy "microcontroller" design for the #ULX3S #FPGA board, interactively running the original #Mecrisp #Forth image for MSP430G2755, enhanced with a text mode on 800x600 video, USB-CDC terminal and a lot of GPIO wires: https://codeberg.org/Mecrisp/FemtoMSP430
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I am happy to announce the FemtoMSP430, a processor designed with the instruction set of the classic #MSP430, but with a flexible bus interface similar to @BrunoLevy01 #FemtoRV32 including memory busy signaling. The playground contains a phantasy "microcontroller" design for the #ULX3S #FPGA board, interactively running the original #Mecrisp #Forth image for MSP430G2755, enhanced with a text mode on 800x600 video, USB-CDC terminal and a lot of GPIO wires: https://codeberg.org/Mecrisp/FemtoMSP430
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I am happy to announce the FemtoMSP430, a processor designed with the instruction set of the classic #MSP430, but with a flexible bus interface similar to @BrunoLevy01 #FemtoRV32 including memory busy signaling. The playground contains a phantasy "microcontroller" design for the #ULX3S #FPGA board, interactively running the original #Mecrisp #Forth image for MSP430G2755, enhanced with a text mode on 800x600 video, USB-CDC terminal and a lot of GPIO wires: https://codeberg.org/Mecrisp/FemtoMSP430
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@[email protected] to be honest, I haven’t dug too much in chips other than the most popular ones - atmega, attiny85, esp8266/32 and now ch32v003. I’m doing electronics more on a hobby level. I’d go for rp2040, since #zeptoforth already supports it quite well and Raspberry Pi Pico board is quite cheap. If you want to build your own board I guess you’ll want to look what chips #zeptoforth or #Mecrisp Forth variants support.
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@extrowerk to be honest, I haven’t dug too much in chips other than the most popular ones - atmega, attiny85, esp8266/32 and now ch32v003. I’m doing electronics more on a hobby level. I’d go for rp2040, since #zeptoforth already supports it quite well and Raspberry Pi Pico board is quite cheap. If you want to build your own board I guess you’ll want to look what chips #zeptoforth or #Mecrisp Forth variants support.
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@extrowerk to be honest, I haven’t dug too much in chips other than the most popular ones - atmega, attiny85, esp8266/32 and now ch32v003. I’m doing electronics more on a hobby level. I’d go for rp2040, since #zeptoforth already supports it quite well and Raspberry Pi Pico board is quite cheap. If you want to build your own board I guess you’ll want to look what chips #zeptoforth or #Mecrisp Forth variants support.
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I am happy to announce the release of a longwave software defined radio which I designed at work for experiments with #DSP algorithms, running on the #ULX3S #FPGA board. The user interface is based on #Mecrisp #Forth running on the #FemtoRV, and the signal chain contains a pipelined FFT designed by Dan Gisselquist. Many thanks to Ulixxe for their USB-CDC implementation!
https://github.com/mb-sat/ulx3s-longwave-sdr
https://codeberg.org/Mecrisp/ulx3s-longwave-sdr -
I am happy to announce the release of a longwave software defined radio which I designed at work for experiments with #DSP algorithms, running on the #ULX3S #FPGA board. The user interface is based on #Mecrisp #Forth running on the #FemtoRV, and the signal chain contains a pipelined FFT designed by Dan Gisselquist. Many thanks to Ulixxe for their USB-CDC implementation!
https://github.com/mb-sat/ulx3s-longwave-sdr
https://codeberg.org/Mecrisp/ulx3s-longwave-sdr -
I am happy to announce the release of a longwave software defined radio which I designed at work for experiments with #DSP algorithms, running on the #ULX3S #FPGA board. The user interface is based on #Mecrisp #Forth running on the #FemtoRV, and the signal chain contains a pipelined FFT designed by Dan Gisselquist. Many thanks to Ulixxe for their USB-CDC implementation!
https://github.com/mb-sat/ulx3s-longwave-sdr
https://codeberg.org/Mecrisp/ulx3s-longwave-sdr -
I am happy to announce the release of a longwave software defined radio which I designed at work for experiments with #DSP algorithms, running on the #ULX3S #FPGA board. The user interface is based on #Mecrisp #Forth running on the #FemtoRV, and the signal chain contains a pipelined FFT designed by Dan Gisselquist. Many thanks to Ulixxe for their USB-CDC implementation!
https://github.com/mb-sat/ulx3s-longwave-sdr
https://codeberg.org/Mecrisp/ulx3s-longwave-sdr -
mecrisp-ice on my iCEBreaker FPGA board. So cool. The first time synthesizing my own Forth CPU.
Thanks to Matthias for the Mecrisp project.
@Mecrisp -
mecrisp-ice on my iCEBreaker FPGA board. So cool. The first time synthesizing my own Forth CPU.
Thanks to Matthias for the Mecrisp project.
@Mecrisp -
mecrisp-ice on my iCEBreaker FPGA board. So cool. The first time synthesizing my own Forth CPU.
Thanks to Matthias for the Mecrisp project.
@Mecrisp -
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The space mission MAIUS-2 I wrote firmware for since 2019 launched in November 2023, and I am now open for new paid projects! My favourites are #Assembler, #Forth and #Verilog on #FPGA. I am the author of #Mecrisp, a family of optimising Forth compilers (Mecrisp-Ice went to space!), did processor design with @BrunoLevy01 (#FemtoRV Gracilis) and I love #sizecoding challenges (Byte-Athlon Champion in #Lovebyte 2023). Formally, I am Dr. rer. nat. in biophysics with experience in laser spectroscopy.
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The space mission MAIUS-2 I wrote firmware for since 2019 launched in November 2023, and I am now open for new paid projects! My favourites are #Assembler, #Forth and #Verilog on #FPGA. I am the author of #Mecrisp, a family of optimising Forth compilers (Mecrisp-Ice went to space!), did processor design with @BrunoLevy01 (#FemtoRV Gracilis) and I love #sizecoding challenges (Byte-Athlon Champion in #Lovebyte 2023). Formally, I am Dr. rer. nat. in biophysics with experience in laser spectroscopy.
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The space mission MAIUS-2 I wrote firmware for since 2019 launched in November 2023, and I am now open for new paid projects! My favourites are #Assembler, #Forth and #Verilog on #FPGA. I am the author of #Mecrisp, a family of optimising Forth compilers (Mecrisp-Ice went to space!), did processor design with @BrunoLevy01 (#FemtoRV Gracilis) and I love #sizecoding challenges (Byte-Athlon Champion in #Lovebyte 2023). Formally, I am Dr. rer. nat. in biophysics with experience in laser spectroscopy.
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The space mission MAIUS-2 I wrote firmware for since 2019 launched in November 2023, and I am now open for new paid projects! My favourites are #Assembler, #Forth and #Verilog on #FPGA. I am the author of #Mecrisp, a family of optimising Forth compilers (Mecrisp-Ice went to space!), did processor design with @BrunoLevy01 (#FemtoRV Gracilis) and I love #sizecoding challenges (Byte-Athlon Champion in #Lovebyte 2023). Formally, I am Dr. rer. nat. in biophysics with experience in laser spectroscopy.
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The killer app for stack machines is debugging FPGAs.
I will be speaking about the obvious advantages of 16 bit stack machines over 32 bit RISC-V machines on resource constrained FPGAs at the @yosyshq
user group meeting.May 27th, 18:00 CEST
Join via this link:
https://meet.jit.si/yosys-users-groupSlides:
https://pythonlinks.info/presentations/forth/YUG27May2024.pdf -
The killer app for stack machines is debugging FPGAs.
I will be speaking about the obvious advantages of 16 bit stack machines over 32 bit RISC-V machines on resource constrained FPGAs at the @yosyshq
user group meeting.May 27th, 18:00 CEST
Join via this link:
https://meet.jit.si/yosys-users-groupSlides:
https://pythonlinks.info/presentations/forth/YUG27May2024.pdf -
I will be speaking about the obvious advantages of 16 bit stack machines over 32 bit RISC-V machines as FPGA soft core processors at the @yosyshq
user group meeting.May 27th, 18:00 CEST
Join via this link:
https://meet.jit.si/yosys-users-groupSlides:
https://pythonlinks.info/presentations/forth/YUG27May2024.pdf -
I will be speaking about the obvious advantages of 16 bit stack machines over 32 bit RISC-V machines as FPGA soft core processors at the @yosyshq
user group meeting.May 27th, 18:00 CEST
Join via this link:
https://meet.jit.si/yosys-users-groupSlides:
https://pythonlinks.info/presentations/forth/YUG27May2024.pdf -
@hanshuebner Synthesis from the command line sounds great.
I presume that it supports Verilog as well. The #J1 and #Mecrisp are all in verilog.
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@hanshuebner Synthesis from the command line sounds great.
I presume that it supports Verilog as well. The #J1 and #Mecrisp are all in verilog.
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@hanshuebner Synthesis from the command line sounds great.
I presume that it supports Verilog as well. The #J1 and #Mecrisp are all in verilog.
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Would you prefer a #forth computer with VGA, HDMI, or a Touch Screen output?
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Would you prefer a #forth computer with VGA, HDMI, or a Touch Screen output?
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Would you prefer a #forth computer with VGA, HDMI, or a Touch Screen output?
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My post about a #forth computer with a mouse and keyboard port, and a VGA adapter received more boosts than any of my other posts.
I wonder why that idea is so popular?
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My post about a #forth computer with a mouse and keyboard port, and a VGA adapter received more boosts than any of my other posts.
I wonder why that idea is so popular?
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I am currently building #forth cores on FPGA's. #mecrisp offers developer libraries, but #konilo has end user applications: a wiki, editor, and catalog. There are a number of fpga boards with 2 usb ports, and a vgA port. Instant computer.
I also like that you have higher level abstractions. *combinators, *quotes and *sigils. I have to figure out what they do.
#napia is even more interesting. 8 Cores! I am sold.
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I am currently building #forth cores on FPGA's. #mecrisp offers developer libraries, but #konilo has end user applications: a wiki, editor, and catalog. There are a number of fpga boards with 2 usb ports, and a vgA port. Instant computer.
I also like that you have higher level abstractions. *combinators, *quotes and *sigils. I have to figure out what they do.
#napia is even more interesting. 8 Cores! I am sold.
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Mecrisp Ice I/O Documentation
https://mecrisp-ice.readthedocs.io/en/latest/io.html#mecrisp @mecrisp
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Mecrisp Ice I/O Documentation
https://mecrisp-ice.readthedocs.io/en/latest/io.html#mecrisp @mecrisp
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I have created a Read The Docs site for Mecrisp Ice, which is a family of 16, 32 and 64 bit soft core Forth processors written in Verilog and based on the J1 stack machine.
https://mecrisp-ice.readthedocs.io
@Mecrisp #mecrisp #fpga #forth #j1 #stackmachine #readthedocs
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I have created a Read The Docs site for Mecrisp Ice, which is a family of 16, 32 and 64 bit soft core Forth processors written in Verilog and based on the J1 stack machine.
https://mecrisp-ice.readthedocs.io
@Mecrisp #mecrisp #fpga #forth #j1 #stackmachine #readthedocs
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FPGA Hackathon.
https://fpgahackathon.com/
"Kria KV260 boards will be used during the event. Additionally, Vivado, MATLAB and VCS will be available."I can port #mecrisp to that board!
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FPGA Hackathon.
https://fpgahackathon.com/
"Kria KV260 boards will be used during the event. Additionally, Vivado, MATLAB and VCS will be available."I can port #mecrisp to that board!
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#Forth is a nutty language.
Here is the code to diaplay the name "Mecrisp" to the user.[char] e
[char] M 2emit
[char] r
[char] c 2emit
[char] s
[char] i 2emit
[char] -
[char] p 2emit -
#Forth is a nutty language.
Here is the code to diaplay the name "Mecrisp" to the user.[char] e
[char] M 2emit
[char] r
[char] c 2emit
[char] s
[char] i 2emit
[char] -
[char] p 2emit -
#Forth is a nutty language.
Here is the code to diaplay the name "Mecrisp" to the user.[char] e
[char] M 2emit
[char] r
[char] c 2emit
[char] s
[char] i 2emit
[char] -
[char] p 2emit -
So it looks like I have single port access mostly working on top of the #mecrisp dualport 16 bit code.
A few more things to polish up.
I made a commit, so I do not loose this precious mostly working verilog.
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So it looks like I have single port access mostly working on top of the #mecrisp dualport 16 bit code.
A few more things to polish up.
I made a commit, so I do not loose this precious mostly working verilog.
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I think that it is very hard to debug complex #verilog circuits. So many things happening at the same time. So I am about to start writing C++ consistency checks for the #Verilator simulator. If this signal is this way, then that signal should be that way. Run a test, if it fails, guess at the bug, write a consistency test, and run it again.
Very different from testing each block, sadly the #J1 CPU + #Forth is one complex circuit.
#Mecrisp -
I think that it is very hard to debug complex #verilog circuits. So many things happening at the same time. So I am about to start writing C++ consistency checks for the #Verilator simulator. If this signal is this way, then that signal should be that way. Run a test, if it fails, guess at the bug, write a consistency test, and run it again.
Very different from testing each block, sadly the #J1 CPU + #Forth is one complex circuit.
#Mecrisp -
I am jsut struggling with the J1a's single port memory access. it would provide twice as much memory, so it seems to be most important.
The problems is that the J1a and Mecrisp have a most confusing way of managing instruction and data read conflicts. i am not yet sure if it is brilliant, or overly complex, but i am getting closer to an answer.
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I am jsut struggling with the J1a's single port memory access. it would provide twice as much memory, so it seems to be most important.
The problems is that the J1a and Mecrisp have a most confusing way of managing instruction and data read conflicts. i am not yet sure if it is brilliant, or overly complex, but i am getting closer to an answer.