#mecrisp — Public Fediverse posts

I am happy to announce the FemtoMSP430, a processor designed with the instruction set of the classic #MSP430, but with a flexible bus interface similar to @BrunoLevy01 #FemtoRV32 including memory busy signaling. The playground contains a phantasy "microcontroller" design for the #ULX3S #FPGA board, interactively running the original #Mecrisp #Forth image for MSP430G2755, enhanced with a text mode on 800x600 video, USB-CDC terminal and a lot of GPIO wires: https://codeberg.org/Mecrisp/FemtoMSP430

@[email protected] to be honest, I haven’t dug too much in chips other than the most popular ones - atmega, attiny85, esp8266/32 and now ch32v003. I’m doing electronics more on a hobby level. I’d go for rp2040, since #zeptoforth already supports it quite well and Raspberry Pi Pico board is quite cheap. If you want to build your own board I guess you’ll want to look what chips #zeptoforth or #Mecrisp Forth variants support.

I am happy to announce the release of a longwave software defined radio which I designed at work for experiments with #DSP algorithms, running on the #ULX3S #FPGA board. The user interface is based on #Mecrisp #Forth running on the #FemtoRV, and the signal chain contains a pipelined FFT designed by Dan Gisselquist. Many thanks to Ulixxe for their USB-CDC implementation!

https://github.com/mb-sat/ulx3s-longwave-sdr
https://codeberg.org/Mecrisp/ulx3s-longwave-sdr

mecrisp-ice on my iCEBreaker FPGA board. So cool. The first time synthesizing my own Forth CPU.

Thanks to Matthias for the Mecrisp project.
@Mecrisp

#forth #mecrisp #fpga #icebreaker

Hana-1: Programmable I/O for FPGAs

Here is what I am building.

https://forth.pythonlinks.info/

#FPGA #Forth #Mecrisp #MecrispIce

^^^ Is an excellent video describing how the FemtoRV works. I will soon be comparing #Mecrisp #ice with Risc-V, so the timing is almost perfect.

#forth #fpga #PicoIce #MecrispIce #riscv #Lattice #Mecrisp

@Mecrisp @BrunoLevy01

The space mission MAIUS-2 I wrote firmware for since 2019 launched in November 2023, and I am now open for new paid projects! My favourites are #Assembler, #Forth and #Verilog on #FPGA. I am the author of #Mecrisp, a family of optimising Forth compilers (Mecrisp-Ice went to space!), did processor design with @BrunoLevy01 (#FemtoRV Gracilis) and I love #sizecoding challenges (Byte-Athlon Champion in #Lovebyte 2023). Formally, I am Dr. rer. nat. in biophysics with experience in laser spectroscopy.

The killer app for stack machines is debugging FPGAs.

I will be speaking about the obvious advantages of 16 bit stack machines over 32 bit RISC-V machines on resource constrained FPGAs at the @yosyshq
user group meeting.

May 27th, 18:00 CEST

Join via this link:
https://meet.jit.si/yosys-users-group

Slides:
https://pythonlinks.info/presentations/forth/YUG27May2024.pdf

#uxn #forth #mecrisp #j1 #riscv #swic

I will be speaking about the obvious advantages of 16 bit stack machines over 32 bit RISC-V machines as FPGA soft core processors at the @yosyshq
user group meeting.

May 27th, 18:00 CEST

Join via this link:
https://meet.jit.si/yosys-users-group

Slides:
https://pythonlinks.info/presentations/forth/YUG27May2024.pdf

#uxn #forth #mecrisp #j1 #riscv #swic

I am thinking of leaving Mastodon.Social.

Where should I go?
#forth
#fpga
#mecrisp
#rp2040
#verilog

@hanshuebner Synthesis from the command line sounds great.

I presume that it supports Verilog as well. The #J1 and #Mecrisp are all in verilog.

Would you prefer a #forth computer with VGA, HDMI, or a Touch Screen output?

#uxn #ilo #napia #mecrisp

https://machdyne.com/product/kolsch-computer/

My post about a #forth computer with a mouse and keyboard port, and a VGA adapter received more boosts than any of my other posts.

I wonder why that idea is so popular?

#uxn #ilo #napia #mecrisp

https://machdyne.com/product/kolsch-computer/

I am currently building #forth cores on FPGA's. #mecrisp offers developer libraries, but #konilo has end user applications: a wiki, editor, and catalog. There are a number of fpga boards with 2 usb ports, and a vgA port. Instant computer.

I also like that you have higher level abstractions. *combinators, *quotes and *sigils. I have to figure out what they do.

#napia is even more interesting. 8 Cores! I am sold.

@crc

Here are the instructions for using #e4thcom with #mecrisp on the #picoIce. #Ice40 #fpga #forth
https://mecrisp-ice.readthedocs.io/en/latest/e4thcom.html

Mecrisp Ice I/O Documentation
https://mecrisp-ice.readthedocs.io/en/latest/io.html

#mecrisp @mecrisp

I have created a Read The Docs site for Mecrisp Ice, which is a family of 16, 32 and 64 bit soft core Forth processors written in Verilog and based on the J1 stack machine.

https://mecrisp-ice.readthedocs.io

@Mecrisp #mecrisp #fpga #forth #j1 #stackmachine #readthedocs

FPGA Hackathon.
https://fpgahackathon.com/

"Kria KV260 boards will be used during the event. Additionally, Vivado, MATLAB and VCS will be available."

I can port #mecrisp to that board!

@Mecrisp
#fpga #forth #XILINX

#Forth is a nutty language.
Here is the code to diaplay the name "Mecrisp" to the user.

[char] e
[char] M 2emit
[char] r
[char] c 2emit
[char] s
[char] i 2emit
[char] -
[char] p 2emit

#Mecrisp

So it looks like I have single port access mostly working on top of the #mecrisp dualport 16 bit code.

A few more things to polish up.

I made a commit, so I do not loose this precious mostly working verilog.

I think that it is very hard to debug complex #verilog circuits. So many things happening at the same time. So I am about to start writing C++ consistency checks for the #Verilator simulator. If this signal is this way, then that signal should be that way. Run a test, if it fails, guess at the bug, write a consistency test, and run it again.

Very different from testing each block, sadly the #J1 CPU + #Forth is one complex circuit.
#Mecrisp

I am jsut struggling with the J1a's single port memory access. it would provide twice as much memory, so it seems to be most important.

The problems is that the J1a and Mecrisp have a most confusing way of managing instruction and data read conflicts. i am not yet sure if it is brilliant, or overly complex, but i am getting closer to an answer.

#j1 #forth #Mecrisp

I am interested in building a #uxn cpu on an #fpga.
I have already built #Mecrisp #Forth on the #PicoIce.
A Uxn cpu is just a slightly different stack machine.
Maybe I will eventually build an entire Varvara computer on an FPGA.

@neauoire
@rek

https://forth.pythonlinks.info/hana-uxn

I now have a Mecrisp Forth core running on the pico-ice FPGA.

#picoice #mecrisp #forth #fpga #ice40.

Mecrisp-Ice 2.6d verilator-16bit
./compile
./emulate
works great.
Thank you for making it such an easy entry point.

Now that I have something working, I can study it, figure out how everything works, and then once I understand it, move on to porting to a new board.

It is a lot of complexity, one has to bite off one part at at ime.
#mecrisp #forth

Here is the documentation for the #PicoIce echo server.
It lets you test connecting #micropython #forth or other languages running on the #RP2040 to the #ice40.

https://forth.pythonlinks.info/pico-ice-echo-server
#mecrisp

I received an #upduino and a #picoice circuit board this week, got the basic tools working, and am working on an echo server. Soon I will be building a #Mecrisp #Forth core.

I am giving a talk on #Forth this week at the #fpgaworld conference in stockholm.
#fpga

Here is my best estimate as to when the Hana processor will ship. Maybe the word guess is more accurate than estimate.

I will update it as things change. #forth #mecrisp #picoice

https://forth.pythonlinks.info/ship-schedule

Thank you @jemo07 for pushing me to ship the product sooner.

Here are my updated slides for my upcoomint talk at #SVFIG on #Forth, #Mecrisp, and #ice40.

There are so many different Forth CPUs. It is possible to categorise them based on what their design constraints and objectives were.

https://pythonlinks.info/presentations/ForthPresentation.pdf

#ZeptoForth boots on the #PicoIce, which means that the default power, usb and flash pins are correctly connected. Which means that #MicroPython and #Mecrisp probably boot as well.

As soon as I get my #FPGA working on the #Upduino, I want to buy a Pico-Ice, and check out the REPLs..

I bought the #upduino board. $33 List Price. $97 shipped to Europe and taxed. And I still need some #pmods.

Now I feel like goofing off until it arrives.

#forth #mecrisp #manycore #transputer #csp

I will be using th #Upduino board, not the #PicIce board. So much simpler, and it optionally comes with 4 pre-doldered headers (slots) for #pmods.

There is even a version of #Mecrisp which already runs on the Upduino.

And I can do all the development on my Mac!

On the RP2040 there is at least #ZeptoForth and #Mecrisp Forth. It is good to know that there is no eForth.

#ZeptoForth says that they can use the Wifi, but that #Mecrisp does not use the Wifi.

I wonder what other Forths are available for that chip. One decision I have to make is which #Forth to use on that chip.

@M0CUV

Sadly the #J1 processor requires dual port RAM, and there are at most 80Kbits of dual port RAM on the ICE40 FPGA's. The J1 cannot use the #1Mbit of available single port RAM.

Single Port RAM uses less resources, and the devices are so much cheaper. Only $35 for the #PicoIce board.

So that is the first thing I have to fix. I think I can do this.
#Forth. #Verilog #Mecrisp

@M0CUV
Dr. Ting's documentation was off the chart awesome.
"I felt like I was there."
I worry that with Dr. Ting's passing, other Forths will be growing more rapidly.
I want to know what are the most popular #Forth versions nowadays.
In particular which is the best for the #RP2040 processor in the #PicoIce processor.
And there is a version of #Mecrisp Ice processor with 27 instructions. I was reading its Verilog this morning.

Ting's EP32/24/16 ran eForth and had 27 words in Hardware. The #J1 and #Mecrisp cores have only 16 instrcutions, are smaller, and so became the hot item for FPGA.s Although the Ting CPU's are larger, and a bit slower, I suspect that they actually execute Forth programs faster. A comparative performance analysis is needed.

#Forth #eForth @Mecrisp #FPGA

@M0CUV