#mecrisp — Public Fediverse posts

I am happy to announce the FemtoMSP430, a processor designed with the instruction set of the classic #MSP430, but with a flexible bus interface similar to @BrunoLevy01 #FemtoRV32 including memory busy signaling. The playground contains a phantasy "microcontroller" design for the #ULX3S #FPGA board, interactively running the original #Mecrisp #Forth image for MSP430G2755, enhanced with a text mode on 800x600 video, USB-CDC terminal and a lot of GPIO wires: https://codeberg.org/Mecrisp/FemtoMSP430

I am happy to announce the FemtoMSP430, a processor designed with the instruction set of the classic #MSP430, but with a flexible bus interface similar to @BrunoLevy01 #FemtoRV32 including memory busy signaling. The playground contains a phantasy "microcontroller" design for the #ULX3S #FPGA board, interactively running the original #Mecrisp #Forth image for MSP430G2755, enhanced with a text mode on 800x600 video, USB-CDC terminal and a lot of GPIO wires: https://codeberg.org/Mecrisp/FemtoMSP430

I am happy to announce the FemtoMSP430, a processor designed with the instruction set of the classic #MSP430, but with a flexible bus interface similar to @BrunoLevy01 #FemtoRV32 including memory busy signaling. The playground contains a phantasy "microcontroller" design for the #ULX3S #FPGA board, interactively running the original #Mecrisp #Forth image for MSP430G2755, enhanced with a text mode on 800x600 video, USB-CDC terminal and a lot of GPIO wires: https://codeberg.org/Mecrisp/FemtoMSP430

I am happy to announce the FemtoMSP430, a processor designed with the instruction set of the classic #MSP430, but with a flexible bus interface similar to @BrunoLevy01 #FemtoRV32 including memory busy signaling. The playground contains a phantasy "microcontroller" design for the #ULX3S #FPGA board, interactively running the original #Mecrisp #Forth image for MSP430G2755, enhanced with a text mode on 800x600 video, USB-CDC terminal and a lot of GPIO wires: https://codeberg.org/Mecrisp/FemtoMSP430

I am happy to announce the FemtoMSP430, a processor designed with the instruction set of the classic #MSP430, but with a flexible bus interface similar to @BrunoLevy01 #FemtoRV32 including memory busy signaling. The playground contains a phantasy "microcontroller" design for the #ULX3S #FPGA board, interactively running the original #Mecrisp #Forth image for MSP430G2755, enhanced with a text mode on 800x600 video, USB-CDC terminal and a lot of GPIO wires: https://codeberg.org/Mecrisp/FemtoMSP430

@extrowerk to be honest, I haven’t dug too much in chips other than the most popular ones - atmega, attiny85, esp8266/32 and now ch32v003. I’m doing electronics more on a hobby level. I’d go for rp2040, since #zeptoforth already supports it quite well and Raspberry Pi Pico board is quite cheap. If you want to build your own board I guess you’ll want to look what chips #zeptoforth or #Mecrisp Forth variants support.

@[email protected] to be honest, I haven’t dug too much in chips other than the most popular ones - atmega, attiny85, esp8266/32 and now ch32v003. I’m doing electronics more on a hobby level. I’d go for rp2040, since #zeptoforth already supports it quite well and Raspberry Pi Pico board is quite cheap. If you want to build your own board I guess you’ll want to look what chips #zeptoforth or #Mecrisp Forth variants support.

@extrowerk to be honest, I haven’t dug too much in chips other than the most popular ones - atmega, attiny85, esp8266/32 and now ch32v003. I’m doing electronics more on a hobby level. I’d go for rp2040, since #zeptoforth already supports it quite well and Raspberry Pi Pico board is quite cheap. If you want to build your own board I guess you’ll want to look what chips #zeptoforth or #Mecrisp Forth variants support.

@extrowerk to be honest, I haven’t dug too much in chips other than the most popular ones - atmega, attiny85, esp8266/32 and now ch32v003. I’m doing electronics more on a hobby level. I’d go for rp2040, since #zeptoforth already supports it quite well and Raspberry Pi Pico board is quite cheap. If you want to build your own board I guess you’ll want to look what chips #zeptoforth or #Mecrisp Forth variants support.

I am happy to announce the release of a longwave software defined radio which I designed at work for experiments with #DSP algorithms, running on the #ULX3S #FPGA board. The user interface is based on #Mecrisp #Forth running on the #FemtoRV, and the signal chain contains a pipelined FFT designed by Dan Gisselquist. Many thanks to Ulixxe for their USB-CDC implementation!

https://github.com/mb-sat/ulx3s-longwave-sdr
https://codeberg.org/Mecrisp/ulx3s-longwave-sdr

I am happy to announce the release of a longwave software defined radio which I designed at work for experiments with #DSP algorithms, running on the #ULX3S #FPGA board. The user interface is based on #Mecrisp #Forth running on the #FemtoRV, and the signal chain contains a pipelined FFT designed by Dan Gisselquist. Many thanks to Ulixxe for their USB-CDC implementation!

https://github.com/mb-sat/ulx3s-longwave-sdr
https://codeberg.org/Mecrisp/ulx3s-longwave-sdr

I am happy to announce the release of a longwave software defined radio which I designed at work for experiments with #DSP algorithms, running on the #ULX3S #FPGA board. The user interface is based on #Mecrisp #Forth running on the #FemtoRV, and the signal chain contains a pipelined FFT designed by Dan Gisselquist. Many thanks to Ulixxe for their USB-CDC implementation!

https://github.com/mb-sat/ulx3s-longwave-sdr
https://codeberg.org/Mecrisp/ulx3s-longwave-sdr

I am happy to announce the release of a longwave software defined radio which I designed at work for experiments with #DSP algorithms, running on the #ULX3S #FPGA board. The user interface is based on #Mecrisp #Forth running on the #FemtoRV, and the signal chain contains a pipelined FFT designed by Dan Gisselquist. Many thanks to Ulixxe for their USB-CDC implementation!

https://github.com/mb-sat/ulx3s-longwave-sdr
https://codeberg.org/Mecrisp/ulx3s-longwave-sdr

I am happy to announce the release of a longwave software defined radio which I designed at work for experiments with #DSP algorithms, running on the #ULX3S #FPGA board. The user interface is based on #Mecrisp #Forth running on the #FemtoRV, and the signal chain contains a pipelined FFT designed by Dan Gisselquist. Many thanks to Ulixxe for their USB-CDC implementation!

https://github.com/mb-sat/ulx3s-longwave-sdr
https://codeberg.org/Mecrisp/ulx3s-longwave-sdr

mecrisp-ice on my iCEBreaker FPGA board. So cool. The first time synthesizing my own Forth CPU.

Thanks to Matthias for the Mecrisp project.
@Mecrisp

#forth #mecrisp #fpga #icebreaker

mecrisp-ice on my iCEBreaker FPGA board. So cool. The first time synthesizing my own Forth CPU.

Thanks to Matthias for the Mecrisp project.
@Mecrisp

#forth #mecrisp #fpga #icebreaker

mecrisp-ice on my iCEBreaker FPGA board. So cool. The first time synthesizing my own Forth CPU.

Thanks to Matthias for the Mecrisp project.
@Mecrisp

#forth #mecrisp #fpga #icebreaker

mecrisp-ice on my iCEBreaker FPGA board. So cool. The first time synthesizing my own Forth CPU.

Thanks to Matthias for the Mecrisp project.
@Mecrisp

#forth #mecrisp #fpga #icebreaker

Hana-1: Programmable I/O for FPGAs

Here is what I am building.

https://forth.pythonlinks.info/

#FPGA #Forth #Mecrisp #MecrispIce

Hana-1: Programmable I/O for FPGAs

Here is what I am building.

https://forth.pythonlinks.info/

#FPGA #Forth #Mecrisp #MecrispIce

Hana-1: Programmable I/O for FPGAs

Here is what I am building.

https://forth.pythonlinks.info/

#FPGA #Forth #Mecrisp #MecrispIce

Hana-1: Programmable I/O for FPGAs

Here is what I am building.

https://forth.pythonlinks.info/

#FPGA #Forth #Mecrisp #MecrispIce

^^^ Is an excellent video describing how the FemtoRV works. I will soon be comparing #Mecrisp #ice with Risc-V, so the timing is almost perfect.

#forth #fpga #PicoIce #MecrispIce #riscv #Lattice #Mecrisp

@Mecrisp @BrunoLevy01

^^^ Is an excellent video describing how the FemtoRV works. I will soon be comparing #Mecrisp #ice with Risc-V, so the timing is almost perfect.

#forth #fpga #PicoIce #MecrispIce #riscv #Lattice #Mecrisp

@Mecrisp @BrunoLevy01

^^^ Is an excellent video describing how the FemtoRV works. I will soon be comparing #Mecrisp #ice with Risc-V, so the timing is almost perfect.

#forth #fpga #PicoIce #MecrispIce #riscv #Lattice #Mecrisp

@Mecrisp @BrunoLevy01

The space mission MAIUS-2 I wrote firmware for since 2019 launched in November 2023, and I am now open for new paid projects! My favourites are #Assembler, #Forth and #Verilog on #FPGA. I am the author of #Mecrisp, a family of optimising Forth compilers (Mecrisp-Ice went to space!), did processor design with @BrunoLevy01 (#FemtoRV Gracilis) and I love #sizecoding challenges (Byte-Athlon Champion in #Lovebyte 2023). Formally, I am Dr. rer. nat. in biophysics with experience in laser spectroscopy.

The space mission MAIUS-2 I wrote firmware for since 2019 launched in November 2023, and I am now open for new paid projects! My favourites are #Assembler, #Forth and #Verilog on #FPGA. I am the author of #Mecrisp, a family of optimising Forth compilers (Mecrisp-Ice went to space!), did processor design with @BrunoLevy01 (#FemtoRV Gracilis) and I love #sizecoding challenges (Byte-Athlon Champion in #Lovebyte 2023). Formally, I am Dr. rer. nat. in biophysics with experience in laser spectroscopy.

The space mission MAIUS-2 I wrote firmware for since 2019 launched in November 2023, and I am now open for new paid projects! My favourites are #Assembler, #Forth and #Verilog on #FPGA. I am the author of #Mecrisp, a family of optimising Forth compilers (Mecrisp-Ice went to space!), did processor design with @BrunoLevy01 (#FemtoRV Gracilis) and I love #sizecoding challenges (Byte-Athlon Champion in #Lovebyte 2023). Formally, I am Dr. rer. nat. in biophysics with experience in laser spectroscopy.

The space mission MAIUS-2 I wrote firmware for since 2019 launched in November 2023, and I am now open for new paid projects! My favourites are #Assembler, #Forth and #Verilog on #FPGA. I am the author of #Mecrisp, a family of optimising Forth compilers (Mecrisp-Ice went to space!), did processor design with @BrunoLevy01 (#FemtoRV Gracilis) and I love #sizecoding challenges (Byte-Athlon Champion in #Lovebyte 2023). Formally, I am Dr. rer. nat. in biophysics with experience in laser spectroscopy.

The space mission MAIUS-2 I wrote firmware for since 2019 launched in November 2023, and I am now open for new paid projects! My favourites are #Assembler, #Forth and #Verilog on #FPGA. I am the author of #Mecrisp, a family of optimising Forth compilers (Mecrisp-Ice went to space!), did processor design with @BrunoLevy01 (#FemtoRV Gracilis) and I love #sizecoding challenges (Byte-Athlon Champion in #Lovebyte 2023). Formally, I am Dr. rer. nat. in biophysics with experience in laser spectroscopy.

The killer app for stack machines is debugging FPGAs.

I will be speaking about the obvious advantages of 16 bit stack machines over 32 bit RISC-V machines on resource constrained FPGAs at the @yosyshq
user group meeting.

May 27th, 18:00 CEST

Join via this link:
https://meet.jit.si/yosys-users-group

Slides:
https://pythonlinks.info/presentations/forth/YUG27May2024.pdf

#uxn #forth #mecrisp #j1 #riscv #swic

The killer app for stack machines is debugging FPGAs.

I will be speaking about the obvious advantages of 16 bit stack machines over 32 bit RISC-V machines on resource constrained FPGAs at the @yosyshq
user group meeting.

May 27th, 18:00 CEST

Join via this link:
https://meet.jit.si/yosys-users-group

Slides:
https://pythonlinks.info/presentations/forth/YUG27May2024.pdf

#uxn #forth #mecrisp #j1 #riscv #swic

The killer app for stack machines is debugging FPGAs.

I will be speaking about the obvious advantages of 16 bit stack machines over 32 bit RISC-V machines on resource constrained FPGAs at the @yosyshq
user group meeting.

May 27th, 18:00 CEST

Join via this link:
https://meet.jit.si/yosys-users-group

Slides:
https://pythonlinks.info/presentations/forth/YUG27May2024.pdf

#uxn #forth #mecrisp #j1 #riscv #swic

I will be speaking about the obvious advantages of 16 bit stack machines over 32 bit RISC-V machines as FPGA soft core processors at the @yosyshq
user group meeting.

May 27th, 18:00 CEST

Join via this link:
https://meet.jit.si/yosys-users-group

Slides:
https://pythonlinks.info/presentations/forth/YUG27May2024.pdf

#uxn #forth #mecrisp #j1 #riscv #swic

I will be speaking about the obvious advantages of 16 bit stack machines over 32 bit RISC-V machines as FPGA soft core processors at the @yosyshq
user group meeting.

May 27th, 18:00 CEST

Join via this link:
https://meet.jit.si/yosys-users-group

Slides:
https://pythonlinks.info/presentations/forth/YUG27May2024.pdf

#uxn #forth #mecrisp #j1 #riscv #swic

I will be speaking about the obvious advantages of 16 bit stack machines over 32 bit RISC-V machines as FPGA soft core processors at the @yosyshq
user group meeting.

May 27th, 18:00 CEST

Join via this link:
https://meet.jit.si/yosys-users-group

Slides:
https://pythonlinks.info/presentations/forth/YUG27May2024.pdf

#uxn #forth #mecrisp #j1 #riscv #swic

I am thinking of leaving Mastodon.Social.

Where should I go?
#forth
#fpga
#mecrisp
#rp2040
#verilog

I am thinking of leaving Mastodon.Social.

Where should I go?
#forth
#fpga
#mecrisp
#rp2040
#verilog

I am thinking of leaving Mastodon.Social.

Where should I go?
#forth
#fpga
#mecrisp
#rp2040
#verilog

I am thinking of leaving Mastodon.Social.

Where should I go?
#forth
#fpga
#mecrisp
#rp2040
#verilog

@hanshuebner Synthesis from the command line sounds great.

I presume that it supports Verilog as well. The #J1 and #Mecrisp are all in verilog.

@hanshuebner Synthesis from the command line sounds great.

I presume that it supports Verilog as well. The #J1 and #Mecrisp are all in verilog.

@hanshuebner Synthesis from the command line sounds great.

I presume that it supports Verilog as well. The #J1 and #Mecrisp are all in verilog.

@hanshuebner Synthesis from the command line sounds great.

I presume that it supports Verilog as well. The #J1 and #Mecrisp are all in verilog.

Would you prefer a #forth computer with VGA, HDMI, or a Touch Screen output?

#uxn #ilo #napia #mecrisp

https://machdyne.com/product/kolsch-computer/

Would you prefer a #forth computer with VGA, HDMI, or a Touch Screen output?

#uxn #ilo #napia #mecrisp

https://machdyne.com/product/kolsch-computer/

Would you prefer a #forth computer with VGA, HDMI, or a Touch Screen output?

#uxn #ilo #napia #mecrisp

https://machdyne.com/product/kolsch-computer/

Would you prefer a #forth computer with VGA, HDMI, or a Touch Screen output?

#uxn #ilo #napia #mecrisp

https://machdyne.com/product/kolsch-computer/

My post about a #forth computer with a mouse and keyboard port, and a VGA adapter received more boosts than any of my other posts.

I wonder why that idea is so popular?

#uxn #ilo #napia #mecrisp

https://machdyne.com/product/kolsch-computer/

My post about a #forth computer with a mouse and keyboard port, and a VGA adapter received more boosts than any of my other posts.

I wonder why that idea is so popular?

#uxn #ilo #napia #mecrisp

https://machdyne.com/product/kolsch-computer/