#riscv — Public Fediverse posts

From FUZxxl:

> SIMD programming challenge: take a vector v and a mask m segmenting it into k segments. Given a (variable) permutation π with k entries, shuffle the segments of v into the order given by π (segment-wise shuffle). How would you approach this problem?

My approach is to run-length-encode the offset of the start of each segment, apply the permutation, decode the RLE-offsets and finally fixup the offsets for the second to last element of each segment. This gives you the shuffle you can apply to the input.

Here is the RVV implementation: https://github.com/camel-cdr/rvv-playground/blob/main/segment-vrgather.c (https://godbolt.org/z/dMhxz84hz)

I've attached an image of an execution log to help visualize this.

#simd #riscv

From FUZxxl:

> SIMD programming challenge: take a vector v and a mask m segmenting it into k segments. Given a (variable) permutation π with k entries, shuffle the segments of v into the order given by π (segment-wise shuffle). How would you approach this problem?

My approach is to run-length-encode the offset of the start of each segment, apply the permutation, decode the RLE-offsets and finally fixup the offsets for the second to last element of each segment. This gives you the shuffle you can apply to the input.

Here is the RVV implementation: https://github.com/camel-cdr/rvv-playground/blob/main/segment-vrgather.c (https://godbolt.org/z/dMhxz84hz)

I've attached an image of an execution log to help visualize this.

#simd #riscv

The RISC-V ISA is crossing the chasm from hobbyist microcontrollers to datacenter-grade CPUs. SiFive, Ventana, and Rivos are shipping serious silicon while the software stack (LLVM, Linux, Debian) catches up. The open model works - no license fees, custom extensions, and a global talent pool driving innovation. #RISCV #OpenSource #Hardware #Linux #Embedded #OpenISA

The RISC-V ISA is crossing the chasm from hobbyist microcontrollers to datacenter-grade CPUs. SiFive, Ventana, and Rivos are shipping serious silicon while the software stack (LLVM, Linux, Debian) catches up. The open model works - no license fees, custom extensions, and a global talent pool driving innovation. #RISCV #OpenSource #Hardware #Linux #Embedded #OpenISA

RISC-V Is Inevitable, State of the Union Keynote Argues - EE Times

https://www.eetimes.com/risc-v-is-inevitable-state-of-the-union-keynote-argues/

#riscv #RVA23 #opensource

RISC-V Is Inevitable, State of the Union Keynote Argues - EE Times

https://www.eetimes.com/risc-v-is-inevitable-state-of-the-union-keynote-argues/

#riscv #RVA23 #opensource

Running DOOM is cool. Building the CPU that runs it is cooler.

This write-up follows the journey from designing a custom RISC-V processor to FPGA implementation and using DOOM to validate the design.

Excellent hardware/software co-design read.

https://armaangomes.com/blogs/doom/

#embedded #riscv #fpga

Running DOOM is cool. Building the CPU that runs it is cooler.

This write-up follows the journey from designing a custom RISC-V processor to FPGA implementation and using DOOM to validate the design.

Excellent hardware/software co-design read.

https://armaangomes.com/blogs/doom/

#embedded #riscv #fpga

Keeping the 2*8 cores (not threads!) of this SpacemiT-K3 busy #RISCV

Keeping the 2*8 cores (not threads!) of this SpacemiT-K3 busy #RISCV

EMiX extends FPGA emulation beyond the limits of a single board by partitioning RISC-V SoCs across multiple interconnected FPGAs. The authors demonstrate a Linux-capable 64-core system spanning 8 FPGAs and plan to open-source the framework.
https://arxiv.org/abs/2604.27012
#RISCV #FPGA

EMiX extends FPGA emulation beyond the limits of a single board by partitioning RISC-V SoCs across multiple interconnected FPGAs. The authors demonstrate a Linux-capable 64-core system spanning 8 FPGAs and plan to open-source the framework.
https://arxiv.org/abs/2604.27012
#RISCV #FPGA

The Milk-V Titan finally arrived! 🎉

#RISCV

The Milk-V Titan finally arrived! 🎉

#RISCV

New #riscv Fast-Track Proposal: Zijf (Far jumps and calls):

https://github.com/riscv/riscv-isa-manual/pull/3269

A) should've been defined way earlier
B) remember the Qualcomm slides (https://lists.riscv.org/g/tech-profiles/attachment/400/0/AOSP%20Compression.pdf)

New #riscv Fast-Track Proposal: Zijf (Far jumps and calls):

https://github.com/riscv/riscv-isa-manual/pull/3269

A) should've been defined way earlier
B) remember the Qualcomm slides (https://lists.riscv.org/g/tech-profiles/attachment/400/0/AOSP%20Compression.pdf)

The #SpacemiT #RV23 #RISCV hardware dev platform just keeps on growing

The #SpacemiT #RV23 #RISCV hardware dev platform just keeps on growing

The #SpacemiT #RV23 #RISCV hardware dev platform just keeps on growing

Fixing #RISCV cross-compilation and usage of @gotosocial on @nixos_org 🚀 https://github.com/NixOS/nixpkgs/pull/544570

Fixing #RISCV cross-compilation and usage of @gotosocial on @nixos_org 🚀 https://github.com/NixOS/nixpkgs/pull/544570

You need a 1234 GiB GPU to run your program?
Let me play you the tiniest... #microcontroller breakout board!

The 10-cent CH32V003 microcontroller and a single capacitor make a complete breakout board. Honestly, I didn't even need the PCB. The capacitor could be soldered directly on the pins.

I flashed it with the #Arduino . Not so "Nano" in comparison! #ESP32 for scale.

And it has #Rust support!

#rustlang #riscv #DIY #electronics

You need a 1234 GiB GPU to run your program?
Let me play you the tiniest... #microcontroller breakout board!

The 10-cent CH32V003 microcontroller and a single capacitor make a complete breakout board. Honestly, I didn't even need the PCB. The capacitor could be soldered directly on the pins.

I flashed it with the #Arduino . Not so "Nano" in comparison! #ESP32 for scale.

And it has #Rust support!

#rustlang #riscv #DIY #electronics

Christopher Barnatt of ExplainingComputers.com reviews the most powerful RISC-V SBC he's yet tested:

Milk-V Jupiter 2: RISC-V RVA23 SBC

https://www.youtube.com/watch?v=vSKA6thLI1U

tl;dw: ahead of RasPi 5 in some ways, behind it in others, hardware acceleration works well with the vendor OS (Bianbu, a patched Ubuntu derivative)

#RISCV #MilkV #RVA23 #SBC #ExplainingComputers

Christopher Barnatt of ExplainingComputers.com reviews the most powerful RISC-V SBC he's yet tested:

Milk-V Jupiter 2: RISC-V RVA23 SBC

https://www.youtube.com/watch?v=vSKA6thLI1U

tl;dw: ahead of RasPi 5 in some ways, behind it in others, hardware acceleration works well with the vendor OS (Bianbu, a patched Ubuntu derivative)

#RISCV #MilkV #RVA23 #SBC #ExplainingComputers

Sooner or later I'll buy an Risc-V SBC board, maybe with NPU.. #riscv #sbc #opensource #
https://youtu.be/vSKA6thLI1U

Sooner or later I'll buy an Risc-V SBC board, maybe with NPU.. #riscv #sbc #opensource #
https://youtu.be/vSKA6thLI1U

Update: I added a sound card :3

The timings are a bit fucked, I'll fix that at some point.

The way it works is slightly cursed, since protoflux doesn't have a way to output arbitrary audio. It drives the frequencies and amplitudes of 20 sine waves to reconstruct the sound.

The CPU is also really weak (running at 100 KHz here), all the audio data is preprocessed and all it has to do is copy it out of ROM and into the audio chip's memory, it is just barely able to do that x3

#resonite #riscv #vr

Update: I added a sound card :3

The timings are a bit fucked, I'll fix that at some point.

The way it works is slightly cursed, since protoflux doesn't have a way to output arbitrary audio. It drives the frequencies and amplitudes of 20 sine waves to reconstruct the sound.

The CPU is also really weak (running at 100 KHz here), all the audio data is preprocessed and all it has to do is copy it out of ROM and into the audio chip's memory, it is just barely able to do that x3

#resonite #riscv #vr

A couple of weeks ago the riscv64 edge builder had ~300 packages to build to catch up.

I moved the builder from Hifive Premiere p550 to Milk-v Pioneer this week because it has not been able to catch up since the 3.24 release.

Yesterday it was 500+

Now it is 811.

I am setting up the Spacemit K3 but somehow I doubt it will be enough. We need to fix the build infra to scale horizontally.

#AlpineLinux #RISCV

A couple of weeks ago the riscv64 edge builder had ~300 packages to build to catch up.

I moved the builder from Hifive Premiere p550 to Milk-v Pioneer this week because it has not been able to catch up since the 3.24 release.

Yesterday it was 500+

Now it is 811.

I am setting up the Spacemit K3 but somehow I doubt it will be enough. We need to fix the build infra to scale horizontally.

#AlpineLinux #RISCV

Java on Banana Pi: I tested the ARM BPI-M4 Zero and RISC-V BPI-F3 for my 2026 single-board-computer series.

The M4 Zero beats the Raspberry Pi Zero 2 on every benchmark, up to 47% faster, and it's the cheapest board in the whole comparison. I also got @pi4j blinking an RGB LED on it, my first working GPIO example on a non-Raspberry Pi board!

Full write-up + video:
https://webtechie.be/post/first-test-of-java-on-banana-pi-arm-and-risc-v-plus-a-blinking-led-with-pi4j/

#Java #BananaPi #RISCV #ARM #Pi4J #SingleBoardComputer #JavaOnSingleBoardComputers #FOSS

Java on Banana Pi: I tested the ARM BPI-M4 Zero and RISC-V BPI-F3 for my 2026 single-board-computer series.

The M4 Zero beats the Raspberry Pi Zero 2 on every benchmark, up to 47% faster, and it's the cheapest board in the whole comparison. I also got @pi4j blinking an RGB LED on it, my first working GPIO example on a non-Raspberry Pi board!

Full write-up + video:
https://webtechie.be/post/first-test-of-java-on-banana-pi-arm-and-risc-v-plus-a-blinking-led-with-pi4j/

#Java #BananaPi #RISCV #ARM #Pi4J #SingleBoardComputer #JavaOnSingleBoardComputers #FOSS

Both SoCs and SBCs come out of StarFive, and all 3 are fun little #RISCV (you'll see their JH7110 SoCs elsewhere too!) boards that can get you into the ecosystem..

https://sbc.compare/starfive

(The VF2 was also the 1st SBC I backed on Kickstarter!)

SpacemiT K3 is faster RISC-V than previous SBCs.

But I would like to have something like Altra. You know: 64-128 cores, dimm sockets for TBs of ram, working and fast PCIe. Just with RVA23 cores instead of Neoverse-N1 ones.

Maybe in 2030?

#riscv #spacemitk3

SpacemiT K3 is faster RISC-V than previous SBCs.

But I would like to have something like Altra. You know: 64-128 cores, dimm sockets for TBs of ram, working and fast PCIe. Just with RVA23 cores instead of Neoverse-N1 ones.

Maybe in 2030?

#riscv #spacemitk3

the protoflux rv32im emulator just rendered it's first mandelbrot set :3

it took almost an hour because this dumbass copied the wrong file and it wasn't actually using M instructions lol

#resonite #riscv #vr

#nixos #riscv #starfivevisionfive2
https://project-insanity.org/2026/03/25/this-small-risc-v-homeserver-can-host-almost-anything/
#HomeLab

Raspberries? Bananas? What about Mangoes?

MangoPi stole our hearts with the bright pink Zero form-factor #RISCV Allwinner D1 #SBC and quickly followed it up with a H618 ARM option but it's been quiet since :(

https://sbc.compare/mango-pi

My KianV RISC-V ASIC is booting mainline Linux with SDRAM.

Everything was developed from scratch.

The board was made by
@machdyne
 , and he also did the bring-up. Huge thanks to him!

Damn... a 32-bit Linux machine running on my own ASIC.

#RISCV #ASIC #Linux #SDRAM

Clintech Pico Board exposes all 48 RP2354B GPIOs in Pico-compatible form factor

https://fed.brid.gy/r/https://linuxgizmos.com/clintech-pico-board-exposes-all-48-rp2354b-gpios-in-pico-compatible-form-factor/

I really wish I had more @MilkV_Official #RISCV boards on the site, hopefully one day I'll change that.. For now, it's just the Mars, but its a fun little board, with a PCB design that stands out!

https://sbc.compare/44-milk-v-mars-4gb