#riscv — Public Fediverse posts

Coincidentally I was also looking for information on the SpacemiT-K3's AI capabilities and came across another of Bruno's articles. Interesting to see the performance figures here, and it's a real shame that - for now - it seems you have to ue prebuilt binaries to access the AI instructions with llama.cpp on Bianbu. But it does work. I have a local qwen2.5-coder running on mine. Just need a bit more work to let it do changes on the file system ...
#AI #RISCV #OpenSource
https://dev.to/gounthar/benchmarking-llamacpp-on-spacemit-k3-risc-v-ai-cores-vs-standard-rvv-part-4-10mc

Coincidentally I was also looking for information on the SpacemiT-K3's AI capabilities and came across another of Bruno's articles. Interesting to see the performance figures here, and it's a real shame that - for now - it seems you have to ue prebuilt binaries to access the AI instructions with llama.cpp on Bianbu. But it does work. I have a local qwen2.5-coder running on mine. Just need a bit more work to let it do changes on the file system ...
#AI #RISCV #OpenSource
https://dev.to/gounthar/benchmarking-llamacpp-on-spacemit-k3-risc-v-ai-cores-vs-standard-rvv-part-4-10mc

Coincidentally I was also looking for information on the SpacemiT-K3's AI capabilities and came across another of Bruno's articles. Interesting to see the performance figures here, and it's a real shame that - for now - it seems you have to ue prebuilt binaries to access the AI instructions with llama.cpp on Bianbu. But it does work. I have a local qwen2.5-coder running on mine. Just need a bit more work to let it do changes on the file system ...
#AI #RISCV #OpenSource
https://dev.to/gounthar/benchmarking-llamacpp-on-spacemit-k3-risc-v-ai-cores-vs-standard-rvv-part-4-10mc

Coincidentally I was also looking for information on the SpacemiT-K3's AI capabilities and came across another of Bruno's articles. Interesting to see the performance figures here, and it's a real shame that - for now - it seems you have to ue prebuilt binaries to access the AI instructions with llama.cpp on Bianbu. But it does work. I have a local qwen2.5-coder running on mine. Just need a bit more work to let it do changes on the file system ...
#AI #RISCV #OpenSource
https://dev.to/gounthar/benchmarking-llamacpp-on-spacemit-k3-risc-v-ai-cores-vs-standard-rvv-part-4-10mc

From FUZxxl:

> SIMD programming challenge: take a vector v and a mask m segmenting it into k segments. Given a (variable) permutation π with k entries, shuffle the segments of v into the order given by π (segment-wise shuffle). How would you approach this problem?

My approach is to run-length-encode the offset of the start of each segment, apply the permutation, decode the RLE-offsets and finally fixup the offsets for the second to last element of each segment. This gives you the shuffle you can apply to the input.

Here is the RVV implementation: https://github.com/camel-cdr/rvv-playground/blob/main/segment-vrgather.c (https://godbolt.org/z/dMhxz84hz)

I've attached an image of an execution log to help visualize this.

#simd #riscv

From FUZxxl:

> SIMD programming challenge: take a vector v and a mask m segmenting it into k segments. Given a (variable) permutation π with k entries, shuffle the segments of v into the order given by π (segment-wise shuffle). How would you approach this problem?

My approach is to run-length-encode the offset of the start of each segment, apply the permutation, decode the RLE-offsets and finally fixup the offsets for the second to last element of each segment. This gives you the shuffle you can apply to the input.

Here is the RVV implementation: https://github.com/camel-cdr/rvv-playground/blob/main/segment-vrgather.c (https://godbolt.org/z/dMhxz84hz)

I've attached an image of an execution log to help visualize this.

#simd #riscv

The RISC-V ISA is crossing the chasm from hobbyist microcontrollers to datacenter-grade CPUs. SiFive, Ventana, and Rivos are shipping serious silicon while the software stack (LLVM, Linux, Debian) catches up. The open model works - no license fees, custom extensions, and a global talent pool driving innovation. #RISCV #OpenSource #Hardware #Linux #Embedded #OpenISA

The RISC-V ISA is crossing the chasm from hobbyist microcontrollers to datacenter-grade CPUs. SiFive, Ventana, and Rivos are shipping serious silicon while the software stack (LLVM, Linux, Debian) catches up. The open model works - no license fees, custom extensions, and a global talent pool driving innovation. #RISCV #OpenSource #Hardware #Linux #Embedded #OpenISA

RISC-V Is Inevitable, State of the Union Keynote Argues - EE Times

https://www.eetimes.com/risc-v-is-inevitable-state-of-the-union-keynote-argues/

#riscv #RVA23 #opensource

RISC-V Is Inevitable, State of the Union Keynote Argues - EE Times

https://www.eetimes.com/risc-v-is-inevitable-state-of-the-union-keynote-argues/

#riscv #RVA23 #opensource

Running DOOM is cool. Building the CPU that runs it is cooler.

This write-up follows the journey from designing a custom RISC-V processor to FPGA implementation and using DOOM to validate the design.

Excellent hardware/software co-design read.

https://armaangomes.com/blogs/doom/

#embedded #riscv #fpga

Running DOOM is cool. Building the CPU that runs it is cooler.

This write-up follows the journey from designing a custom RISC-V processor to FPGA implementation and using DOOM to validate the design.

Excellent hardware/software co-design read.

https://armaangomes.com/blogs/doom/

#embedded #riscv #fpga

Keeping the 2*8 cores (not threads!) of this SpacemiT-K3 busy #RISCV

Keeping the 2*8 cores (not threads!) of this SpacemiT-K3 busy #RISCV

Having fun with alternate #ISA like #RISC_V #RISCV #ARM #PowerPC #LoongArch is fun but also revealing how bad people code these days even aside from SLOP, when something like #Discord or #Fluxer absolutely murders your little dev board or in general how popular using web apps over a framework is, just bloody sucks.

EMiX extends FPGA emulation beyond the limits of a single board by partitioning RISC-V SoCs across multiple interconnected FPGAs. The authors demonstrate a Linux-capable 64-core system spanning 8 FPGAs and plan to open-source the framework.
https://arxiv.org/abs/2604.27012
#RISCV #FPGA

EMiX extends FPGA emulation beyond the limits of a single board by partitioning RISC-V SoCs across multiple interconnected FPGAs. The authors demonstrate a Linux-capable 64-core system spanning 8 FPGAs and plan to open-source the framework.
https://arxiv.org/abs/2604.27012
#RISCV #FPGA

The Milk-V Titan finally arrived! 🎉

#RISCV

The Milk-V Titan finally arrived! 🎉

#RISCV

New #riscv Fast-Track Proposal: Zijf (Far jumps and calls):

https://github.com/riscv/riscv-isa-manual/pull/3269

A) should've been defined way earlier
B) remember the Qualcomm slides (https://lists.riscv.org/g/tech-profiles/attachment/400/0/AOSP%20Compression.pdf)

New #riscv Fast-Track Proposal: Zijf (Far jumps and calls):

https://github.com/riscv/riscv-isa-manual/pull/3269

A) should've been defined way earlier
B) remember the Qualcomm slides (https://lists.riscv.org/g/tech-profiles/attachment/400/0/AOSP%20Compression.pdf)

The #SpacemiT #RV23 #RISCV hardware dev platform just keeps on growing

The #SpacemiT #RV23 #RISCV hardware dev platform just keeps on growing

The #SpacemiT #RV23 #RISCV hardware dev platform just keeps on growing

The #SpacemiT #RV23 #RISCV hardware dev platform just keeps on growing

The #SpacemiT #RV23 #RISCV hardware dev platform just keeps on growing

The #SpacemiT #RV23 #RISCV hardware dev platform just keeps on growing

The #SpacemiT #RV23 #RISCV hardware dev platform just keeps on growing

Fixing #RISCV cross-compilation and usage of @gotosocial on @nixos_org 🚀 https://github.com/NixOS/nixpkgs/pull/544570

Fixing #RISCV cross-compilation and usage of @gotosocial on @nixos_org 🚀 https://github.com/NixOS/nixpkgs/pull/544570

You need a 1234 GiB GPU to run your program?
Let me play you the tiniest... #microcontroller breakout board!

The 10-cent CH32V003 microcontroller and a single capacitor make a complete breakout board. Honestly, I didn't even need the PCB. The capacitor could be soldered directly on the pins.

I flashed it with the #Arduino . Not so "Nano" in comparison! #ESP32 for scale.

And it has #Rust support!

#rustlang #riscv #DIY #electronics

You need a 1234 GiB GPU to run your program?
Let me play you the tiniest... #microcontroller breakout board!

The 10-cent CH32V003 microcontroller and a single capacitor make a complete breakout board. Honestly, I didn't even need the PCB. The capacitor could be soldered directly on the pins.

I flashed it with the #Arduino . Not so "Nano" in comparison! #ESP32 for scale.

And it has #Rust support!

#rustlang #riscv #DIY #electronics

You need a 1234 GiB GPU to run your program?
Let me play you the tiniest... #microcontroller breakout board!

The 10-cent CH32V003 microcontroller and a single capacitor make a complete breakout board. Honestly, I didn't even need the PCB. The capacitor could be soldered directly on the pins.

I flashed it with the #Arduino . Not so "Nano" in comparison! #ESP32 for scale.

And it has #Rust support!

#rustlang #riscv #DIY #electronics

You need a 1234 GiB GPU to run your program?
Let me play you the tiniest... #microcontroller breakout board!

The 10-cent CH32V003 microcontroller and a single capacitor make a complete breakout board. Honestly, I didn't even need the PCB. The capacitor could be soldered directly on the pins.

I flashed it with the #Arduino . Not so "Nano" in comparison! #ESP32 for scale.

And it has #Rust support!

#rustlang #riscv #DIY #electronics

You need a 1234 GiB GPU to run your program?
Let me play you the tiniest... #microcontroller breakout board!

The 10-cent CH32V003 microcontroller and a single capacitor make a complete breakout board. Honestly, I didn't even need the PCB. The capacitor could be soldered directly on the pins.

I flashed it with the #Arduino . Not so "Nano" in comparison! #ESP32 for scale.

And it has #Rust support!

#rustlang #riscv #DIY #electronics

Christopher Barnatt of ExplainingComputers.com reviews the most powerful RISC-V SBC he's yet tested:

Milk-V Jupiter 2: RISC-V RVA23 SBC

https://www.youtube.com/watch?v=vSKA6thLI1U

tl;dw: ahead of RasPi 5 in some ways, behind it in others, hardware acceleration works well with the vendor OS (Bianbu, a patched Ubuntu derivative)

#RISCV #MilkV #RVA23 #SBC #ExplainingComputers

Christopher Barnatt of ExplainingComputers.com reviews the most powerful RISC-V SBC he's yet tested:

Milk-V Jupiter 2: RISC-V RVA23 SBC

https://www.youtube.com/watch?v=vSKA6thLI1U

tl;dw: ahead of RasPi 5 in some ways, behind it in others, hardware acceleration works well with the vendor OS (Bianbu, a patched Ubuntu derivative)

#RISCV #MilkV #RVA23 #SBC #ExplainingComputers

Christopher Barnatt of ExplainingComputers.com reviews the most powerful RISC-V SBC he's yet tested:

Milk-V Jupiter 2: RISC-V RVA23 SBC

https://www.youtube.com/watch?v=vSKA6thLI1U

tl;dw: ahead of RasPi 5 in some ways, behind it in others, hardware acceleration works well with the vendor OS (Bianbu, a patched Ubuntu derivative)

#RISCV #MilkV #RVA23 #SBC #ExplainingComputers

Christopher Barnatt of ExplainingComputers.com reviews the most powerful RISC-V SBC he's yet tested:

Milk-V Jupiter 2: RISC-V RVA23 SBC

https://www.youtube.com/watch?v=vSKA6thLI1U

tl;dw: ahead of RasPi 5 in some ways, behind it in others, hardware acceleration works well with the vendor OS (Bianbu, a patched Ubuntu derivative)

#RISCV #MilkV #RVA23 #SBC #ExplainingComputers

Christopher Barnatt of ExplainingComputers.com reviews the most powerful RISC-V SBC he's yet tested:

Milk-V Jupiter 2: RISC-V RVA23 SBC

https://www.youtube.com/watch?v=vSKA6thLI1U

tl;dw: ahead of RasPi 5 in some ways, behind it in others, hardware acceleration works well with the vendor OS (Bianbu, a patched Ubuntu derivative)

#RISCV #MilkV #RVA23 #SBC #ExplainingComputers

Sooner or later I'll buy an Risc-V SBC board, maybe with NPU.. #riscv #sbc #opensource #
https://youtu.be/vSKA6thLI1U

Sooner or later I'll buy an Risc-V SBC board, maybe with NPU.. #riscv #sbc #opensource #
https://youtu.be/vSKA6thLI1U

Sooner or later I'll buy an Risc-V SBC board, maybe with NPU.. #riscv #sbc #opensource #
https://youtu.be/vSKA6thLI1U

Sooner or later I'll buy an Risc-V SBC board, maybe with NPU.. #riscv #sbc #opensource #
https://youtu.be/vSKA6thLI1U

Sooner or later I'll buy an Risc-V SBC board, maybe with NPU.. #riscv #sbc #opensource #
https://youtu.be/vSKA6thLI1U

Update: I added a sound card :3

The timings are a bit fucked, I'll fix that at some point.

The way it works is slightly cursed, since protoflux doesn't have a way to output arbitrary audio. It drives the frequencies and amplitudes of 20 sine waves to reconstruct the sound.

The CPU is also really weak (running at 100 KHz here), all the audio data is preprocessed and all it has to do is copy it out of ROM and into the audio chip's memory, it is just barely able to do that x3

#resonite #riscv #vr

Update: I added a sound card :3

The timings are a bit fucked, I'll fix that at some point.

The way it works is slightly cursed, since protoflux doesn't have a way to output arbitrary audio. It drives the frequencies and amplitudes of 20 sine waves to reconstruct the sound.

The CPU is also really weak (running at 100 KHz here), all the audio data is preprocessed and all it has to do is copy it out of ROM and into the audio chip's memory, it is just barely able to do that x3

#resonite #riscv #vr

Update: I added a sound card :3

The timings are a bit fucked, I'll fix that at some point.

The way it works is slightly cursed, since protoflux doesn't have a way to output arbitrary audio. It drives the frequencies and amplitudes of 20 sine waves to reconstruct the sound.

The CPU is also really weak (running at 100 KHz here), all the audio data is preprocessed and all it has to do is copy it out of ROM and into the audio chip's memory, it is just barely able to do that x3

#resonite #riscv #vr

Update: I added a sound card :3

The timings are a bit fucked, I'll fix that at some point.

The way it works is slightly cursed, since protoflux doesn't have a way to output arbitrary audio. It drives the frequencies and amplitudes of 20 sine waves to reconstruct the sound.

The CPU is also really weak (running at 100 KHz here), all the audio data is preprocessed and all it has to do is copy it out of ROM and into the audio chip's memory, it is just barely able to do that x3

#resonite #riscv #vr

Update: I added a sound card :3

The timings are a bit fucked, I'll fix that at some point.

The way it works is slightly cursed, since protoflux doesn't have a way to output arbitrary audio. It drives the frequencies and amplitudes of 20 sine waves to reconstruct the sound.

The CPU is also really weak (running at 100 KHz here), all the audio data is preprocessed and all it has to do is copy it out of ROM and into the audio chip's memory, it is just barely able to do that x3

#resonite #riscv #vr