#riscv — Public Fediverse posts

🚩 NetBSD 11.0 a fost lansat: Suport nativ pentru RISC-V și compatibilitate îmbunătățită cu Linux!

Noul update major al istoricului sistem de operare din familia BSD, NetBSD 11.0, este acum disponibil oficial, aducând îmbunătățiri remarcabile pe partea de suport hardware, performanță și securitate.

✨ Ce aduce nou NetBSD 11.0:

🏗️ Arhitectură RISC-V extinsă:
• Suport complet și îmbunătățit pentru hardware-ul bazat pe arhitectura deschisă RISC-V (atât pe 64 de biți, cât și pe 32 de biți), extinzând portabilitatea legendară a sistemului.

🐧 Compatibilitate mai bună cu pachetele Linux:
• Stratul de compatibilitate COMPAT_LINUX a primit actualizări majore, permițând rularea mai multor aplicații și utilitare native de Linux pe un kernel NetBSD.

⚡ Drivere și stivă grafică modernizate:
• Drivere grafice actualizate pentru procesoarele grafice moderne Intel, AMD și NVIDIA, oferind suport mai bun pentru accelerarea 3D și monitoare de înaltă rezoluție.

🔒 Măsuri avansate de securitate:
• Îmbunătățiri la nivelul kernelului pentru prevenirea exploatării vulnerabilităților de memorie (ASLR extins, măsuri mai severe de izolare a proceselor).

🛠️ Sistem de fișiere și rețea:
• Optimizări de performanță pentru FFS (Fast File System) și ZFS, alături de îmbunătățiri ale stack-ului de rețea IPv4/IPv6.

Conform celebrului lor motto "Of course it runs NetBSD", noua versiune demonstrează încă o dată flexibilitatea incredibilă a acestui sistem de operare! 🚀

#NetBSD #BSD #OpenSource #RISCV #Linux #SysAdmin #Unix #TechNews #SoftwareLibre

🚩 NetBSD 11.0 a fost lansat: Suport nativ pentru RISC-V și compatibilitate îmbunătățită cu Linux!

Noul update major al istoricului sistem de operare din familia BSD, NetBSD 11.0, este acum disponibil oficial, aducând îmbunătățiri remarcabile pe partea de suport hardware, performanță și securitate.

✨ Ce aduce nou NetBSD 11.0:

🏗️ Arhitectură RISC-V extinsă:
• Suport complet și îmbunătățit pentru hardware-ul bazat pe arhitectura deschisă RISC-V (atât pe 64 de biți, cât și pe 32 de biți), extinzând portabilitatea legendară a sistemului.

🐧 Compatibilitate mai bună cu pachetele Linux:
• Stratul de compatibilitate COMPAT_LINUX a primit actualizări majore, permițând rularea mai multor aplicații și utilitare native de Linux pe un kernel NetBSD.

⚡ Drivere și stivă grafică modernizate:
• Drivere grafice actualizate pentru procesoarele grafice moderne Intel, AMD și NVIDIA, oferind suport mai bun pentru accelerarea 3D și monitoare de înaltă rezoluție.

🔒 Măsuri avansate de securitate:
• Îmbunătățiri la nivelul kernelului pentru prevenirea exploatării vulnerabilităților de memorie (ASLR extins, măsuri mai severe de izolare a proceselor).

🛠️ Sistem de fișiere și rețea:
• Optimizări de performanță pentru FFS (Fast File System) și ZFS, alături de îmbunătățiri ale stack-ului de rețea IPv4/IPv6.

Conform celebrului lor motto "Of course it runs NetBSD", noua versiune demonstrează încă o dată flexibilitatea incredibilă a acestui sistem de operare! 🚀

#NetBSD #BSD #OpenSource #RISCV #Linux #SysAdmin #Unix #TechNews #SoftwareLibre

I've managed to build GNU Guix from source on Milk-V Jupyter RISC-V machine:
https://codeberg.org/guix/guix/issues/9898#issuecomment-20414228

The next step is to actually run Guix and check if "guix pull", "guix upgrade", "guix install" etc. work fine.

#guix #riscv

I've managed to build GNU Guix from source on Milk-V Jupyter RISC-V machine:
https://codeberg.org/guix/guix/issues/9898#issuecomment-20414228

The next step is to actually run Guix and check if "guix pull", "guix upgrade", "guix install" etc. work fine.

#guix #riscv

Двенадцать символов, двадцать один байт: как я научил голый RISC-V говорить «Привет, мир!»

Без библиотек, без обвязок, без операционной системы под ногами. Реальный код на реальном железе — ну, почти реальном. Пустая эмулируемая машина RISC-V, десяток строк ассемблера, и в терминале: Сначала думал вывести «hello», как все. Пусть будет «Привет, мир!» Ну, привет!

https://habr.com/ru/articles/1065554/

#RISCV #QEMU #bare_metal #UART #ассемблер #UTF8

｢ The Xen Project has just announced the release of Xen 4.22, a major update to the open-source type-1 hypervisor which includes new x86 capabilities, better power management for ARM guests, stronger Xenstore resource controls, and carries on the project’s initial efforts in the area of RISC-V virtualization ｣
https://linuxiac.com/xen-4-22-hypervisor-brings-new-x86-features-and-better-arm-power-management/

#xen #hypervisor #riscv #opensource

｢ The Xen Project has just announced the release of Xen 4.22, a major update to the open-source type-1 hypervisor which includes new x86 capabilities, better power management for ARM guests, stronger Xenstore resource controls, and carries on the project’s initial efforts in the area of RISC-V virtualization ｣
https://linuxiac.com/xen-4-22-hypervisor-brings-new-x86-features-and-better-arm-power-management/

#xen #hypervisor #riscv #opensource

Tweaking the #NixOS systemd-timer for the regular tmpfiles cleanup so our small #RISCV home server can do this in the hours at night

Tweaking the #NixOS systemd-timer for the regular tmpfiles cleanup so our small #RISCV home server can do this in the hours at night

#Espressif #ESP32 Chip Varianten im Vergleich - Update: neuer ESP32-S31

--> https://cool-web.de/esp8266-esp32/espressif-esp32-chip-varianten-im-vergleich.htm

Ich habe den neuen ESP32-S31 in RISC-V-Architektur mit in die Liste aufgenommen, der bei Espressif jetzt in die Massenproduktion geht.

#ESP32S31 #RISCV #Maker #Microcontroller

#Espressif #ESP32 Chip Varianten im Vergleich - Update: neuer ESP32-S31

--> https://cool-web.de/esp8266-esp32/espressif-esp32-chip-varianten-im-vergleich.htm

Ich habe den neuen ESP32-S31 in RISC-V-Architektur mit in die Liste aufgenommen, der bei Espressif jetzt in die Massenproduktion geht.

#ESP32S31 #RISCV #Maker #Microcontroller

Bad Apple but it's played on a protoflux risc-v emulator x3

Slight flashing lights warning, due to the display having a tearing effect.

#resonite #riscv #vr

Bad Apple but it's played on a protoflux risc-v emulator x3

Slight flashing lights warning, due to the display having a tearing effect.

#resonite #riscv #vr

A follow up to this as someone on Bluesky pointed me to an article which mentions a GCC toolchain that might allow llama.cpp with the IME2 extensions for the SpacemiT-K3 to be built from source instead of using the Bianbu binaries.
#AI #RISCV
https://github.com/ggml-org/llama.cpp/blob/master/docs/build-riscv64-spacemit.md
Ref: https://bsky.app/profile/did:plc:2r2e6zmohz6p4z654i6jewv5/post/3mrrnuhhpb22e

A follow up to this as someone on Bluesky pointed me to an article which mentions a GCC toolchain that might allow llama.cpp with the IME2 extensions for the SpacemiT-K3 to be built from source instead of using the Bianbu binaries.
#AI #RISCV
https://github.com/ggml-org/llama.cpp/blob/master/docs/build-riscv64-spacemit.md
Ref: https://bsky.app/profile/did:plc:2r2e6zmohz6p4z654i6jewv5/post/3mrrnuhhpb22e

Espressif begins mass production of ESP32-S31 wireless RISC-V SoC

https://fed.brid.gy/r/https://linuxgizmos.com/espressif-begins-mass-production-of-esp32-s31-wireless-risc-v-soc/

Gave up trying to run #opencode locally on the #RISCV box - far too slow under qemu. I've now tried it in WSL on my Windows/Arm laptop connected to the llama.cpp+qwen2.5 instance on the RISC-V K3 system and quite pleased with the results. Generated a basic piece of code fairly quickly. Definitely usable. Will be interesting to see how it copes with more complex queries.

Currently using the 3b version of the model but may try the 8b one too to see how it works - (when machine is otherwise idle)

Gave up trying to run #opencode locally on the #RISCV box - far too slow under qemu. I've now tried it in WSL on my Windows/Arm laptop connected to the llama.cpp+qwen2.5 instance on the RISC-V K3 system and quite pleased with the results. Generated a basic piece of code fairly quickly. Definitely usable. Will be interesting to see how it copes with more complex queries.

Currently using the 3b version of the model but may try the 8b one too to see how it works - (when machine is otherwise idle)

｢ The GNU Project has announced the release of GNU Binutils 2.47, a core component of the GNU toolchain, alongside gcc, glibc, and gdb, introducing additional RISC-V extension support, new assembler and linker options, and improvements to tools such as objdump and readelf ｣

https://linuxiac.com/gnu-binutils-2-47-released-with-new-risc-v-improvements/

#gnubinutils #binutils #riscv #opensource

｢ The GNU Project has announced the release of GNU Binutils 2.47, a core component of the GNU toolchain, alongside gcc, glibc, and gdb, introducing additional RISC-V extension support, new assembler and linker options, and improvements to tools such as objdump and readelf ｣

https://linuxiac.com/gnu-binutils-2-47-released-with-new-risc-v-improvements/

#gnubinutils #binutils #riscv #opensource

Thwarted! Was hoping to run #opencode (https://opencode.ai/) on my #RISCV system with the local llama.cpp LLM but seems its build and distribution requires the bun javascript runtime which means its platform support is quite limited <sigh>

Trying to run it under qemu and it's started up but still not settled down with qemu chewing over 200% CPU at the moment...

I'll edit this toot if it gets to a vaguely usable state

Thwarted! Was hoping to run #opencode (https://opencode.ai/) on my #RISCV system with the local llama.cpp LLM but seems its build and distribution requires the bun javascript runtime which means its platform support is quite limited <sigh>

Trying to run it under qemu and it's started up but still not settled down with qemu chewing over 200% CPU at the moment...

I'll edit this toot if it gets to a vaguely usable state

Coincidentally I was also looking for information on the SpacemiT-K3's AI capabilities and came across another of Bruno's articles. Interesting to see the performance figures here, and it's a real shame that - for now - it seems you have to ue prebuilt binaries to access the AI instructions with llama.cpp on Bianbu. But it does work. I have a local qwen2.5-coder running on mine. Just need a bit more work to let it do changes on the file system ...
#AI #RISCV #OpenSource
https://dev.to/gounthar/benchmarking-llamacpp-on-spacemit-k3-risc-v-ai-cores-vs-standard-rvv-part-4-10mc

Coincidentally I was also looking for information on the SpacemiT-K3's AI capabilities and came across another of Bruno's articles. Interesting to see the performance figures here, and it's a real shame that - for now - it seems you have to ue prebuilt binaries to access the AI instructions with llama.cpp on Bianbu. But it does work. I have a local qwen2.5-coder running on mine. Just need a bit more work to let it do changes on the file system ...
#AI #RISCV #OpenSource
https://dev.to/gounthar/benchmarking-llamacpp-on-spacemit-k3-risc-v-ai-cores-vs-standard-rvv-part-4-10mc

PineVoice RISC-V smart speaker supports local wake-word detection for Home Assistant

https://fed.brid.gy/r/https://linuxgizmos.com/pinevoice-brings-local-voice-control-to-home-assistant/

From FUZxxl:

> SIMD programming challenge: take a vector v and a mask m segmenting it into k segments. Given a (variable) permutation π with k entries, shuffle the segments of v into the order given by π (segment-wise shuffle). How would you approach this problem?

My approach is to run-length-encode the offset of the start of each segment, apply the permutation, decode the RLE-offsets and finally fixup the offsets for the second to last element of each segment. This gives you the shuffle you can apply to the input.

Here is the RVV implementation: https://github.com/camel-cdr/rvv-playground/blob/main/segment-vrgather.c (https://godbolt.org/z/dMhxz84hz)

I've attached an image of an execution log to help visualize this.

#simd #riscv

From FUZxxl:

> SIMD programming challenge: take a vector v and a mask m segmenting it into k segments. Given a (variable) permutation π with k entries, shuffle the segments of v into the order given by π (segment-wise shuffle). How would you approach this problem?

My approach is to run-length-encode the offset of the start of each segment, apply the permutation, decode the RLE-offsets and finally fixup the offsets for the second to last element of each segment. This gives you the shuffle you can apply to the input.

Here is the RVV implementation: https://github.com/camel-cdr/rvv-playground/blob/main/segment-vrgather.c (https://godbolt.org/z/dMhxz84hz)

I've attached an image of an execution log to help visualize this.

#simd #riscv

The RISC-V ISA is crossing the chasm from hobbyist microcontrollers to datacenter-grade CPUs. SiFive, Ventana, and Rivos are shipping serious silicon while the software stack (LLVM, Linux, Debian) catches up. The open model works - no license fees, custom extensions, and a global talent pool driving innovation. #RISCV #OpenSource #Hardware #Linux #Embedded #OpenISA

The RISC-V ISA is crossing the chasm from hobbyist microcontrollers to datacenter-grade CPUs. SiFive, Ventana, and Rivos are shipping serious silicon while the software stack (LLVM, Linux, Debian) catches up. The open model works - no license fees, custom extensions, and a global talent pool driving innovation. #RISCV #OpenSource #Hardware #Linux #Embedded #OpenISA

RISC-V Is Inevitable, State of the Union Keynote Argues - EE Times

https://www.eetimes.com/risc-v-is-inevitable-state-of-the-union-keynote-argues/

#riscv #RVA23 #opensource

RISC-V Is Inevitable, State of the Union Keynote Argues - EE Times

https://www.eetimes.com/risc-v-is-inevitable-state-of-the-union-keynote-argues/

#riscv #RVA23 #opensource

Running DOOM is cool. Building the CPU that runs it is cooler.

This write-up follows the journey from designing a custom RISC-V processor to FPGA implementation and using DOOM to validate the design.

Excellent hardware/software co-design read.

https://armaangomes.com/blogs/doom/

#embedded #riscv #fpga

Running DOOM is cool. Building the CPU that runs it is cooler.

This write-up follows the journey from designing a custom RISC-V processor to FPGA implementation and using DOOM to validate the design.

Excellent hardware/software co-design read.

https://armaangomes.com/blogs/doom/

#embedded #riscv #fpga

Keeping the 2*8 cores (not threads!) of this SpacemiT-K3 busy #RISCV

Keeping the 2*8 cores (not threads!) of this SpacemiT-K3 busy #RISCV

EMiX extends FPGA emulation beyond the limits of a single board by partitioning RISC-V SoCs across multiple interconnected FPGAs. The authors demonstrate a Linux-capable 64-core system spanning 8 FPGAs and plan to open-source the framework.
https://arxiv.org/abs/2604.27012
#RISCV #FPGA

EMiX extends FPGA emulation beyond the limits of a single board by partitioning RISC-V SoCs across multiple interconnected FPGAs. The authors demonstrate a Linux-capable 64-core system spanning 8 FPGAs and plan to open-source the framework.
https://arxiv.org/abs/2604.27012
#RISCV #FPGA

The Milk-V Titan finally arrived! 🎉

#RISCV

The Milk-V Titan finally arrived! 🎉

#RISCV

New #riscv Fast-Track Proposal: Zijf (Far jumps and calls):

https://github.com/riscv/riscv-isa-manual/pull/3269

A) should've been defined way earlier
B) remember the Qualcomm slides (https://lists.riscv.org/g/tech-profiles/attachment/400/0/AOSP%20Compression.pdf)

New #riscv Fast-Track Proposal: Zijf (Far jumps and calls):

https://github.com/riscv/riscv-isa-manual/pull/3269

A) should've been defined way earlier
B) remember the Qualcomm slides (https://lists.riscv.org/g/tech-profiles/attachment/400/0/AOSP%20Compression.pdf)

The #SpacemiT #RV23 #RISCV hardware dev platform just keeps on growing

The #SpacemiT #RV23 #RISCV hardware dev platform just keeps on growing

Fixing #RISCV cross-compilation and usage of @gotosocial on @nixos_org 🚀 https://github.com/NixOS/nixpkgs/pull/544570

You need a 1234 GiB GPU to run your program?
Let me play you the tiniest... #microcontroller breakout board!

The 10-cent CH32V003 microcontroller and a single capacitor make a complete breakout board. Honestly, I didn't even need the PCB. The capacitor could be soldered directly on the pins.

I flashed it with the #Arduino . Not so "Nano" in comparison! #ESP32 for scale.

And it has #Rust support!

#rustlang #riscv #DIY #electronics