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#picoice — Public Fediverse posts

Live and recent posts from across the Fediverse tagged #picoice, aggregated by home.social.

  1. Not having based live debug for the was a little annoying

    so I am hoping to revive the small pipelinec project that was sorta a build your own chipscope attempt 🤙 and demo that on the pico ice

  2. Not having #AMD #Xilinx #Vivado #Chipscope based live #hardware debug for the #picoice #Lattice #ice40 #FPGA was a little annoying

    so I am hoping to revive the small pipelinec project that was sorta a build your own chipscope attempt 🤙 and demo that on the pico ice

  3. Not having #AMD #Xilinx #Vivado #Chipscope based live #hardware debug for the #picoice #Lattice #ice40 #FPGA was a little annoying

    so I am hoping to revive the small pipelinec project that was sorta a build your own chipscope attempt 🤙 and demo that on the pico ice

  4. Not having #AMD #Xilinx #Vivado #Chipscope based live #hardware debug for the #picoice #Lattice #ice40 #FPGA was a little annoying

    so I am hoping to revive the small pipelinec project that was sorta a build your own chipscope attempt 🤙 and demo that on the pico ice

  5. Not having #AMD #Xilinx #Vivado #Chipscope based live #hardware debug for the #picoice #Lattice #ice40 #FPGA was a little annoying

    so I am hoping to revive the small pipelinec project that was sorta a build your own chipscope attempt 🤙 and demo that on the pico ice

  6. Two of the reasons I am not using the @olimex #Gatemate boards are that they do not have usb host nor DVI.

    But then the #picoice also does not have them.

    Do you have a a web page about your boards?

    @goran_mahovlic @olimex @nlnet

  7. ^^^ Is an excellent video describing how the FemtoRV works. I will soon be comparing #Mecrisp #ice with Risc-V, so the timing is almost perfect.

    #forth #fpga #PicoIce #MecrispIce #riscv #Lattice #Mecrisp

    @Mecrisp @BrunoLevy01

  8. @olimex I think that both your board and the #picoice are fantastic. The combination of an #RP2040 and an #FPGA is both powerful and inexpensive. I think I prefer your #gatemate fpga, but I prefer their sdk. github.com/tinyvision-ai-inc/p
    I like your ps2 and vga ports but I would prefer 2 usb host ports. Which pico-ice also does not have.
    I like that they have two flash memories, one for the rp2040, and one for the fpga.

    All we can do is to choose between the boards that are available to us.

  9. Konilo looks really interesting. A big brother to #uxn. UXN had 8bit memory cells. Like the discontinued z80. 32 bit memory makes much more sense to me.

    Would you like a version of this running on an #FPGA? On a $35 pico-ice? #forth
    @crc #picoice

  10. I now have a blinky running on my #picoice board generated using #SpinalHDL and APIO.

    Getting the initial J!Sc running on a non supported board looks quie difficult because of all of its additional features.

  11. If anyone is playing with the new fpga devboard. There might be a bug in the firmware for transferring uf2 bitstream to the ice40. I was unable to use apio upload or dragging a uf2 into the pico-ice drive. only use `dfu-utils -d 1209:b1c0 -a 1 -D firmware.bin` worked for me. Or using the ice-makefile-blinky example, which automates the same command.

    discord.com/channels/644405956

  12. I am interested in building a #uxn cpu on an #fpga.
    I have already built #Mecrisp #Forth on the #PicoIce.
    A Uxn cpu is just a slightly different stack machine.
    Maybe I will eventually build an entire Varvara computer on an FPGA.

    @neauoire
    @rek

    forth.pythonlinks.info/hana-ux

  13. My flashing echo server flashes when a person types a character on the PC. Is the echo server correctly installed? Hold down the FPGA button, and it blinks green, to demonstrate that all is well.

    #picoice

  14. I now have a flashing echo server working on the #picoice. Type a character, it flashes.

    This will be needed for people to debug the RP2040 pass through for multiple languages.

    Next, I want to use the FPGA reset button to flash, so that the person installing it, knows that it is done corectly.
    #forth #micropython.

  15. I received an #upduino and a #picoice circuit board this week, got the basic tools working, and am working on an echo server. Soon I will be building a #Mecrisp #Forth core.

    I am giving a talk on #Forth this week at the #fpgaworld conference in stockholm.
    #fpga

  16. Here is my best estimate as to when the Hana processor will ship. Maybe the word guess is more accurate than estimate.

    I will update it as things change. #forth #mecrisp #picoice

    forth.pythonlinks.info/ship-sc

    Thank you @jemo07 for pushing me to ship the product sooner.

  17. So although it uses the #ICE40, it is by a different manufacturer than the #picoice, so the pins that connect the USB chip to the FPGA chip may be different, in which case it will need a different bitstream. Sigh.

    @jemo07

  18. @PythonLinks I do like the look of that ! I'm sure runs on the RP2040 but are there any extensions to, say, deploy to the iCE40 from MicroPython?

  19. It turns out that #MicroPython works on the #PicoIce. The power, USB, and flash pins are the same on all boards.
    @matt_trentini

  20. #ZeptoForth boots on the #picoice. It is written in RP2040 assembly, is reportedly very small, and supports the programming model of communicating sequential processes, just like GoLang.
    @jemo07

  21. #ZeptoForth boots on the #PicoIce, which means that the default power, usb and flash pins are correctly connected. Which means that #MicroPython and #Mecrisp probably boot as well.

    As soon as I get my #FPGA working on the #Upduino, I want to buy a Pico-Ice, and check out the REPLs..

  22. I would love to see a port of #MicroPyton to the #PicoIce board. Then I could work with #FPGA and MicroPython.

    @matt_trentini

  23. Sadly the #J1 processor requires dual port RAM, and there are at most 80Kbits of dual port RAM on the ICE40 FPGA's. The J1 cannot use the #1Mbit of available single port RAM.

    Single Port RAM uses less resources, and the devices are so much cheaper. Only $35 for the #PicoIce board.

    So that is the first thing I have to fix. I think I can do this.
    #Forth. #Verilog #Mecrisp

  24. @M0CUV
    Dr. Ting's documentation was off the chart awesome.
    "I felt like I was there."
    I worry that with Dr. Ting's passing, other Forths will be growing more rapidly.
    I want to know what are the most popular #Forth versions nowadays.
    In particular which is the best for the #RP2040 processor in the #PicoIce processor.
    And there is a version of #Mecrisp Ice processor with 27 instructions. I was reading its Verilog this morning.

  25. Necrisp-ice supports double length numbers with. 2dub 2over, 2drop and 2swap.

    I had a long conversation with a MicroMouse contestant about using a 4 stack Forth processor. He wanted 32 bit numbers. We thought about supporting them, but what happens when he wants to do rot3, that is six deep on the stack.

    We agreed to do a 24 bit processor, plenty of LUTS on the #picoice board.

    With a pause option, I think I could even get Mecrisp Ice to work with single port memory.

    @Mecrisp

  26. I am building a many core #Forth processor on Lattice Semiconductor FPGAs using the open source #Yosys tools. The first products released will be two 4 core processors. 16K* 16 bit words or 10.6K * 24 bit words. Every pair of processors will communicate using 10Kbits of dual port RAM. The processors will run on the $35 #PicoIce and $30 #Upduino boards. Later there will be hundreds of cores on the larger #ULX3S #ECP5 boards.

    My climate persona: @UncensoredNews
    #fpga #ManyCore #introduction