PipelineC

The StreamSoC demo is a fun music visualizer and video feedback experiment.
But also is a reference for how easy PipelineC makes it to design your own SoC.
Happy to help anyone give their own project a try!

https://github.com/JulianKemmerer/PipelineC/wiki/Example:-StreamSoC

A SoC in C? StreamSoC shows how to move from embedded C software to custom PipelineC hardware for doing things like realtime streaming data processing.

https://youtu.be/dzF3okigyog

Fun in the frequency domain 🤓 Camera pointed at it's own display also showing audio FFT for cool glitchy visualizer effect. Video processing all done in PipelineC hardware. And how?

https://github.com/JulianKemmerer/PipelineC/wiki/Example:-Video-Pipelines

#hardware #fpga #dsp #rtl #hdl #hls #verilog #vhdl #pipelinec

@nlnet NLnet Foundation funded open source WireGuard router in FPGA. Featuring PipelineC for cryptography blocks 🤓

https://github.com/JulianKemmerer/PipelineC/wiki/Example:-ChaCha20%E2%80%90Poly1305-for-WireGuard

#hardware #fpga #rtl #hdl #hls #verilog #vhdl #cryptography #wireguard #pipelinec

PipelineC holds the throughput lead on Latchup.app. For now! How does your design stack up against a pipelining tool? Far too time consuming and fun of a site 🤓 Look forward to seeing competing solutions.

https://github.com/JulianKemmerer/PipelineC/wiki/Example:-Latchup-Solutions

#fpga #asic #rtl #hdl #verilog #vhdl #hls #eda

Existing libraries help: memory mapping is as simple as a struct. All stitched together with valid ready handshaking 'streams'. Writes done over StreamSoC's AXI-Lite like 'shared resource bus' that comes with helper FSMs

https://github.com/JulianKemmerer/PipelineC/wiki/Shared-Resource-Bus

#hardware #fpga #rtl #hls #hdl #graphics #gpu #cpu

Easy: draw_rect_t struct shared between embedded C software and PipelineC hardware. Mem mapped registers enqueue into command FIFO. Small hardware FSM reads from cmd FIFO does simple iteration to draw a rect of pixels.

https://github.com/JulianKemmerer/PipelineC/tree/master/examples/stream_soc/gpu

#hardware #fpga #rtl #hls #hdl #graphics #gpu #cpu

Is a hardware FSM that draws rectangles to a frame buffer a GPU? Well whatever you call it, it's no longer the CPU pushing pixels in the PipelineC StreamSoC design. Now it sends 'draw rectangle' commands to hardware. And how? #hardware #fpga #rtl #hls #hdl #graphics #gpu #cpu

Check out PipelineC #HDL Advent of FPGA #hardware solutions: high perf, deeply pipelined, multiple #FPGA platforms, 10's Gbit per sec throughput, easily scales: variable latency off chip mem, faster off chip IO and more resources.

https://github.com/JulianKemmerer/PipelineC/wiki/Example:-Advent-of-Code-2025

#rtl #hls #verilog #vhdl #asic #eda

Advent of Code Day 5: Iterates over RAM holding fresh ID ranges. Autopipeline checks N IDs against M ranges each cycle. Easily does N=3,M=2 at ~235MHz, ~1.4 billion ID-in-range checks computed per sec 😎

https://github.com/JulianKemmerer/PipelineC/blob/master/examples/aof25/day5.c

#aoc25 #fpga #hardware #verilog #vhdl #hdl #rtl #hls #asic #eda

Advent of Code Day 7: very simple design, good intro to #pipelinec. processing all ~hundreds of elements of an entire line each cycle. ~600 million to ~5.3 billion tachyon beams splitting per second. 😎

https://github.com/JulianKemmerer/PipelineC/blob/master/examples/aof25/day7.c

#aoc25 #fpga #hardware #verilog #vhdl #hdl #rtl #hls #asic #eda

Advent of Code Day 4: video-like stream of 'pixel' data to a sliding 3x3 window via line buffer fifos. Auto pipeline for kernel function (counting neighbors), ~150M windows per sec. https://github.com/JulianKemmerer/PipelineC/blob/master/examples/aof25/day4.c

#fpga #rtl #hdl #hls #aoc25

Advent of Code Day 9: Iterates over RAM holding points. Autopipeline computes N rectangle areas per clock cycle and finds max. Easily does N=4 at ~100MHz with few pipeline stages, ~400M rect areas computed per sec 🎄

https://github.com/JulianKemmerer/PipelineC/blob/master/examples/aof25/day9.c

#fpga #rtl #hdl #hls #aoc25

Advent of Code Day 3 pipelined no back pressure. N ascii chars as input each cycle. finding max pair of digits pipelined arbitrarily. 8 chars of input each cycle? no problem to get FMAX of 100+MHz.

~1 Gbyte per sec of ascii could be processed 😎 🎄
https://github.com/JulianKemmerer/PipelineC/blob/master/examples/aof25/day3.c #aoc25 #fpga #hdl #hls

How to send a struct from one dev board to another? A PipelineC Story

#hdl #hls #RTL #fpga #ethernet #i2s #hardware

https://www.reddit.com/r/FPGA/comments/1m8gl5o/how_to_send_a_struct_from_one_dev_board_to_another/

Check out @dutracgi 's very cool #16APSK #FPGA Modulator written in #PipelineC #HDL !
#dsp #sdr #rf #apsk #dac #deltasigma #space #qam #radio #hardware https://www.linkedin.com/pulse/16-apsk-modulator-fpga-using-pipelinec-hdl-paulo-dutra-79uce/?trackingId=ldQbwhDmRd%2BU7F35jVGjAQ%3D%3D

So what can you do with the ability to read arbitrary #FPGA registers out of your design over #UART? Capture time series data (last four #ethernet packet bytes) in your regs and write a little #python script that launches #GTKWave and you have yourself a tiny homemade cross platform logic analyzer thing!
https://github.com/JulianKemmerer/PipelineC/wiki/Example:-Debug-Probes

Say I am debugging an #ethernet project on the #ice40 #fpga of pico-ice board. I want to know the contents of some registers down in my design (which destination MAC address my #hardware tried to transmit). I don't want to use manufacturer specific ILAs and don't want to hand route a bunch of debug signals to my top level for external #debug equipment I don't have.

In PipelineC just assign to a globally visible #UART debug probe wire:
https://github.com/JulianKemmerer/PipelineC/wiki/Example:-Debug-Probes

Not having #AMD #Xilinx #Vivado #Chipscope based live #hardware debug for the #picoice #Lattice #ice40 #FPGA was a little annoying

so I am hoping to revive the small pipelinec project that was sorta a build your own chipscope attempt 🤙 and demo that on the pico ice

Yay those cheap #hardware #ethernet phy #pmod -LIKE things work with the pico-ice #ice40 #FPGA . Thanks for your help with RMII interface @dutracgi ! #embedded #HDL #RTL #Verilog #VHDL #HLS https://github.com/JulianKemmerer/PipelineC/blob/master/examples/pico-ice/ice_makefile_pipelinec/ethernet_top.c

Learn PipelineC #HDL basics featuring the pico-ice dev board from tinyVision.ai! It has a Lattice Semiconductor @latticesemi #ice40 #FPGA and @Raspberrypi. This intro covers #LED, #UART, and #VGA projects using OSS CAD Suite tools. #hardware #RTL #Verilog #VHDL #HLS
https://www.youtube.com/watch?v=wWdvuAQXeS0

Don't forget the intro to pipelinec talk is just over 24 hours away! See you there folks 🤓
#HDL #ice40 #fpga #RaspberryPi #hardware #RTL #Verilog #VHDL #HLS

Come learn some PipelineC #HDL basics featuring the pico-ice dev board from tinyVision.ai! It has a Lattice Semiconductor @latticesemi #ice40 #FPGA and @Raspberrypi. This intro talk will cover #LED, #UART, and #VGA projects using OSS CAD Suite tools. #hardware #RTL #Verilog #VHDL #HLS

In the mood for the littlest bit of #FPGA #GameDev? 🤓 Check out this pico-ice based #pong demo. Just need #VGA #pmod and #UART connected to host PC. #HDL #hardware #RTL #Verilog #VHDL #HLS #lattice #ice40 https://github.com/JulianKemmerer/PipelineC/blob/master/examples/pico-ice/ice_makefile_pipelinec/pong_top.c

Come on over to the Discord channel if you want to join the conversation about this fun work 🤓 https://discord.gg/vBUtmBZcxC #FPGA #raspberrypi #pico-ice #PipelineC #HDL #Verilog #VHDL

Have been super pleased with the #ice40 #FPGA and #raspberrypi board that https://pico-ice.tinyvision.ai/ sent me to experiment with. Many thanks and I look forward to putting together a talk for intro users getting started with #PipelineC and boards like the pico-ice 🤓 #HDL #Verilog #VHDL #hardware #embedded

Over at Digital Design HQ #ddhq, I'm documenting and discussing a #hardware #FPGA #I2S #audio #pmod to-from #AXI project. Stop on by 👋 and see how nice it is to work in #PipelineC 🤓 #RTL #HDL #HLS https://discord.gg/ceheSfKzRM

#graphics #demoscene folks: What's possible with just a few hundred bits of memory? Make custom #ASIC #hardware. #PipelineC friends @suarezvictor and @dutracgi have done LARGE #FPGA demos in the past. Now the challenge is to be very SMALL! 🤓
https://tinytapeout.com/competitions/demoscene/

Anyone want to help make a #PipelineC version of @DG3YEV 's #FPGA real time #FFT display but for audio? Have Arty w/ #pmod ready to go for testing. Picturing the start of some kind of #hardware #audio visualizer 🤩 with more #DSP learning along the way 🤓
https://x.com/Dg3Yev/status/1796857709276373211

@tsalvo Just saw your work in progress on the stack #CPU implementation in #PipelineC 👋 . Great work, how neat! Hope it has gone well and as always happy to help! 🤓 #uxn #varvara #AnaloguePocket #FPGA #stackmachine #FPGA #HDL https://github.com/tsalvo/varvara-fpga

Dream is more generic pipelined compute accelerator #hardware. #photogrammetry next ? Want to allow for custom dataflow to-from memories managed by one or more #CPU threads. Always looking for anyone who wants to help, plenty of work to do. Come chat on Discord 🤓 https://discord.gg/7DECDMvbmc
#HDL #FPGA #HLS #PipelineC

What kind of fixed point (or small floating point) shaders without textures do yall #graphics folks know of? I know @BrunoLevy01 had that great link I need to dig into still 🙌 🤓

#FPGA #RISCV #hardware #hdl #vhdl #verilog #PipelineC #HLS #graphics

https://x.com/BrunoLevy01/status/1746927953865322628

#RISCV #CPU out of the #graphics rendering loop ~DMA style: only limited by the direct connection memory bandwidth to-from DDR controller and the compute pipeline 🔥
#FPGA #hardware #HDL #PipelineC #HLS #HPC

#PipelineC pure function autopipelining combined with libraries for sharing hardware resources with ~AXI like buses + arbitration made this all possible. #fpga #hdl #hls #graphics #SoC #RISCV

1/4 as many RV32I @risc_v cores for same or better performance. Threads share #PipelineC auto pipelined ~15 stage kernel() hardware function to offload shader compute. CPU is now bottleneck for moving data around from RAM to pipeline and back.
#FPGA #HDL #RTL #graphics #riscv

C code that each thread is running: https://github.com/JulianKemmerer/PipelineC/blob/5ec0258cae9bf18d2073be2fb59b4a29b3cd98e0/examples/risc-v/gcc_test/frame_buffer_test.c#L43

C code and #PipelineC play nicely together for when hardware and software need to share interfaces/types 🤓

Code for the barrel #RISCV CPUs in #PipelineC https://github.com/JulianKemmerer/PipelineC/blob/master/examples/risc-v/barrel_risc-v.c

Four RV32I @risc_v cores totaling ~333M IPS do work with a 480p frame buffer 🤓. 20 threads, ~software rendering, but focus isn't on CPU core, next up: experiments with custom accelerator pipelines to offload compute 😏 #PipelineC
#FPGA #HDL #RTL #graphics #RISCV Thanks @BrunoLevy01 and friends!

Use #PipelineC to listen to FM #radio with an #FPGA #SDR! Huge thanks to @dutracgi and @Darkknight512 for making this first version a great learning experience. And @deepwavedigital for the fantastic hardware platform and workplace <3
#hardware #hdl #hls #asic
https://github.com/JulianKemmerer/PipelineC/wiki/Example:-FM-Radio-Demodulation

Very cool work from @DutraCGI , love trying to follow along 😅 🤓

#QAM16 Modulator made with #PipelineC simulation with #GHDL and cocotb! Raised Cosine filter with 0.35 rollof and 4 samples/symbol !
#fpga #qam #sdr #dsp

https://x.com/DutraCGI/status/1715912210910724185?s=20

If the problem is given in the right language, doing RTL digital design like #UART RX can be made as simple as a typical #cprogramming problem.
Any more #embedded #software folks out there want to give the puzzle a go? 🤓
#clang #softwaredevelopment #HDL #HLS #RTL #FPGA #ASIC #hardware #microcontroller #pipelinec
https://github.com/JulianKemmerer/PipelineC/wiki/C-Puzzle

PipelineC's new 'shared resource buses' are pretty neat: Multiple 'threads' of C function derived state machines can easily share resources (memory, compute, etc) by generating AXI-like buses and arbitration. This is still highly experimental but very powerful - reach out if you want to make something together! https://github.com/JulianKemmerer/PipelineC/wiki/Shared-Resource-Bus #rtl #hdl #hls #vhdl #verilog #asic #hardware #multithreaded #hpc

Frame buffers are the "shared resource" in the recent Game of Life demo. PipelineC generates arbitration between multiple state machine 'threads' simultaneously reading+writing the buffers. What can you do with C code and a frame buffer? https://github.com/JulianKemmerer/PipelineC/wiki/Shared-Resource-Bus#graphics-demo #rtl #hdl #hls #vhdl #verilog #asic #hardware #multithreaded #hpc #computergraphics

'C code' Game of Life in #FPGA at 48FPS 🤓 PipelineC derived state machines and new shared resource buses make it super easy to adapt multi-threaded software C implementations for quick FPGA prototypes. Highly experimental but very powerful - reach out if you want to make something together! https://github.com/JulianKemmerer/PipelineC/wiki/Shared-Resource-Bus#game-of-life-demo
#rtl #hdl #hls #vhdl #verilog #asic #hardware #multithreaded #hpc #computergraphics