#vivado — Public Fediverse posts
Live and recent posts from across the Fediverse tagged #vivado, aggregated by home.social.
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As of today, I am claiming credit as the first Shure associate in the 101 year history of Shure Incorporated to officially contribute to an open source project by completing our new Open Source Contribution process!
Thank you Gwenhael Goavec-Merou for maintaining the excellent openFPGALoader project!
https://github.com/trabucayre/openFPGALoader/pull/685
#Shure #openFPGALoader #FPGA #Xilinx #Vivado #AMD #JTAG #FOSS
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As of today, I am claiming credit as the first Shure associate in the 101 year history of Shure Incorporated to officially contribute to an open source project by completing our new Open Source Contribution process!
Thank you Gwenhael Goavec-Merou for maintaining the excellent openFPGALoader project!
https://github.com/trabucayre/openFPGALoader/pull/685
#Shure #openFPGALoader #FPGA #Xilinx #Vivado #AMD #JTAG #FOSS
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As of today, I am claiming credit as the first Shure associate in the 101 year history of Shure Incorporated to officially contribute to an open source project by completing our new Open Source Contribution process!
Thank you Gwenhael Goavec-Merou for maintaining the excellent openFPGALoader project!
https://github.com/trabucayre/openFPGALoader/pull/685
#Shure #openFPGALoader #FPGA #Xilinx #Vivado #AMD #JTAG #FOSS
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As of today, I am claiming credit as the first Shure associate in the 101 year history of Shure Incorporated to officially contribute to an open source project by completing our new Open Source Contribution process!
Thank you Gwenhael Goavec-Merou for maintaining the excellent openFPGALoader project!
https://github.com/trabucayre/openFPGALoader/pull/685
#Shure #openFPGALoader #FPGA #Xilinx #Vivado #AMD #JTAG #FOSS
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As of today, I am claiming credit as the first Shure associate in the 101 year history of Shure Incorporated to officially contribute to an open source project by completing our new Open Source Contribution process!
Thank you Gwenhael Goavec-Merou for maintaining the excellent openFPGALoader project!
https://github.com/trabucayre/openFPGALoader/pull/685
#Shure #openFPGALoader #FPGA #Xilinx #Vivado #AMD #JTAG #FOSS
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Posted to: #openFPGALoader #irc channel:
Hello. I'm new here. I was in need of support for indirect flashing of a flash part that is not supported by #vivado. I am working on adding support for the #Winbond W25Q256PW and #Xilinx XCAU7P-1SBVC484E, and have a working prototype. I will push it to my fork. Would this be a contribution others are interested in?
I also produced a PR:
https://github.com/trabucayre/openFPGALoader/pull/680#FOSS tools are great. I couldn't have added this support to #vivado without a binary patch.
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Posted to: #openFPGALoader #irc channel:
Hello. I'm new here. I was in need of support for indirect flashing of a flash part that is not supported by #vivado. I am working on adding support for the #Winbond W25Q256PW and #Xilinx XCAU7P-1SBVC484E, and have a working prototype. I will push it to my fork. Would this be a contribution others are interested in?
I also produced a PR:
https://github.com/trabucayre/openFPGALoader/pull/680#FOSS tools are great. I couldn't have added this support to #vivado without a binary patch.
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Posted to: #openFPGALoader #irc channel:
Hello. I'm new here. I was in need of support for indirect flashing of a flash part that is not supported by #vivado. I am working on adding support for the #Winbond W25Q256PW and #Xilinx XCAU7P-1SBVC484E, and have a working prototype. I will push it to my fork. Would this be a contribution others are interested in?
I also produced a PR:
https://github.com/trabucayre/openFPGALoader/pull/680#FOSS tools are great. I couldn't have added this support to #vivado without a binary patch.
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Posted to: #openFPGALoader #irc channel:
Hello. I'm new here. I was in need of support for indirect flashing of a flash part that is not supported by #vivado. I am working on adding support for the #Winbond W25Q256PW and #Xilinx XCAU7P-1SBVC484E, and have a working prototype. I will push it to my fork. Would this be a contribution others are interested in?
I also produced a PR:
https://github.com/trabucayre/openFPGALoader/pull/680#FOSS tools are great. I couldn't have added this support to #vivado without a binary patch.
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Posted to: #openFPGALoader #irc channel:
Hello. I'm new here. I was in need of support for indirect flashing of a flash part that is not supported by #vivado. I am working on adding support for the #Winbond W25Q256PW and #Xilinx XCAU7P-1SBVC484E, and have a working prototype. I will push it to my fork. Would this be a contribution others are interested in?
I also produced a PR:
https://github.com/trabucayre/openFPGALoader/pull/680#FOSS tools are great. I couldn't have added this support to #vivado without a binary patch.
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Создаем I2C Master Controller на Verilog. Перенос на Zynq 7000 (bare-metal)
После успешной отладки на плате с Cyclone IV пришла пора перенести наработки на плату Zynq Mini c XC7Z020. В этой статье я опишу, каким образом можно организовать вывод нужной нам информации из PS-части Zynq на дисплей который подключен к EMIO на выводах PL. Сделаем обновленный модуль i2c_master_axi который добавляет сверху к уже разработанному ядру поддержку AXI4-Lite Slave, сделаем сборку проекта, подключим их к PS и проверим в bare-metal сценарии. После того как это будет все работать - переходить к Linux уже будет гораздо проще. Всем заинтересованным добро пожаловать под кат!
https://habr.com/ru/companies/beget/articles/1037124/
#zynq7000 #zynqmini #oled #ssd1306 #verilog #baremetal #tutorial #vivado #vitis
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Создаем I2C Master Controller на Verilog. Перенос на Zynq 7000 (bare-metal)
После успешной отладки на плате с Cyclone IV пришла пора перенести наработки на плату Zynq Mini c XC7Z020. В этой статье я опишу, каким образом можно организовать вывод нужной нам информации из PS-части Zynq на дисплей который подключен к EMIO на выводах PL. Сделаем обновленный модуль i2c_master_axi который добавляет сверху к уже разработанному ядру поддержку AXI4-Lite Slave, сделаем сборку проекта, подключим их к PS и проверим в bare-metal сценарии. После того как это будет все работать - переходить к Linux уже будет гораздо проще. Всем заинтересованным добро пожаловать под кат!
https://habr.com/ru/companies/beget/articles/1037124/
#zynq7000 #zynqmini #oled #ssd1306 #verilog #baremetal #tutorial #vivado #vitis
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While not as ubiquitous as the two big ones, there *are* #FPGA vendors that embrace #FOSS toolchains. So, given #AMD's license blunder with #vivado free version not available for #Linux anymore, I'll push for companies like #CologneChip wherever I can (which is also #digitalsoveignty for those who care): https://colognechip.com/
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While not as ubiquitous as the two big ones, there *are* #FPGA vendors that embrace #FOSS toolchains. So, given #AMD's license blunder with #vivado free version not available for #Linux anymore, I'll push for companies like #CologneChip wherever I can (which is also #digitalsoveignty for those who care): https://colognechip.com/
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Запуск Vivado 2019.1 на Orange Pi 3 LTS через QEMU
Если вам интересно как выглядит работа Vivado на одноядерном ARM процессоре с частотой 1.8 ГГц, и 2 Гб ОЗУ, то я вам это покажу, и расскажу, как я запустил и успешно прошил плату (ДА! Собрал проект и прошил).
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MiniMig RTG Progress: AmiCube FPGA Roadmap Gets Clearer
#AmiCube #MiniMig #FPGA #Amiga #RTG #Spartan7 #Vivado #RetroComputing #OpenSourceHardware #PiStorm
https://theoasisbbs.com/minimig-rtg-progress-amicube-fpga-roadmap-gets-clearer/?feed_id=7369&_unique_id=69553d540c10f -
MiniMig RTG Progress: AmiCube FPGA Roadmap Gets Clearer
#AmiCube #MiniMig #FPGA #Amiga #RTG #Spartan7 #Vivado #RetroComputing #OpenSourceHardware #PiStorm
https://theoasisbbs.com/minimig-rtg-progress-amicube-fpga-roadmap-gets-clearer/?feed_id=7369&_unique_id=69553d540c10f -
MiniMig RTG Progress: AmiCube FPGA Roadmap Gets Clearer
#AmiCube #MiniMig #FPGA #Amiga #RTG #Spartan7 #Vivado #RetroComputing #OpenSourceHardware #PiStorm
https://theoasisbbs.com/minimig-rtg-progress-amicube-fpga-roadmap-gets-clearer/?feed_id=7369&_unique_id=69553d540c10f -
MiniMig RTG Progress: AmiCube FPGA Roadmap Gets Clearer
#AmiCube #MiniMig #FPGA #Amiga #RTG #Spartan7 #Vivado #RetroComputing #OpenSourceHardware #PiStorm
https://theoasisbbs.com/minimig-rtg-progress-amicube-fpga-roadmap-gets-clearer/?feed_id=7369&_unique_id=69553d540c10f -
MiniMig RTG Progress: AmiCube FPGA Roadmap Gets Clearer
#AmiCube #MiniMig #FPGA #Amiga #RTG #Spartan7 #Vivado #RetroComputing #OpenSourceHardware #PiStorm
https://theoasisbbs.com/minimig-rtg-progress-amicube-fpga-roadmap-gets-clearer/?feed_id=7369&_unique_id=69553d540c10f -
Новое поколение ПЛИС это не только про повышение частоты…
Прослеживается тенденция, что сложность CLB повышается, сами примитивы становятся хитрее. От сюда вытекает вопрос, а на сколько эффективными становятся ячейки, и сколько ресурсов ПЛИС они экономят в сравнении с предыдущими поколениями?
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#FPGA dorks. I'm running into an issue where #vivado says: multiple drivers on MMCM pins when I use a known good block (LVDS deserializer from appnote xapp523) in the vivado block diagram for a 7 series #xilinx #zynq part (snickerdoodle black). I get the error even if I pin out directly to top level pins. I hate using the gui because it hides too much magic. Has anyone hit this madness before?
I'm trying to deserialize a 1.024 Mbps 8b10b lvds to get it on the linux side for storage on disk.
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#FPGA dorks. I'm running into an issue where #vivado says: multiple drivers on MMCM pins when I use a known good block (LVDS deserializer from appnote xapp523) in the vivado block diagram for a 7 series #xilinx #zynq part (snickerdoodle black). I get the error even if I pin out directly to top level pins. I hate using the gui because it hides too much magic. Has anyone hit this madness before?
I'm trying to deserialize a 1.024 Mbps 8b10b lvds to get it on the linux side for storage on disk.
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#FPGA dorks. I'm running into an issue where #vivado says: multiple drivers on MMCM pins when I use a known good block (LVDS deserializer from appnote xapp523) in the vivado block diagram for a 7 series #xilinx #zynq part (snickerdoodle black). I get the error even if I pin out directly to top level pins. I hate using the gui because it hides too much magic. Has anyone hit this madness before?
I'm trying to deserialize a 1.024 Mbps 8b10b lvds to get it on the linux side for storage on disk.
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#FPGA dorks. I'm running into an issue where #vivado says: multiple drivers on MMCM pins when I use a known good block (LVDS deserializer from appnote xapp523) in the vivado block diagram for a 7 series #xilinx #zynq part (snickerdoodle black). I get the error even if I pin out directly to top level pins. I hate using the gui because it hides too much magic. Has anyone hit this madness before?
I'm trying to deserialize a 1.024 Mbps 8b10b lvds to get it on the linux side for storage on disk.
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#FPGA dorks. I'm running into an issue where #vivado says: multiple drivers on MMCM pins when I use a known good block (LVDS deserializer from appnote xapp523) in the vivado block diagram for a 7 series #xilinx #zynq part (snickerdoodle black). I get the error even if I pin out directly to top level pins. I hate using the gui because it hides too much magic. Has anyone hit this madness before?
I'm trying to deserialize a 1.024 Mbps 8b10b lvds to get it on the linux side for storage on disk.
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Затолкаем братцы!!! UART Lite через PCIe прямиком в Linux: драйвер за вечер (почти)
Что если можно было бы подключить своё AXI-устройство на FPGA к Linux через PCIe за вечер? В этой статье рассказываю, как написать драйвер для UARTLite через XDMA, собрать свою TTY и начать работать с GPS прямо из терминала! Залетай, что смотришь....
https://habr.com/ru/articles/900644/
#fpga #linux #linux_kernel #uart #pcie #tty #axi #vivado #embedded #driver
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Затолкаем братцы!!! UART Lite через PCIe прямиком в Linux: драйвер за вечер (почти)
Что если можно было бы подключить своё AXI-устройство на FPGA к Linux через PCIe за вечер? В этой статье рассказываю, как написать драйвер для UARTLite через XDMA, собрать свою TTY и начать работать с GPS прямо из терминала! Залетай, что смотришь....
https://habr.com/ru/articles/900644/
#fpga #linux #linux_kernel #uart #pcie #tty #axi #vivado #embedded #driver
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Затолкаем братцы!!! UART Lite через PCIe прямиком в Linux: драйвер за вечер (почти)
Что если можно было бы подключить своё AXI-устройство на FPGA к Linux через PCIe за вечер? В этой статье рассказываю, как написать драйвер для UARTLite через XDMA, собрать свою TTY и начать работать с GPS прямо из терминала! Залетай, что смотришь....
https://habr.com/ru/articles/900644/
#fpga #linux #linux_kernel #uart #pcie #tty #axi #vivado #embedded #driver
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Linux From Scratch на Zynq UltraScale+ MPSoC
В данной статье я постараюсь описать процесс создания кастомного образа Linux на Zynq UltraScale+ MPSoCс. Каждый необходимый компонент будет собран отдельно с использованием соответствующих утилит. Статья разбита на разделы, которые шаг за шагом знакомят вас с процессом сборки и запуска системы на данной платформе.
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Linux From Scratch на Zynq UltraScale+ MPSoC
В данной статье я постараюсь описать процесс создания кастомного образа Linux на Zynq UltraScale+ MPSoCс. Каждый необходимый компонент будет собран отдельно с использованием соответствующих утилит. Статья разбита на разделы, которые шаг за шагом знакомят вас с процессом сборки и запуска системы на данной платформе.
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@remi Yeah my whole group gave up on mathworks (and Microsoft). We do everything in python now with boost c++ for some bits (on linux). No more dealing with license servers is great. We stimulate on a cluster of machines now and never worry about running out of licenses. It's great. Now when we can get rid of #modelsim we will be ~100% #foss tool chain. #ghdl and or #cvc with #cocotb is close but not quite. Xilinx #vivado encrypted ip cores are a problem that can only be avoided by saying no...
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@remi Yeah my whole group gave up on mathworks (and Microsoft). We do everything in python now with boost c++ for some bits (on linux). No more dealing with license servers is great. We stimulate on a cluster of machines now and never worry about running out of licenses. It's great. Now when we can get rid of #modelsim we will be ~100% #foss tool chain. #ghdl and or #cvc with #cocotb is close but not quite. Xilinx #vivado encrypted ip cores are a problem that can only be avoided by saying no...
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@remi Yeah my whole group gave up on mathworks (and Microsoft). We do everything in python now with boost c++ for some bits (on linux). No more dealing with license servers is great. We stimulate on a cluster of machines now and never worry about running out of licenses. It's great. Now when we can get rid of #modelsim we will be ~100% #foss tool chain. #ghdl and or #cvc with #cocotb is close but not quite. Xilinx #vivado encrypted ip cores are a problem that can only be avoided by saying no...
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@remi Yeah my whole group gave up on mathworks (and Microsoft). We do everything in python now with boost c++ for some bits (on linux). No more dealing with license servers is great. We stimulate on a cluster of machines now and never worry about running out of licenses. It's great. Now when we can get rid of #modelsim we will be ~100% #foss tool chain. #ghdl and or #cvc with #cocotb is close but not quite. Xilinx #vivado encrypted ip cores are a problem that can only be avoided by saying no...