#zynq — Public Fediverse posts
Live and recent posts from across the Fediverse tagged #zynq, aggregated by home.social.
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The #SpaceWire ( #satellite oriented wired communication standard) #OpenSource #GNU/ #Linux software support (C library, CLI, Python) for Remote Memory Access Protocol ( #RMAP ) initiator and target realized by STAR-Dundee RMAP IP Cores integrated into custom variant of TEDIA PCD-8006 PCIe expansion card developed by Kyaw Htet Lin at #CVUT #CVUTFEL and his related thesis have been published.
The project page https://gitlab.fel.cvut.cz/otrees/spacewire/spw-pcie-tedia, Wiki, Thesis PDF, Presentation PDF and complete record with review reports https://dspace.cvut.cz/entities/publication/490357d1-8609-414e-91ad-87d4cc0e9b7e.
Longer term plan is to continue with support of more SpW IP cores, #RTEMS and #Zynq and #BeagleV/ #BeagleVFire with potential to be used even for space qualified #PolarFire #SoC.
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#FPGA dorks. I'm running into an issue where #vivado says: multiple drivers on MMCM pins when I use a known good block (LVDS deserializer from appnote xapp523) in the vivado block diagram for a 7 series #xilinx #zynq part (snickerdoodle black). I get the error even if I pin out directly to top level pins. I hate using the gui because it hides too much magic. Has anyone hit this madness before?
I'm trying to deserialize a 1.024 Mbps 8b10b lvds to get it on the linux side for storage on disk.