#xilinx — Public Fediverse posts

Запуск Vivado 2019.1 на Orange Pi 3 LTS через QEMU

Если вам интересно как выглядит работа Vivado на одноядерном ARM процессоре с частотой 1.8 ГГц, и 2 Гб ОЗУ, то я вам это покажу, и расскажу, как я запустил и успешно прошил плату (ДА! Собрал проект и прошил).

https://habr.com/ru/articles/1033766/

#Vivado #Xilinx #FPGA #OrangePi #Orange_Pi_3 #QEMU

Запуск Vivado 2019.1 на Orange Pi 3 LTS через QEMU

Если вам интересно как выглядит работа Vivado на одноядерном ARM процессоре с частотой 1.8 ГГц, и 2 Гб ОЗУ, то я вам это покажу, и расскажу, как я запустил и успешно прошил плату (ДА! Собрал проект и прошил).

https://habr.com/ru/articles/1033766/

#Vivado #Xilinx #FPGA #OrangePi #Orange_Pi_3 #QEMU

Запуск Vivado 2019.1 на Orange Pi 3 LTS через QEMU

Если вам интересно как выглядит работа Vivado на одноядерном ARM процессоре с частотой 1.8 ГГц, и 2 Гб ОЗУ, то я вам это покажу, и расскажу, как я запустил и успешно прошил плату (ДА! Собрал проект и прошил).

https://habr.com/ru/articles/1033766/

#Vivado #Xilinx #FPGA #OrangePi #Orange_Pi_3 #QEMU

Запуск Vivado 2019.1 на Orange Pi 3 LTS через QEMU

Если вам интересно как выглядит работа Vivado на одноядерном ARM процессоре с частотой 1.8 ГГц, и 2 Гб ОЗУ, то я вам это покажу, и расскажу, как я запустил и успешно прошил плату (ДА! Собрал проект и прошил).

https://habr.com/ru/articles/1033766/

#Vivado #Xilinx #FPGA #OrangePi #Orange_Pi_3 #QEMU

Как мы прототипировали контроллер PCI Express от стороннего производителя

Привет! Я Константин Павлов, старший инженер по разработке СнК в компании

https://habr.com/ru/companies/yadro/articles/1011186/

#pcie #xilinx #phy #плис #прототипирование

Start rtl counter with a timer that is initialized 10 seconds from a 32bit wrap point so that the software handling of wrap-around is well exercised during development.

#rtl #fpga #verilog #vhdl #xilinx #alchitry #eureka #protonpack #software #softwaredevelopment #hardware #embedded #fensterFreitag

Start rtl counter with a timer that is initialized 10 seconds from a 32bit wrap point so that the software handling of wrap-around is well exercised during development.

#rtl #fpga #verilog #vhdl #xilinx #alchitry #eureka #protonpack #software #softwaredevelopment #hardware #embedded #fensterFreitag

Start rtl counter with a timer that is initialized 10 seconds from a 32bit wrap point so that the software handling of wrap-around is well exercised during development.

#rtl #fpga #verilog #vhdl #xilinx #alchitry #eureka #protonpack #software #softwaredevelopment #hardware #embedded #fensterFreitag

«Если ты не страдал — ты не считаешься ПЛИСоводом»: подкаст «Битовые маски» с Михаилом Коробковым

В подкасте «Битовые Маски» ведущие Лена Лепилкина и Антон Афанасьев обсуждают с экспертами системное программирование и разработку «железа». В 25-м выпуске гостем стал Михаил Коробков — создатель сообщества FPGA-Systems и одноименного журнала, ПЛИСовод-энтузиаст и по совместительству старший инженер по разработке СнК Погружаемся в ПЛИСоводство →

https://habr.com/ru/companies/yadro/articles/992190/

#fpgasystems #fpga #asic #xilinx #altera #плис #lattice #embedded_fpga #highlevel_synthesis #efpga

@root42

This was in the 2015-2020 timeframe.

Since then we've installed several racks with linux servers. Hired an engineer reporting to our department to manage everything. And another to manage test automation.

And finally this past month we decommissioned the last windows machine our department was holding on to to run legacy #Xilinx #ISE builds. I ported those scripts to #linux.

All this because IT was not providing service and treated us as untrusted threats in their threat modelling.

PSA: This just landed on my work feed:

Zynq UltraScale+ Design Advisory

https://adaptivesupport.amd.com/s/article/72992?language=en_US

#FPGA #Xilinx #vhdl #verilog #pcie

Новое поколение ПЛИС это не только про повышение частоты…

Прослеживается тенденция, что сложность CLB повышается, сами примитивы становятся хитрее. От сюда вытекает вопрос, а на сколько эффективными становятся ячейки, и сколько ресурсов ПЛИС они экономят в сравнении с предыдущими поколениями?

https://habr.com/ru/articles/971560/

#ise #vivado #xilinx #fpga #ПЛИС

I plugged it in to USB... it powered on.
I went to plug in the second USB and as the metal made contact it suddenly powered off...

I saw no magic smoke.

It sure looks dead. I hope it's not a design flaw... because I just ordered two replacements.

#FPGA #Alchitry #Xilinx

https://forum.alchitry.com/t/regulator-failure-on-1v8-from-adp5052acpz-r7-on-pt-board/3546

Образовательные технологии опробованные в России — работают и в США

Провели мероприятие в Калифорнийском политехническом государственном университете в Сан-Луис-Обиспо. Докладчиками были: ваш покорный слуга Юрий Панчул, два американских инженера проектирующие чип по ускорению ИИ, и китайский студент из Университета Калифорнии в Санта-Барбаре. Идея мероприятия возникла, когда я встретился с выпускником Cal Poly Стенли на конференции самоделкиных OpenSause, и он поведал мне то, что я уже знал из собеседований американских студентов: они изучают в вузе карты Карно, доходят до конечного автомата светофора, отдельно постигают классический 5-стадийный конвейер MIPS (ныне RISC-V), а потом идут на собеседование на работу, и - хоба! - выясняется что их карты Карно никого в индустрии не интересуют, а вопросы идут про сопряжение конвейера обработки данных (не процессорного!) и FIFO, чего они не проходили. Привожу ниже мой отчет на английском.

https://habr.com/ru/articles/961364/

#SystemVerilog #Gowin #Xilinx #Altera #ASIC #FPGA #TinyTapeout #Cal_Poly #Verilog #vlsi

A watched vivado build doesn't close timing.

#fpga #xilinx #kria

Dear @PaulaMaddox, I hope you are well! I think I'm going to punt on my lvds deserializer approach. I fear I am having what look like signal integrity issues, but could also be design/fpga timing issues. Achieving lvds deserialization is not necessary, and I don't want to spend any more time fighting it.

I see Alchitry has a new Pt board with transceivers. It also has a 400Mbit USB part on an Ft+ board.

Hmm... will I face vendor lock-in? Do you have any advice?

#Xilinx #FPGA #verilog #vhdl

@philpem No, but that sounds wild. Device trees are taking over everything.

I learned last month that #Xilinx is replacing their proprietary SoC toolchain (XSCT, implemented in #tcl) and file formats (MSS, MLD, etc) with Python and device tree files.

No only if we can bring back Open Firmware and get #forth in bootloaders again...

Summer 2025 #cvut defended theses by OTREES/my students:

• Matyáš Bobek, FlexCAN Controller Emulation for QEMU, #qemu #canbus (git), I hope for mainlining soon, my thanks to
  @marckleinebudde for review
• Albert Bezděk, Stereo Camera FPGA Interface and Processing for Zynq Based Systems, with initial rectification and disparity in #XilinX #Zynq #FPGA (git), thank to Martin Meloun for review
• Michal Matiáš, NuttX RTOS Driver for Single Unshielded Twisted Pair Communication, working with ncv7410 and ESP32-C6 for now (nuttx, apps git), continues by #GSoC expected to lead to broader OpenAlliance SPI Ethernet MAC-PHY T1S for mainline #NuttX support after summer, thanks to @cynerd for review

See the last OTREES theses list for link to repositories and more

Another related theses from #cvut Faculty of Information Technologies mentored by Michal Štepanovský to mention:

• Jan Medek, Implementation of RISC-V soft-core processor on FPGA board with real-time operating system support, port (git) of #NuttX to the own setup of Ibex #riscv to Digilent Basys 3 and Digilent Nexys Video, includes even #NuttX, #RTEMS, #Zephyr, #FreeRTOS and RT-Thread choice analysis, some minor clarifications in my review, out of the text documentation, the student ported NuttX even to the CPU system prepared in frame of the next thesis
• Ondřej Golasowski, RISC-V open-source microarchitecture analysis and optimization, the VESP-BETA single-cycle RV32IMZicsr #riscv design for basic #comparch education with #FPGA labs

Stay tuned next summer as well, there is student interesting in thesis to add MMU to #QtRvSim

Summer 2025 #cvut defended theses by OTREES / “my” students:

• Matyáš Bobek, FlexCAN Controller Emulation for QEMU, #qemu #canbus (git), I hope for mainlining soon, my thanks to
  @marckleinebudde for review
• Albert Bezděk, Stereo Camera FPGA Interface and Processing for Zynq Based Systems, with initial rectification and disparity in #XilinX #Zynq #FPGA (git), thank to Martin Meloun for review
• Michal Matiáš, NuttX RTOS Driver for Single Unshielded Twisted Pair Communication, working with ncv7410 and ESP32-C6 for now (nuttx, apps git), continues by #GSoC expected to lead to broader OpenAlliance SPI Ethernet MAC-PHY T1S for mainline #NuttX support after summer, thanks to @cynerd for review

See the last OTREES theses list for link to repositories and more

Another related theses from #cvut Faculty of Information Technologies mentored by Michal Štepanovský to mention:

• Jan Medek, Implementation of RISC-V soft-core processor on FPGA board with real-time operating system support, port (git) of #NuttX to the own setup of Ibex #riscv to Digilent Basys 3 and Digilent Nexys Video, includes even #NuttX, #RTEMS, #Zephyr, #FreeRTOS and RT-Thread choice analysis, some minor clarifications in my review, out of the text documentation, the student ported NuttX even to the CPU system prepared in frame of the next thesis
• Ondřej Golasowski, RISC-V open-source microarchitecture analysis and optimization, the VESP-BETA single-cycle RV32IMZicsr #riscv design for basic #comparch education with #FPGA labs

Stay tuned next summer as well, there is student interested in thesis to add MMU to #QtRvSim

Summer 2025 #cvut defended theses by OTREES / “my” students:

• Matyáš Bobek, FlexCAN Controller Emulation for QEMU, #qemu #canbus (git), I hope for mainlining soon, my thanks to
  @marckleinebudde for review
• Albert Bezděk, Stereo Camera FPGA Interface and Processing for Zynq Based Systems, with initial rectification and disparity in #XilinX #Zynq #FPGA (git), thank to Martin Meloun for review
• Michal Matiáš, NuttX RTOS Driver for Single Unshielded Twisted Pair Communication, working with ncv7410 and ESP32-C6 for now (nuttx, apps git), continues by #GSoC expected to lead to broader OpenAlliance SPI Ethernet MAC-PHY T1S for mainline #NuttX support after summer, thanks to @cynerd for review

See the last OTREES theses list for link to repositories and more

Another related theses from #cvut Faculty of Information Technologies mentored by Michal Štepanovský to mention:

• Jan Medek, Implementation of RISC-V soft-core processor on FPGA board with real-time operating system support, port (git) of #NuttX to the own setup of Ibex #riscv to Digilent Basys 3 and Digilent Nexys Video, includes even #NuttX, #RTEMS, #Zephyr, #FreeRTOS and RT-Thread choice analysis, some minor clarifications in my review, out of the text documentation, the student ported NuttX even to the CPU system prepared in frame of the next thesis
• Ondřej Golasowski, RISC-V open-source microarchitecture analysis and optimization, the VESP-BETA single-cycle RV32IMZicsr #riscv design for basic #comparch education with #FPGA labs

Stay tuned next summer as well, there is student interested in thesis to add MMU to #QtRvSim

Summer 2025 #cvut defended theses by OTREES / “my” students:

• Matyáš Bobek, FlexCAN Controller Emulation for QEMU, #qemu #canbus (git), I hope for mainlining soon, my thanks to
  @marckleinebudde for review
• Albert Bezděk, Stereo Camera FPGA Interface and Processing for Zynq Based Systems, with initial rectification and disparity in #XilinX #Zynq #FPGA (git), thank to Martin Meloun for review
• Michal Matiáš, NuttX RTOS Driver for Single Unshielded Twisted Pair Communication, working with ncv7410 and ESP32-C6 for now (nuttx, apps git), continues by #GSoC expected to lead to broader OpenAlliance SPI Ethernet MAC-PHY T1S for mainline #NuttX support after summer, thanks to @cynerd for review

See the last OTREES theses list for link to repositories and more

Another related theses from #cvut Faculty of Information Technologies mentored by Michal Štepanovský to mention:

• Jan Medek, Implementation of RISC-V soft-core processor on FPGA board with real-time operating system support, port (git) of #NuttX to the own setup of Ibex #riscv to Digilent Basys 3 and Digilent Nexys Video, includes even #NuttX, #RTEMS, #Zephyr, #FreeRTOS and RT-Thread choice analysis, some minor clarifications in my review, out of the text documentation, the student ported NuttX even to the CPU system prepared in frame of the next thesis
• Ondřej Golasowski, RISC-V open-source microarchitecture analysis and optimization, the VESP-BETA single-cycle RV32IMZicsr #riscv design for basic #comparch education with #FPGA labs

Stay tuned next summer as well, there is student interesting in thesis to add MMU to #QtRvSim

Summer 2025 #cvut defended theses by OTREES/my students:

• Matyáš Bobek, FlexCAN Controller Emulation for QEMU, #qemu #canbus (git), I hope for mainlining soon, my thanks to
  @marckleinebudde for review
• Albert Bezděk, Stereo Camera FPGA Interface and Processing for Zynq Based Systems, with initial rectification and disparity in #XilinX #Zynq #FPGA (git), thank to Martin Meloun for review
• Michal Matiáš, NuttX RTOS Driver for Single Unshielded Twisted Pair Communication, working with ncv7410 and ESP32-C6 for now (nuttx, apps git), continues by #GSoC expected to lead to broader OpenAlliance SPI Ethernet MAC-PHY T1S for mainline #NuttX support after summer, thanks to @cynerd for review

See the last OTREES theses list for link to repositories and more

Another related theses from #cvut Faculty of Information Technologies mentored by Michal Štepanovský to mention:

• Jan Medek, Implementation of RISC-V soft-core processor on FPGA board with real-time operating system support, port (git) of #NuttX to the own setup of Ibex #riscv to Digilent Basys 3 and Digilent Nexys Video, includes even #NuttX, #RTEMS, #Zephyr, #FreeRTOS and RT-Thread choice analysis, some minor clarifications in my review, out of the text documentation, the student ported NuttX even to the CPU system prepared in frame of the next thesis
• Ondřej Golasowski, RISC-V open-source microarchitecture analysis and optimization, the VESP-BETA single-cycle RV32IMZicsr #riscv design for basic #comparch education with #FPGA labs

Stay tuned next summer as well, there is student interesting in thesis to add MMU to #QtRvSim

Before (at 1.024 Gbps) it had slipped in one direction at 210 MHz and the other direction at 290 MHz. This indicated that there was a clock rate problem.

Once it was running at 200MHz the slipping was random. Random slipping indicated to me there was also a signal integrity problem and the clock rate problem was fixed.

I had soldered a termination resistor on that proto-board (0201... yikes!) because #Xilinx doesn't allow internal resistors on this bank.

On a hunch I added attenuators...

#FPGA dorks. I'm running into an issue where #vivado says: multiple drivers on MMCM pins when I use a known good block (LVDS deserializer from appnote xapp523) in the vivado block diagram for a 7 series #xilinx #zynq part (snickerdoodle black). I get the error even if I pin out directly to top level pins. I hate using the gui because it hides too much magic. Has anyone hit this madness before?

I'm trying to deserialize a 1.024 Mbps 8b10b lvds to get it on the linux side for storage on disk.

#FPGA dorks. I'm running into an issue where #vivado says: multiple drivers on MMCM pins when I use a known good block (LVDS deserializer from appnote xapp523) in the vivado block diagram for a 7 series #xilinx #zynq part (snickerdoodle black). I get the error even if I pin out directly to top level pins. I hate using the gui because it hides too much magic. Has anyone hit this madness before?

I'm trying to deserialize a 1.024 Mbps 8b10b lvds to get it on the linux side for storage on disk.

#FPGA dorks. I'm running into an issue where #vivado says: multiple drivers on MMCM pins when I use a known good block (LVDS deserializer from appnote xapp523) in the vivado block diagram for a 7 series #xilinx #zynq part (snickerdoodle black). I get the error even if I pin out directly to top level pins. I hate using the gui because it hides too much magic. Has anyone hit this madness before?

I'm trying to deserialize a 1.024 Mbps 8b10b lvds to get it on the linux side for storage on disk.

#FPGA dorks. I'm running into an issue where #vivado says: multiple drivers on MMCM pins when I use a known good block (LVDS deserializer from appnote xapp523) in the vivado block diagram for a 7 series #xilinx #zynq part (snickerdoodle black). I get the error even if I pin out directly to top level pins. I hate using the gui because it hides too much magic. Has anyone hit this madness before?

I'm trying to deserialize a 1.024 Mbps 8b10b lvds to get it on the linux side for storage on disk.

#FPGA dorks. I'm running into an issue where #vivado says: multiple drivers on MMCM pins when I use a known good block (LVDS deserializer from appnote xapp523) in the vivado block diagram for a 7 series #xilinx #zynq part (snickerdoodle black). I get the error even if I pin out directly to top level pins. I hate using the gui because it hides too much magic. Has anyone hit this madness before?

I'm trying to deserialize a 1.024 Mbps 8b10b lvds to get it on the linux side for storage on disk.

AMD NPU and Xilinx Versal AI Engines Signal Processing in Radio Astronomy (2024) [pdf]

https://git.astron.nl/RD/acap/-/raw/main/Presentation_FPL24_Vincent_Sprave.pdf

#HackerNews #AMD #NPU #Xilinx #Versal #AI #Radio #Astronomy #Signal #Processing #2024

PCIe Endpoint on Xilinx 7-Series FPGAs with PCIe_2_1 Hard Block and GTP

https://github.com/regymm/pcie_7x

#HackerNews #PCIe #FPGA #Xilinx #7Series #GTP #PCIeHardBlock

PCIe Endpoint on Xilinx 7-Series FPGAs with PCIe_2_1 Hard Block and GTP

https://github.com/regymm/pcie_7x

#HackerNews #PCIe #FPGA #Xilinx #7Series #GTP #PCIeHardBlock

PCIe Endpoint on Xilinx 7-Series FPGAs with PCIe_2_1 Hard Block and GTP

https://github.com/regymm/pcie_7x

#HackerNews #PCIe #FPGA #Xilinx #7Series #GTP #PCIeHardBlock

PCIe Endpoint on Xilinx 7-Series FPGAs with PCIe_2_1 Hard Block and GTP

https://github.com/regymm/pcie_7x

#HackerNews #PCIe #FPGA #Xilinx #7Series #GTP #PCIeHardBlock

Das EasyGate1541 jetzt auch für die 1541-II

Das EasyGate1541 war bisher nur für die “alte” 1541 erhältlich. Die spätere 1541-II bekam von Commodore ein anderes Gate-Array, das noch mehr Funktionalitäten integriert hat. Es war an der Zeit, dass eine Alternative geschaffen wurde.

#1541II #1571 #Array #commodore #CPLD #EasyGate1541 #EasyGate1541II #Ersatz #Festplatte #Gate #Laufwerk #Xilinx

https://dirkwouters.de/easygate1541-ii/

Neue Hauptplatine für das Commodore 1541-Diskettenlaufwerk, Teil II

Hier nun der versprochene 2. Teil über eine neue Systemplatine für das Floppy-Laufwerk VC1541 von Commodore. Ein komplettes Redesign und die Zusammenführung verschiedener Projekte zu einem neuen Controller…

#1541 #C128 #c64 #commodore #CPLD #Disk #DolphinDOS #Ersatz #Erweitert #Generation #GPIB #IEEE488 #Laufwerk #Mainboard #Neu #PCB #SpeedDOS #VC1541 #Weiter #Xilinx

https://dirkwouters.de/neue-hauptplatine-fuer-das-commodore-1541-diskettenlaufwerk-teil-ii/

Neue Hauptplatine für das Commodore 1541-Diskettenlaufwerk, Teil II

Hier nun der versprochene 2. Teil über eine neue Systemplatine für das Floppy-Laufwerk VC1541 von Commodore. Ein komplettes Redesign und die Zusammenführung verschiedener Projekte zu einem neuen Controller…

#1541 #C128 #c64 #commodore #CPLD #Disk #DolphinDOS #Ersatz #Erweitert #Generation #GPIB #IEEE488 #Laufwerk #Mainboard #Neu #PCB #SpeedDOS #VC1541 #Weiter #Xilinx

https://dirkwouters.de/neue-hauptplatine-fuer-das-commodore-1541-diskettenlaufwerk-teil-ii/

Neue Hauptplatine für das Commodore 1541-Diskettenlaufwerk, Teil II

Hier nun der versprochene 2. Teil über eine neue Systemplatine für das Floppy-Laufwerk VC1541 von Commodore. Ein komplettes Redesign und die Zusammenführung verschiedener Projekte zu einem neuen Controller…

#1541 #C128 #c64 #commodore #CPLD #Disk #DolphinDOS #Ersatz #Erweitert #Generation #GPIB #IEEE488 #Laufwerk #Mainboard #Neu #PCB #SpeedDOS #VC1541 #Weiter #Xilinx

https://dirkwouters.de/neue-hauptplatine-fuer-das-commodore-1541-diskettenlaufwerk-teil-ii/

Neue Hauptplatine für das Commodore 1541-Diskettenlaufwerk, Teil II

Hier nun der versprochene 2. Teil über eine neue Systemplatine für das Floppy-Laufwerk VC1541 von Commodore. Ein komplettes Redesign und die Zusammenführung verschiedener Projekte zu einem neuen Controller…

#1541 #C128 #c64 #commodore #CPLD #Disk #DolphinDOS #Ersatz #Erweitert #Generation #GPIB #IEEE488 #Laufwerk #Mainboard #Neu #PCB #SpeedDOS #VC1541 #Weiter #Xilinx

https://dirkwouters.de/neue-hauptplatine-fuer-das-commodore-1541-diskettenlaufwerk-teil-ii/

Neue Hauptplatine für das Commodore 1541-Diskettenlaufwerk, Teil II

Hier nun der versprochene 2. Teil über eine neue Systemplatine für das Floppy-Laufwerk VC1541 von Commodore. Ein komplettes Redesign und die Zusammenführung verschiedener Projekte zu einem neuen Controller…

#1541 #C128 #c64 #commodore #CPLD #Disk #DolphinDOS #Ersatz #Erweitert #Generation #GPIB #IEEE488 #Laufwerk #Mainboard #Neu #PCB #SpeedDOS #VC1541 #Weiter #Xilinx

https://dirkwouters.de/neue-hauptplatine-fuer-das-commodore-1541-diskettenlaufwerk-teil-ii/

TriMod 2.0 CBM Adapter – Die All-In-One Lösung

In der Commodore-Welt haben sich zwei Schnittstellen für Peripheriegeräte etabliert, der CBM-Bus bzw. IEC-Bus für den C64 und seine Verwandten und IEEE-488 für die “große” CBM-Welt. Warum nicht eine Floppy für beide Welten? Jetzt auch mit…

#1541 #2031 #4040 #Bus #c64 #Cable #commodore #CPLD #diy #DolphinDOS #GPIB #parallel #PET #Ribbon #SpeedDOS #Switchable #TriMod #VC1541 #Xilinx

https://dirkwouters.de/trimod-ii-adapter/

TriMod 2.0 CBM Adapter – Die All-In-One Lösung

In der Commodore-Welt haben sich zwei Schnittstellen für Peripheriegeräte etabliert, der CBM-Bus bzw. IEC-Bus für den C64 und seine Verwandten und IEEE-488 für die “große” CBM-Welt. Warum nicht eine Floppy für beide Welten? Jetzt auch mit…

#1541 #2031 #4040 #Bus #c64 #Cable #commodore #CPLD #diy #DolphinDOS #GPIB #parallel #PET #Ribbon #SpeedDOS #Switchable #TriMod #VC1541 #Xilinx

https://dirkwouters.de/trimod-ii-adapter/

EasyFlash³ – Flashen der verschiedenen Komponenten

Wurde ein neues Easyflash3-Modul bestückt, sind die einzelnen Komponenten wie der FTDI-Chip, der CPLD und auch der Flash noch leer und das Modul daher nicht einsatzbereit. Oder einer der ICs wurde nach einem Defekt ausgetauscht und muss nun ne…

#C128 #c64 #commodore #CPLD #CRT #Driver #EASP #EasyFlash #EasyFlash3 #EF3 #Flash #Flashing #FT232 #installation #SKOE #windows #Xilinx

https://dirkwouters.de/easyflash%c2%b3-flashen-der-verschiedenen-komponenten/

EasyFlash³ – Flashen der verschiedenen Komponenten

Wurde ein neues Easyflash3-Modul bestückt, sind die einzelnen Komponenten wie der FTDI-Chip, der CPLD und auch der Flash noch leer und das Modul daher nicht einsatzbereit. Oder einer der ICs wurde nach einem Defekt ausgetauscht und muss nun ne…

#C128 #c64 #commodore #CPLD #CRT #Driver #EASP #EasyFlash #EasyFlash3 #EF3 #Flash #Flashing #FT232 #installation #SKOE #windows #Xilinx

https://dirkwouters.de/easyflash%c2%b3-flashen-der-verschiedenen-komponenten/

EasyFlash³ – Probleme mit dem CPLD

Das EasyFlash³-Modul ist nach wie vor ein beliebtes Zubehör für den Commodore C64. Und mittlerweile kann man die einzelnen Komponenten für kleines Geld aus Asien beziehen. Allerdings gibt es hier und da die eine oder andere Stolperfalle. Heute möchte ich ein paar…

#AliExpress #C128 #c64 #commodore #CPLD #EASP #EasyFlash. #EasyFlash³ #EF3 #Fehler #Flashen #Probleme #SX64 #TDO #XC95144XL #Xilinx

https://dirkwouters.de/easyflash%c2%b3-probleme-mit-dem-cpld/

EasyFlash³ – Probleme mit dem CPLD

Das EasyFlash³-Modul ist nach wie vor ein beliebtes Zubehör für den Commodore C64. Und mittlerweile kann man die einzelnen Komponenten für kleines Geld aus Asien beziehen. Allerdings gibt es hier und da die eine oder andere Stolperfalle. Heute möchte ich ein paar…

#AliExpress #C128 #c64 #commodore #CPLD #EASP #EasyFlash. #EasyFlash³ #EF3 #Fehler #Flashen #Probleme #SX64 #TDO #XC95144XL #Xilinx

https://dirkwouters.de/easyflash%c2%b3-probleme-mit-dem-cpld/

Not having #AMD #Xilinx #Vivado #Chipscope based live #hardware debug for the #picoice #Lattice #ice40 #FPGA was a little annoying

so I am hoping to revive the small pipelinec project that was sorta a build your own chipscope attempt 🤙 and demo that on the pico ice

#AMD Moves Up Instinct #MI350/#MI355X To Now Release By Mid-2025, #MI400 Lineup Slated For 2026 As #Datacenter Biz Hits Records
Last year the datacenter business at AMD, which includes #EPYC #CPU, Instinct #GPU, #Pensando #DPU, and #Xilinx #FPGA accelerators, accounted for $12.58 billion in sales, or 48.8% of revenues. In both Q3 and Q4 of 2024, datacenter drove in excess of half of AMD’s revenues and nearly 60% of its operating income.
https://www.nextplatform.com/2025/02/04/amd-moves-up-instinct-355x-launch-as-datacenter-biz-hits-records/

#AMD Moves Up Instinct #MI350/#MI355X To Now Release By Mid-2025, #MI400 Lineup Slated For 2026 As #Datacenter Biz Hits Records
Last year the datacenter business at AMD, which includes #EPYC #CPU, Instinct #GPU, #Pensando #DPU, and #Xilinx #FPGA accelerators, accounted for $12.58 billion in sales, or 48.8% of revenues. In both Q3 and Q4 of 2024, datacenter drove in excess of half of AMD’s revenues and nearly 60% of its operating income.
https://www.nextplatform.com/2025/02/04/amd-moves-up-instinct-355x-launch-as-datacenter-biz-hits-records/

#AMD Moves Up Instinct #MI350/#MI355X To Now Release By Mid-2025, #MI400 Lineup Slated For 2026 As #Datacenter Biz Hits Records
Last year the datacenter business at AMD, which includes #EPYC #CPU, Instinct #GPU, #Pensando #DPU, and #Xilinx #FPGA accelerators, accounted for $12.58 billion in sales, or 48.8% of revenues. In both Q3 and Q4 of 2024, datacenter drove in excess of half of AMD’s revenues and nearly 60% of its operating income.
https://www.nextplatform.com/2025/02/04/amd-moves-up-instinct-355x-launch-as-datacenter-biz-hits-records/

#AMD Moves Up Instinct #MI350/#MI355X To Now Release By Mid-2025, #MI400 Lineup Slated For 2026 As #Datacenter Biz Hits Records
Last year the datacenter business at AMD, which includes #EPYC #CPU, Instinct #GPU, #Pensando #DPU, and #Xilinx #FPGA accelerators, accounted for $12.58 billion in sales, or 48.8% of revenues. In both Q3 and Q4 of 2024, datacenter drove in excess of half of AMD’s revenues and nearly 60% of its operating income.
https://www.nextplatform.com/2025/02/04/amd-moves-up-instinct-355x-launch-as-datacenter-biz-hits-records/