#comparch — Public Fediverse posts

If you have interest in basic or more advanced computer architectures learning and teaching then I plan to visit #RISCV #FOSDEM devroom this Satturday. We can discuss even use of our #QtRvSim in the teaching. We are working on Sv32 and latter even Sv39 addition to extend this tool even for teaching operating system basic concepts. Tenative goal is to run MIT-PDOS one day. We have new #QtRvSim manual at our #CompArch site as well and revamped online training site (thanks to Jakub Pelc https://swpelc.eu/).

#CVUTFEL ( #CVUT FEE) Advanced Computer Architecture ( #comparch) course recodings of the first five lectures are published at #VHSky.cz. Czech language recordings from the 2021 round are available as well. The B4M35PAP course builds on the knowledge from the introductory #comparch B35APO course (recordings). Each student builds their own CPU design (tools and ISA are open). The #QtRvSim #RISCV educational simulator is provided for inspiration (online version and The Czech Technical University #comparch related courses guidepost https://comparch.edu.cvut.cz/).

P.S.: Help with tooling for transcribing the lectures in my Czenglish dialect into English subtitles would be appreciated, as well as all other forms of feedback. For the introductory course, we provide reusable LaTeX sources (CC-BY-SA license) that are open to pull requests.

#CVUTFEL ( #CVUT FEE) Advanced Computer Architecture ( #comparch) course recodings of the first five lectures are published at #VHSky.cz. Czech language recordings from the 2021 round are available as well. The B4M35PAP course builds on the knowledge from the introductory #comparch B35APO course (recordings). Each student builds their own CPU design (tools and ISA are open). The #QtRvSim #RISCV educational simulator is provided for inspiration (online version and The Czech Technical University #comparch related courses guidepost https://comparch.edu.cvut.cz/).

P.S.: Help with tooling for transcribing the lectures in my Czenglish dialect into English subtitles would be appreciated, as well as all other forms of feedback. For the introductory course, we provide reusable LaTeX sources (CC-BY-SA license) that are open to pull requests.

#CVUTFEL ( #CVUT FEE) Advanced Computer Architecture ( #comparch) course recodings of the first five lectures are published at #VHSky.cz. Czech language recordings from the 2021 round are available as well. The B4M35PAP course builds on the knowledge from the introductory #comparch B35APO course (recordings). Each student builds their own CPU design (tools and ISA are open). The #QtRvSim #RISCV educational simulator is provided for inspiration (online version and The Czech Technical University #comparch related courses guidepost https://comparch.edu.cvut.cz/).

P.S.: Help with tooling for transcribing the lectures in my Czenglish dialect into English subtitles would be appreciated, as well as all other forms of feedback. For the introductory course, we provide reusable LaTeX sources (CC-BY-SA license) that are open to pull requests.

#CVUTFEL ( #CVUT FEE) Advanced Computer Architecture ( #comparch) course recodings of the first five lectures are published at #VHSky.cz. Czech language recordings from the 2021 round are available as well. The B4M35PAP course builds on the knowledge from the introductory #comparch B35APO course (recordings). Each student builds their own CPU design (tools and ISA are open). The #QtRvSim #RISCV educational simulator is provided for inspiration (online version and The Czech Technical University #comparch related courses guidepost https://comparch.edu.cvut.cz/).

P.S.: Help with tooling for transcribing the lectures in my Czenglish dialect into English subtitles would be appreciated, as well as all other forms of feedback. For the introductory course, we provide reusable LaTeX sources (CC-BY-SA license) that are open to pull requests.

#CVUTFEL ( #CVUT FEE) Advanced Computer Architecture ( #comparch) course recodings of the first five lectures are published at #VHSky.cz. Czech language recordings from the 2021 round are available as well. The B4M35PAP course builds on the knowledge from the introductory #comparch B35APO course (recordings). Each student builds their own CPU design (tools and ISA are open). The #QtRvSim #RISCV educational simulator is provided for inspiration (online version and The Czech Technical University #comparch related courses guidepost https://comparch.edu.cvut.cz/).

P.S.: Help with tooling for transcribing the lectures in my Czenglish dialect into English subtitles would be appreciated, as well as all other forms of feedback. For the introductory course, we provide reusable LaTeX sources (CC-BY-SA license) that are open to pull requests.

Summer 2025 #cvut defended theses by OTREES/my students:

• Matyáš Bobek, FlexCAN Controller Emulation for QEMU, #qemu #canbus (git), I hope for mainlining soon, my thanks to
  @marckleinebudde for review
• Albert Bezděk, Stereo Camera FPGA Interface and Processing for Zynq Based Systems, with initial rectification and disparity in #XilinX #Zynq #FPGA (git), thank to Martin Meloun for review
• Michal Matiáš, NuttX RTOS Driver for Single Unshielded Twisted Pair Communication, working with ncv7410 and ESP32-C6 for now (nuttx, apps git), continues by #GSoC expected to lead to broader OpenAlliance SPI Ethernet MAC-PHY T1S for mainline #NuttX support after summer, thanks to @cynerd for review

See the last OTREES theses list for link to repositories and more

Another related theses from #cvut Faculty of Information Technologies mentored by Michal Štepanovský to mention:

• Jan Medek, Implementation of RISC-V soft-core processor on FPGA board with real-time operating system support, port (git) of #NuttX to the own setup of Ibex #riscv to Digilent Basys 3 and Digilent Nexys Video, includes even #NuttX, #RTEMS, #Zephyr, #FreeRTOS and RT-Thread choice analysis, some minor clarifications in my review, out of the text documentation, the student ported NuttX even to the CPU system prepared in frame of the next thesis
• Ondřej Golasowski, RISC-V open-source microarchitecture analysis and optimization, the VESP-BETA single-cycle RV32IMZicsr #riscv design for basic #comparch education with #FPGA labs

Stay tuned next summer as well, there is student interesting in thesis to add MMU to #QtRvSim

Summer 2025 #cvut defended theses by OTREES / “my” students:

• Matyáš Bobek, FlexCAN Controller Emulation for QEMU, #qemu #canbus (git), I hope for mainlining soon, my thanks to
  @marckleinebudde for review
• Albert Bezděk, Stereo Camera FPGA Interface and Processing for Zynq Based Systems, with initial rectification and disparity in #XilinX #Zynq #FPGA (git), thank to Martin Meloun for review
• Michal Matiáš, NuttX RTOS Driver for Single Unshielded Twisted Pair Communication, working with ncv7410 and ESP32-C6 for now (nuttx, apps git), continues by #GSoC expected to lead to broader OpenAlliance SPI Ethernet MAC-PHY T1S for mainline #NuttX support after summer, thanks to @cynerd for review

See the last OTREES theses list for link to repositories and more

Another related theses from #cvut Faculty of Information Technologies mentored by Michal Štepanovský to mention:

• Jan Medek, Implementation of RISC-V soft-core processor on FPGA board with real-time operating system support, port (git) of #NuttX to the own setup of Ibex #riscv to Digilent Basys 3 and Digilent Nexys Video, includes even #NuttX, #RTEMS, #Zephyr, #FreeRTOS and RT-Thread choice analysis, some minor clarifications in my review, out of the text documentation, the student ported NuttX even to the CPU system prepared in frame of the next thesis
• Ondřej Golasowski, RISC-V open-source microarchitecture analysis and optimization, the VESP-BETA single-cycle RV32IMZicsr #riscv design for basic #comparch education with #FPGA labs

Stay tuned next summer as well, there is student interested in thesis to add MMU to #QtRvSim

Summer 2025 #cvut defended theses by OTREES / “my” students:

• Matyáš Bobek, FlexCAN Controller Emulation for QEMU, #qemu #canbus (git), I hope for mainlining soon, my thanks to
  @marckleinebudde for review
• Albert Bezděk, Stereo Camera FPGA Interface and Processing for Zynq Based Systems, with initial rectification and disparity in #XilinX #Zynq #FPGA (git), thank to Martin Meloun for review
• Michal Matiáš, NuttX RTOS Driver for Single Unshielded Twisted Pair Communication, working with ncv7410 and ESP32-C6 for now (nuttx, apps git), continues by #GSoC expected to lead to broader OpenAlliance SPI Ethernet MAC-PHY T1S for mainline #NuttX support after summer, thanks to @cynerd for review

See the last OTREES theses list for link to repositories and more

Another related theses from #cvut Faculty of Information Technologies mentored by Michal Štepanovský to mention:

• Jan Medek, Implementation of RISC-V soft-core processor on FPGA board with real-time operating system support, port (git) of #NuttX to the own setup of Ibex #riscv to Digilent Basys 3 and Digilent Nexys Video, includes even #NuttX, #RTEMS, #Zephyr, #FreeRTOS and RT-Thread choice analysis, some minor clarifications in my review, out of the text documentation, the student ported NuttX even to the CPU system prepared in frame of the next thesis
• Ondřej Golasowski, RISC-V open-source microarchitecture analysis and optimization, the VESP-BETA single-cycle RV32IMZicsr #riscv design for basic #comparch education with #FPGA labs

Stay tuned next summer as well, there is student interested in thesis to add MMU to #QtRvSim

Summer 2025 #cvut defended theses by OTREES / “my” students:

• Matyáš Bobek, FlexCAN Controller Emulation for QEMU, #qemu #canbus (git), I hope for mainlining soon, my thanks to
  @marckleinebudde for review
• Albert Bezděk, Stereo Camera FPGA Interface and Processing for Zynq Based Systems, with initial rectification and disparity in #XilinX #Zynq #FPGA (git), thank to Martin Meloun for review
• Michal Matiáš, NuttX RTOS Driver for Single Unshielded Twisted Pair Communication, working with ncv7410 and ESP32-C6 for now (nuttx, apps git), continues by #GSoC expected to lead to broader OpenAlliance SPI Ethernet MAC-PHY T1S for mainline #NuttX support after summer, thanks to @cynerd for review

See the last OTREES theses list for link to repositories and more

Another related theses from #cvut Faculty of Information Technologies mentored by Michal Štepanovský to mention:

• Jan Medek, Implementation of RISC-V soft-core processor on FPGA board with real-time operating system support, port (git) of #NuttX to the own setup of Ibex #riscv to Digilent Basys 3 and Digilent Nexys Video, includes even #NuttX, #RTEMS, #Zephyr, #FreeRTOS and RT-Thread choice analysis, some minor clarifications in my review, out of the text documentation, the student ported NuttX even to the CPU system prepared in frame of the next thesis
• Ondřej Golasowski, RISC-V open-source microarchitecture analysis and optimization, the VESP-BETA single-cycle RV32IMZicsr #riscv design for basic #comparch education with #FPGA labs

Stay tuned next summer as well, there is student interesting in thesis to add MMU to #QtRvSim

Summer 2025 #cvut defended theses by OTREES/my students:

• Matyáš Bobek, FlexCAN Controller Emulation for QEMU, #qemu #canbus (git), I hope for mainlining soon, my thanks to
  @marckleinebudde for review
• Albert Bezděk, Stereo Camera FPGA Interface and Processing for Zynq Based Systems, with initial rectification and disparity in #XilinX #Zynq #FPGA (git), thank to Martin Meloun for review
• Michal Matiáš, NuttX RTOS Driver for Single Unshielded Twisted Pair Communication, working with ncv7410 and ESP32-C6 for now (nuttx, apps git), continues by #GSoC expected to lead to broader OpenAlliance SPI Ethernet MAC-PHY T1S for mainline #NuttX support after summer, thanks to @cynerd for review

See the last OTREES theses list for link to repositories and more

Another related theses from #cvut Faculty of Information Technologies mentored by Michal Štepanovský to mention:

• Jan Medek, Implementation of RISC-V soft-core processor on FPGA board with real-time operating system support, port (git) of #NuttX to the own setup of Ibex #riscv to Digilent Basys 3 and Digilent Nexys Video, includes even #NuttX, #RTEMS, #Zephyr, #FreeRTOS and RT-Thread choice analysis, some minor clarifications in my review, out of the text documentation, the student ported NuttX even to the CPU system prepared in frame of the next thesis
• Ondřej Golasowski, RISC-V open-source microarchitecture analysis and optimization, the VESP-BETA single-cycle RV32IMZicsr #riscv design for basic #comparch education with #FPGA labs

Stay tuned next summer as well, there is student interesting in thesis to add MMU to #QtRvSim

The new book how to build #riscv processor for #comparch courses is on the horizon (ETA later H2 2025) RISC-V System-on-Chip Design by D. Harris, J. Stine, R. Thompson, S. Harris. It has been presented at the RISC-V International Academic and Training SIG meeting. The recording of the session is available on YouTube https://youtu.be/Qyq5nHUDt4g The related configurable RV32I to RV64IMAFDCB core and Wally SoC sources https://github.com/openhwgroup/cvw

If you want to learn #RiscV basic principles yourself or use it in your computer architectures #comparch basic classes, then you can use our really open and fully shared resources, no registration required for experimenting online https://comparch.edu.cvut.cz/, downloading #QtRvSim packages for all major desktop operating systems #linux, #macos, #mswidows and obtaining lectures with the sources https://cw.fel.cvut.cz/wiki/courses/b35apo/en/lectures/start and recordings on YouTube and even advertisement-free community PeerTube instance VHSky.cz. We offer even online training and and competition site https://comparch.edu.cvut.cz/online-tools/webeval/. In this case, we store SHA1 of your e-mail only for purpose to allow participants to reset their password. So again we do not intend and even cannot use your registration for advertisement for paid courses etc.

example: ordering of memory writes.
on a strongly ordered system, writes are reordered to program order before commiting (actually writing to D$). On a weakly ordered memory system, writes to different locations can happen in different order #uarch #comparch #microarchitecture

This morning I read a post on a very active commercial archaeology Facebook group, asking whether a young person with an interest in maths and archaeology could combine the two.

15 replies in and all the answers are basically "no, there's no maths in archaeology"!

How is it our 70-year-old subfield is still so invisible? #comparch

Call for panels* for #ArcheoFOSS 2023: https://www.archeofoss.org/2023/call-for-panels

ArcheoFOSS is a really nice community that IMO is doing all the right things in terms of conference accessibility and openness, i.e. unlike certain other computational archaeology conferences, it's free and fully hybrid.

* This year they're experimenting with doing only roundtable-style discussion panels, so check it out if you have something #digitalarch, #comparch, etc. you want to talk about!

seven open source RISC-V implementations compared

https://bitlog.it/20220118_asic_roundup_of_open_source_riscv_cpu_cores.html

#riscv #comparch

via El Correo Libre (issue 47)