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1000 results for “pipelinec”

1. 

   PipelineC @pipelinec · 2026-05-15 · 14:22 UTC

   The StreamSoC demo is a fun music visualizer and video feedback experiment.
   But also is a reference for how easy PipelineC makes it to design your own SoC.
   Happy to help anyone give their own project a try!

   https://github.com/JulianKemmerer/PipelineC/wiki/Example:-StreamSoC

2. 

   PipelineC @pipelinec · 2026-05-15 · 14:21 UTC

   A SoC in C? StreamSoC shows how to move from embedded C software to custom PipelineC hardware for doing things like realtime streaming data processing.

   https://youtu.be/dzF3okigyog

3. 

   PipelineC @pipelinec · 2026-03-28 · 02:05 UTC

   Fun in the frequency domain 🤓 Camera pointed at it's own display also showing audio FFT for cool glitchy visualizer effect. Video processing all done in PipelineC hardware. And how?

   https://github.com/JulianKemmerer/PipelineC/wiki/Example:-Video-Pipelines

   #hardware #fpga #dsp #rtl #hdl #hls #verilog #vhdl #pipelinec

   #hardware #fpga #dsp #rtl #hdl #hls
4. 

   PipelineC @[email protected] · 2026-03-28 · 02:05 UTC

   Fun in the frequency domain 🤓 Camera pointed at it's own display also showing audio FFT for cool glitchy visualizer effect. Video processing all done in PipelineC hardware. And how?

   https://github.com/JulianKemmerer/PipelineC/wiki/Example:-Video-Pipelines

   #hardware #fpga #dsp #rtl #hdl #hls #verilog #vhdl #pipelinec

   #hardware #fpga #dsp #rtl #hdl #hls
5. 

   PipelineC @[email protected] · 2026-03-28 · 02:05 UTC

   Fun in the frequency domain 🤓 Camera pointed at it's own display also showing audio FFT for cool glitchy visualizer effect. Video processing all done in PipelineC hardware. And how?

   https://github.com/JulianKemmerer/PipelineC/wiki/Example:-Video-Pipelines

   #hardware #fpga #dsp #rtl #hdl #hls #verilog #vhdl #pipelinec

   #pipelinec #vhdl #verilog #hls #hdl #rtl
6. 

   PipelineC @[email protected] · 2026-03-28 · 02:05 UTC

   Fun in the frequency domain 🤓 Camera pointed at it's own display also showing audio FFT for cool glitchy visualizer effect. Video processing all done in PipelineC hardware. And how?

   https://github.com/JulianKemmerer/PipelineC/wiki/Example:-Video-Pipelines

   #hardware #fpga #dsp #rtl #hdl #hls #verilog #vhdl #pipelinec

   #hardware #fpga #dsp #rtl #hdl #hls
7. 

   PipelineC @[email protected] · 2026-03-28 · 02:04 UTC

   Fun in the frequency domain 🤓 Camera pointed at it's own display also showing audio FFT for cool glitchy visualizer effect. Video processing all done in PipelineC hardware. And how? github.com/JulianKemmer... #hardware #fpga #dsp #rtl #hdl #hls #verilog #vhdl #pipelinec

   #hardware #fpga #dsp #rtl #hdl #hls
8. 

   PipelineC @[email protected] · 2026-03-13 · 19:20 UTC

   @nlnetlabs.bsky.social NLnet Foundation funded open source WireGuard router in FPGA. Featuring PipelineC for cryptography blocks 🤓 github.com/JulianKemmer... #hardware #fpga #rtl #hdl #hls #verilog #vhdl #cryptography #wireguard #pipelinec

   #hardware #fpga #rtl #hdl #hls #verilog
9. 

   PipelineC @[email protected] · 2026-03-13 · 19:20 UTC

   @nlnetlabs.bsky.social NLnet Foundation funded open source WireGuard router in FPGA. Featuring PipelineC for cryptography blocks 🤓 github.com/JulianKemmer... #hardware #fpga #rtl #hdl #hls #verilog #vhdl #cryptography #wireguard #pipelinec

   #hardware #fpga #rtl #hdl #hls #verilog
10. 

    PipelineC @[email protected] · 2026-03-13 · 19:20 UTC

    @nlnetlabs.bsky.social NLnet Foundation funded open source WireGuard router in FPGA. Featuring PipelineC for cryptography blocks 🤓 github.com/JulianKemmer... #hardware #fpga #rtl #hdl #hls #verilog #vhdl #cryptography #wireguard #pipelinec

    #hardware #fpga #rtl #hdl #hls #verilog
11. 

    PipelineC @[email protected] · 2026-03-13 · 19:20 UTC

    @nlnetlabs.bsky.social NLnet Foundation funded open source WireGuard router in FPGA. Featuring PipelineC for cryptography blocks 🤓 github.com/JulianKemmer... #hardware #fpga #rtl #hdl #hls #verilog #vhdl #cryptography #wireguard #pipelinec

    #hardware #fpga #rtl #hdl #hls #verilog
12. 

    PipelineC @[email protected] · 2026-03-13 · 19:20 UTC

    @nlnet NLnet Foundation funded open source WireGuard router in FPGA. Featuring PipelineC for cryptography blocks 🤓

    https://github.com/JulianKemmerer/PipelineC/wiki/Example:-ChaCha20%E2%80%90Poly1305-for-WireGuard

    #hardware #fpga #rtl #hdl #hls #verilog #vhdl #cryptography #wireguard #pipelinec

    #hardware #fpga #rtl #hdl #hls #verilog
13. 

    PipelineC @pipelinec · 2026-03-13 · 19:20 UTC

    @nlnet NLnet Foundation funded open source WireGuard router in FPGA. Featuring PipelineC for cryptography blocks 🤓

    https://github.com/JulianKemmerer/PipelineC/wiki/Example:-ChaCha20%E2%80%90Poly1305-for-WireGuard

    #hardware #fpga #rtl #hdl #hls #verilog #vhdl #cryptography #wireguard #pipelinec

    #hardware #fpga #rtl #hdl #hls #verilog
14. 

    PipelineC @[email protected] · 2026-03-13 · 19:20 UTC

    @nlnet NLnet Foundation funded open source WireGuard router in FPGA. Featuring PipelineC for cryptography blocks 🤓

    https://github.com/JulianKemmerer/PipelineC/wiki/Example:-ChaCha20%E2%80%90Poly1305-for-WireGuard

    #hardware #fpga #rtl #hdl #hls #verilog #vhdl #cryptography #wireguard #pipelinec

    #hardware #fpga #rtl #hdl #hls #verilog
15. 

    PipelineC @[email protected] · 2026-03-13 · 19:20 UTC

    @nlnet NLnet Foundation funded open source WireGuard router in FPGA. Featuring PipelineC for cryptography blocks 🤓

    https://github.com/JulianKemmerer/PipelineC/wiki/Example:-ChaCha20%E2%80%90Poly1305-for-WireGuard

    #hardware #fpga #rtl #hdl #hls #verilog #vhdl #cryptography #wireguard #pipelinec

    #pipelinec #wireguard #cryptography #vhdl #verilog #hls
16. 

    PipelineC @[email protected] · 2026-03-13 · 19:20 UTC

    @nlnet NLnet Foundation funded open source WireGuard router in FPGA. Featuring PipelineC for cryptography blocks 🤓

    https://github.com/JulianKemmerer/PipelineC/wiki/Example:-ChaCha20%E2%80%90Poly1305-for-WireGuard

    #hardware #fpga #rtl #hdl #hls #verilog #vhdl #cryptography #wireguard #pipelinec

    #hardware #fpga #rtl #hdl #hls #verilog
17. 

    PipelineC @[email protected] · 2026-03-10 · 18:46 UTC

    PipelineC holds the throughput lead on Latchup.app. For now! How does your design stack up against a pipelining tool? Far too time consuming and fun of a site 🤓 Look forward to seeing competing solutions.

    https://github.com/JulianKemmerer/PipelineC/wiki/Example:-Latchup-Solutions

    #fpga #asic #rtl #hdl #verilog #vhdl #hls #eda

    #fpga #asic #rtl #hdl #verilog #vhdl
18. 

    PipelineC @pipelinec · 2026-03-10 · 18:46 UTC

    PipelineC holds the throughput lead on Latchup.app. For now! How does your design stack up against a pipelining tool? Far too time consuming and fun of a site 🤓 Look forward to seeing competing solutions.

    https://github.com/JulianKemmerer/PipelineC/wiki/Example:-Latchup-Solutions

    #fpga #asic #rtl #hdl #verilog #vhdl #hls #eda

    #fpga #asic #rtl #hdl #verilog #vhdl
19. 

    PipelineC @[email protected] · 2026-03-10 · 18:46 UTC

    PipelineC holds the throughput lead on Latchup.app. For now! How does your design stack up against a pipelining tool? Far too time consuming and fun of a site 🤓 Look forward to seeing competing solutions.

    https://github.com/JulianKemmerer/PipelineC/wiki/Example:-Latchup-Solutions

    #fpga #asic #rtl #hdl #verilog #vhdl #hls #eda

    #fpga #asic #rtl #hdl #verilog #vhdl
20. 

    PipelineC @[email protected] · 2026-03-10 · 18:46 UTC

    PipelineC holds the throughput lead on Latchup.app. For now! How does your design stack up against a pipelining tool? Far too time consuming and fun of a site 🤓 Look forward to seeing competing solutions.

    https://github.com/JulianKemmerer/PipelineC/wiki/Example:-Latchup-Solutions

    #fpga #asic #rtl #hdl #verilog #vhdl #hls #eda

    #eda #hls #vhdl #verilog #hdl #rtl
21. 

    PipelineC @[email protected] · 2026-03-10 · 18:46 UTC

    PipelineC holds the throughput lead on Latchup.app. For now! How does your design stack up against a pipelining tool? Far too time consuming and fun of a site 🤓 Look forward to seeing competing solutions.

    https://github.com/JulianKemmerer/PipelineC/wiki/Example:-Latchup-Solutions

    #fpga #asic #rtl #hdl #verilog #vhdl #hls #eda

    #fpga #asic #rtl #hdl #verilog #vhdl
22. 

    PipelineC @pipelinec · 2025-07-24 · 21:23 UTC

    How to send a struct from one dev board to another? A PipelineC Story

    #hdl #hls #RTL #fpga #ethernet #i2s #hardware

    https://www.reddit.com/r/FPGA/comments/1m8gl5o/how_to_send_a_struct_from_one_dev_board_to_another/

    #hdl #hls #rtl #fpga #ethernet #i2s
23. 

    PipelineC @pipelinec · 2026-02-13 · 21:50 UTC

    Easy: draw_rect_t struct shared between embedded C software and PipelineC hardware. Mem mapped registers enqueue into command FIFO. Small hardware FSM reads from cmd FIFO does simple iteration to draw a rect of pixels.

    https://github.com/JulianKemmerer/PipelineC/tree/master/examples/stream_soc/gpu

    #hardware #fpga #rtl #hls #hdl #graphics #gpu #cpu

    #hardware #fpga #rtl #hls #hdl #graphics
24. 

    PipelineC @pipelinec · 2026-02-13 · 21:47 UTC

    Is a hardware FSM that draws rectangles to a frame buffer a GPU? Well whatever you call it, it's no longer the CPU pushing pixels in the PipelineC StreamSoC design. Now it sends 'draw rectangle' commands to hardware. And how? #hardware #fpga #rtl #hls #hdl #graphics #gpu #cpu

    #hardware #fpga #rtl #hls #hdl #graphics
25. 

    PipelineC @pipelinec · 2026-02-12 · 17:13 UTC

    Check out PipelineC #HDL Advent of FPGA #hardware solutions: high perf, deeply pipelined, multiple #FPGA platforms, 10's Gbit per sec throughput, easily scales: variable latency off chip mem, faster off chip IO and more resources.

    https://github.com/JulianKemmerer/PipelineC/wiki/Example:-Advent-of-Code-2025

    #rtl #hls #verilog #vhdl #asic #eda

    #hdl #hardware #fpga #rtl #hls #verilog
26. 

    PipelineC @pipelinec · 2024-07-25 · 22:47 UTC

    Over at Digital Design HQ #ddhq, I'm documenting and discussing a #hardware #FPGA #I2S #audio #pmod to-from #AXI project. Stop on by 👋 and see how nice it is to work in #PipelineC 🤓 #RTL #HDL #HLS https://discord.gg/ceheSfKzRM

    #ddhq #hardware #fpga #i2s #audio #pmod
27. 

    PipelineC @pipelinec · 2025-02-14 · 01:42 UTC

    Yay those cheap #hardware #ethernet phy #pmod -LIKE things work with the pico-ice #ice40 #FPGA . Thanks for your help with RMII interface @dutracgi ! #embedded #HDL #RTL #Verilog #VHDL #HLS https://github.com/JulianKemmerer/PipelineC/blob/master/examples/pico-ice/ice_makefile_pipelinec/ethernet_top.c

    #hardware #ethernet #pmod #ice40 #fpga #embedded
28. 

    PipelineC @pipelinec · 2025-01-08 · 02:07 UTC

    In the mood for the littlest bit of #FPGA #GameDev? 🤓 Check out this pico-ice based #pong demo. Just need #VGA #pmod and #UART connected to host PC. #HDL #hardware #RTL #Verilog #VHDL #HLS #lattice #ice40 https://github.com/JulianKemmerer/PipelineC/blob/master/examples/pico-ice/ice_makefile_pipelinec/pong_top.c

    #fpga #gamedev #pong #vga #pmod #uart
29. 

    PipelineC @pipelinec · 2024-06-01 · 16:25 UTC

    Anyone want to help make a #PipelineC version of @DG3YEV 's #FPGA real time #FFT display but for audio? Have Arty w/ #pmod ready to go for testing. Picturing the start of some kind of #hardware #audio visualizer 🤩 with more #DSP learning along the way 🤓
    https://x.com/Dg3Yev/status/1796857709276373211

    #pipelinec #fpga #fft #pmod #hardware #audio
30. 

    PipelineC @pipelinec · 2023-04-26 · 22:43 UTC

    PipelineC's new 'shared resource buses' are pretty neat: Multiple 'threads' of C function derived state machines can easily share resources (memory, compute, etc) by generating AXI-like buses and arbitration. This is still highly experimental but very powerful - reach out if you want to make something together! https://github.com/JulianKemmerer/PipelineC/wiki/Shared-Resource-Bus #rtl #hdl #hls #vhdl #verilog #asic #hardware #multithreaded #hpc

    #rtl #hdl #hls #vhdl #verilog #asic