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#pipelinec — Public Fediverse posts

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  1. PypelineC @pipelinec ·

    Fun in the frequency domain 🤓 Camera pointed at it's own display also showing audio FFT for cool glitchy visualizer effect. Video processing all done in PipelineC hardware. And how?

    github.com/JulianKemmerer/Pipe

    #hardware #fpga #dsp #rtl #hdl #hls
  2. PypelineC @[email protected] ·

    Fun in the frequency domain 🤓 Camera pointed at it's own display also showing audio FFT for cool glitchy visualizer effect. Video processing all done in PipelineC hardware. And how?

    github.com/JulianKemmerer/Pipe

    #hardware #fpga #dsp #rtl #hdl #hls #verilog #vhdl #pipelinec

    #hardware #fpga #dsp #rtl #hdl #hls
  3. PypelineC @[email protected] ·

    Fun in the frequency domain 🤓 Camera pointed at it's own display also showing audio FFT for cool glitchy visualizer effect. Video processing all done in PipelineC hardware. And how?

    github.com/JulianKemmerer/Pipe

    #hardware #fpga #dsp #rtl #hdl #hls #verilog #vhdl #pipelinec

    #pipelinec #vhdl #verilog #hls #hdl #rtl
  4. PypelineC @[email protected] ·

    Fun in the frequency domain 🤓 Camera pointed at it's own display also showing audio FFT for cool glitchy visualizer effect. Video processing all done in PipelineC hardware. And how?

    github.com/JulianKemmerer/Pipe

    #hardware #fpga #dsp #rtl #hdl #hls #verilog #vhdl #pipelinec

    #hardware #fpga #dsp #rtl #hdl #hls
  5. PypelineC @[email protected] ·

    Fun in the frequency domain 🤓 Camera pointed at it's own display also showing audio FFT for cool glitchy visualizer effect. Video processing all done in PipelineC hardware. And how? github.com/JulianKemmer... #hardware #fpga #dsp #rtl #hdl #hls #verilog #vhdl #pipelinec

    #hardware #fpga #dsp #rtl #hdl #hls
  6. PipelineC @[email protected] ·

    @nlnetlabs.bsky.social NLnet Foundation funded open source WireGuard router in FPGA. Featuring PipelineC for cryptography blocks 🤓 github.com/JulianKemmer... #hardware #fpga #rtl #hdl #hls #verilog #vhdl #cryptography #wireguard #pipelinec

    #hardware #fpga #rtl #hdl #hls #verilog
  7. PypelineC @[email protected] ·

    @nlnetlabs.bsky.social NLnet Foundation funded open source WireGuard router in FPGA. Featuring PipelineC for cryptography blocks 🤓 github.com/JulianKemmer... #hardware #fpga #rtl #hdl #hls #verilog #vhdl #cryptography #wireguard #pipelinec

    #hardware #fpga #rtl #hdl #hls #verilog
  8. PipelineC @[email protected] ·

    @nlnetlabs.bsky.social NLnet Foundation funded open source WireGuard router in FPGA. Featuring PipelineC for cryptography blocks 🤓 github.com/JulianKemmer... #hardware #fpga #rtl #hdl #hls #verilog #vhdl #cryptography #wireguard #pipelinec

    #hardware #fpga #rtl #hdl #hls #verilog
  9. PypelineC @pipelinec ·

    @nlnet NLnet Foundation funded open source WireGuard router in FPGA. Featuring PipelineC for cryptography blocks 🤓

    github.com/JulianKemmerer/Pipe

    #hardware #fpga #rtl #hdl #hls #verilog
  10. PypelineC @[email protected] ·

    @nlnet NLnet Foundation funded open source WireGuard router in FPGA. Featuring PipelineC for cryptography blocks 🤓

    github.com/JulianKemmerer/Pipe

    #hardware #fpga #rtl #hdl #hls #verilog #vhdl #cryptography #wireguard #pipelinec

    #hardware #fpga #rtl #hdl #hls #verilog
  11. PypelineC @[email protected] ·

    @nlnet NLnet Foundation funded open source WireGuard router in FPGA. Featuring PipelineC for cryptography blocks 🤓

    github.com/JulianKemmerer/Pipe

    #hardware #fpga #rtl #hdl #hls #verilog #vhdl #cryptography #wireguard #pipelinec

    #pipelinec #wireguard #cryptography #vhdl #verilog #hls
  12. PypelineC @[email protected] ·

    @nlnet NLnet Foundation funded open source WireGuard router in FPGA. Featuring PipelineC for cryptography blocks 🤓

    github.com/JulianKemmerer/Pipe

    #hardware #fpga #rtl #hdl #hls #verilog #vhdl #cryptography #wireguard #pipelinec

    #hardware #fpga #rtl #hdl #hls #verilog
  13. PypelineC @pipelinec ·

    Advent of Code Day 7: very simple design, good intro to . processing all ~hundreds of elements of an entire line each cycle. ~600 million to ~5.3 billion tachyon beams splitting per second. 😎

    github.com/JulianKemmerer/Pipe

    #pipelinec #aoc25 #fpga #hardware #verilog #vhdl
  14. PypelineC @[email protected] ·

    Advent of Code Day 7: very simple design, good intro to #pipelinec. processing all ~hundreds of elements of an entire line each cycle. ~600 million to ~5.3 billion tachyon beams splitting per second. 😎

    github.com/JulianKemmerer/Pipe

    #aoc25 #fpga #hardware #verilog #vhdl #hdl #rtl #hls #asic #eda

    #pipelinec #aoc25 #fpga #hardware #verilog #vhdl
  15. PypelineC @[email protected] ·

    Advent of Code Day 7: very simple design, good intro to #pipelinec. processing all ~hundreds of elements of an entire line each cycle. ~600 million to ~5.3 billion tachyon beams splitting per second. 😎

    github.com/JulianKemmerer/Pipe

    #aoc25 #fpga #hardware #verilog #vhdl #hdl #rtl #hls #asic #eda

    #eda #asic #hls #rtl #hdl #vhdl
  16. PypelineC @[email protected] ·

    Advent of Code Day 7: very simple design, good intro to #pipelinec. processing all ~hundreds of elements of an entire line each cycle. ~600 million to ~5.3 billion tachyon beams splitting per second. 😎

    github.com/JulianKemmerer/Pipe

    #aoc25 #fpga #hardware #verilog #vhdl #hdl #rtl #hls #asic #eda

    #pipelinec #aoc25 #fpga #hardware #verilog #vhdl
  17. PipelineC @[email protected] ·

    Advent of Code Day 7: very simple design, good intro to #pipelinec. processing all ~hundreds of elements of an entire line each cycle. ~600 million to ~5.3 billion tachyon beams splitting per second. 😎 github.com/JulianKemmer... #aoc25 #fpga #hardware #verilog #vhdl #hdl #rtl #hls #asic #eda

    github.com/JulianKemmerer...

    #pipelinec #aoc25 #fpga #hardware #verilog #vhdl
  18. PypelineC @[email protected] ·

    Advent of Code Day 7: very simple design, good intro to #pipelinec. processing all ~hundreds of elements of an entire line each cycle. ~600 million to ~5.3 billion tachyon beams splitting per second. 😎 github.com/JulianKemmer... #aoc25 #fpga #hardware #verilog #vhdl #hdl #rtl #hls #asic #eda

    github.com/JulianKemmerer...

    #pipelinec #aoc25 #fpga #hardware #verilog #vhdl
  19. PipelineC @[email protected] ·

    Advent of Code Day 7: very simple design, good intro to #pipelinec. processing all ~hundreds of elements of an entire line each cycle. ~600 million to ~5.3 billion tachyon beams splitting per second. 😎 github.com/JulianKemmer... #aoc25 #fpga #hardware #verilog #vhdl #hdl #rtl #hls #asic #eda

    github.com/JulianKemmerer...

    #eda #asic #hls #rtl #hdl #vhdl
  20. PipelineC @[email protected] ·

    Advent of Code Day 7: very simple design, good intro to #pipelinec. processing all ~hundreds of elements of an entire line each cycle. ~600 million to ~5.3 billion tachyon beams splitting per second. 😎 github.com/JulianKemmer... #aoc25 #fpga #hardware #verilog #vhdl #hdl #rtl #hls #asic #eda

    github.com/JulianKemmerer...

    #pipelinec #aoc25 #fpga #hardware #verilog #vhdl
  21. PypelineC @pipelinec ·

    Check out @dutracgi 's very cool Modulator written in !
    linkedin.com/pulse/16-apsk-mod

    #16apsk #fpga #pipelinec #hdl #dsp #sdr
  22. PypelineC @[email protected] ·

    Check out @dutracgi 's very cool #16APSK #FPGA Modulator written in #PipelineC #HDL !
    #dsp #sdr #rf #apsk #dac #deltasigma #space #qam #radio #hardware linkedin.com/pulse/16-apsk-mod

    #16apsk #fpga #pipelinec #hdl #dsp #sdr
  23. PypelineC @[email protected] ·

    Check out @dutracgi 's very cool #16APSK #FPGA Modulator written in #PipelineC #HDL !
    #dsp #sdr #rf #apsk #dac #deltasigma #space #qam #radio #hardware linkedin.com/pulse/16-apsk-mod

    #hardware #radio #qam #space #deltasigma #dac
  24. PypelineC @[email protected] ·

    Check out @dutracgi 's very cool #16APSK #FPGA Modulator written in #PipelineC #HDL !
    #dsp #sdr #rf #apsk #dac #deltasigma #space #qam #radio #hardware linkedin.com/pulse/16-apsk-mod

    #16apsk #fpga #pipelinec #hdl #dsp #sdr
  25. PypelineC @pipelinec ·

    Come on over to the Discord channel if you want to join the conversation about this fun work 🤓 discord.gg/vBUtmBZcxC -ice

    #fpga #raspberrypi #pico #pipelinec #hdl #verilog
  26. PypelineC @[email protected] ·

    Come on over to the Discord channel if you want to join the conversation about this fun work 🤓 discord.gg/vBUtmBZcxC #FPGA #raspberrypi #pico-ice #PipelineC #HDL #Verilog #VHDL

    #fpga #raspberrypi #pico #pipelinec #hdl #verilog
  27. PypelineC @[email protected] ·

    Come on over to the Discord channel if you want to join the conversation about this fun work 🤓 discord.gg/vBUtmBZcxC #FPGA #raspberrypi #pico-ice #PipelineC #HDL #Verilog #VHDL

    #vhdl #verilog #hdl #pipelinec #pico #raspberrypi
  28. PypelineC @[email protected] ·

    Come on over to the Discord channel if you want to join the conversation about this fun work 🤓 discord.gg/vBUtmBZcxC #FPGA #raspberrypi #pico-ice #PipelineC #HDL #Verilog #VHDL

    #fpga #raspberrypi #pico #pipelinec #hdl #verilog
  29. PypelineC @pipelinec ·

    Have been super pleased with the and board that pico-ice.tinyvision.ai/ sent me to experiment with. Many thanks and I look forward to putting together a talk for intro users getting started with and boards like the pico-ice 🤓

    #ice40 #fpga #raspberrypi #pipelinec #hdl #verilog
  30. PypelineC @[email protected] ·

    Have been super pleased with the #ice40 #FPGA and #raspberrypi board that pico-ice.tinyvision.ai/ sent me to experiment with. Many thanks and I look forward to putting together a talk for intro users getting started with #PipelineC and boards like the pico-ice 🤓 #HDL #Verilog #VHDL #hardware #embedded

    #ice40 #fpga #raspberrypi #pipelinec #hdl #verilog
  31. PypelineC @[email protected] ·

    Have been super pleased with the #ice40 #FPGA and #raspberrypi board that pico-ice.tinyvision.ai/ sent me to experiment with. Many thanks and I look forward to putting together a talk for intro users getting started with #PipelineC and boards like the pico-ice 🤓 #HDL #Verilog #VHDL #hardware #embedded

    #embedded #hardware #vhdl #verilog #hdl #pipelinec
  32. PypelineC @[email protected] ·

    Have been super pleased with the #ice40 #FPGA and #raspberrypi board that pico-ice.tinyvision.ai/ sent me to experiment with. Many thanks and I look forward to putting together a talk for intro users getting started with #PipelineC and boards like the pico-ice 🤓 #HDL #Verilog #VHDL #hardware #embedded

    #ice40 #fpga #raspberrypi #pipelinec #hdl #verilog
  33. PypelineC @pipelinec ·

    Over at Digital Design HQ , I'm documenting and discussing a to-from project. Stop on by 👋 and see how nice it is to work in 🤓 discord.gg/ceheSfKzRM

    #ddhq #hardware #fpga #i2s #audio #pmod
  34. PypelineC @[email protected] ·

    Over at Digital Design HQ #ddhq, I'm documenting and discussing a #hardware #FPGA #I2S #audio #pmod to-from #AXI project. Stop on by 👋 and see how nice it is to work in #PipelineC 🤓 #RTL #HDL #HLS discord.gg/ceheSfKzRM

    #ddhq #hardware #fpga #i2s #audio #pmod
  35. PypelineC @[email protected] ·

    Over at Digital Design HQ #ddhq, I'm documenting and discussing a #hardware #FPGA #I2S #audio #pmod to-from #AXI project. Stop on by 👋 and see how nice it is to work in #PipelineC 🤓 #RTL #HDL #HLS discord.gg/ceheSfKzRM

    #hls #hdl #rtl #pipelinec #axi #pmod
  36. PypelineC @[email protected] ·

    Over at Digital Design HQ #ddhq, I'm documenting and discussing a #hardware #FPGA #I2S #audio #pmod to-from #AXI project. Stop on by 👋 and see how nice it is to work in #PipelineC 🤓 #RTL #HDL #HLS discord.gg/ceheSfKzRM

    #ddhq #hardware #fpga #i2s #audio #pmod
  37. PypelineC @pipelinec ·

    folks: What's possible with just a few hundred bits of memory? Make custom . friends @suarezvictor and @dutracgi have done LARGE demos in the past. Now the challenge is to be very SMALL! 🤓
    tinytapeout.com/competitions/d

    #graphics #demoscene #asic #hardware #pipelinec #fpga
  38. PypelineC @[email protected] ·

    #graphics #demoscene folks: What's possible with just a few hundred bits of memory? Make custom #ASIC #hardware. #PipelineC friends @suarezvictor and @dutracgi have done LARGE #FPGA demos in the past. Now the challenge is to be very SMALL! 🤓
    tinytapeout.com/competitions/d

    #graphics #demoscene #asic #hardware #pipelinec #fpga
  39. PypelineC @[email protected] ·

    #graphics #demoscene folks: What's possible with just a few hundred bits of memory? Make custom #ASIC #hardware. #PipelineC friends @suarezvictor and @dutracgi have done LARGE #FPGA demos in the past. Now the challenge is to be very SMALL! 🤓
    tinytapeout.com/competitions/d

    #fpga #pipelinec #hardware #asic #demoscene #graphics
  40. PypelineC @[email protected] ·

    #graphics #demoscene folks: What's possible with just a few hundred bits of memory? Make custom #ASIC #hardware. #PipelineC friends @suarezvictor and @dutracgi have done LARGE #FPGA demos in the past. Now the challenge is to be very SMALL! 🤓
    tinytapeout.com/competitions/d

    #graphics #demoscene #asic #hardware #pipelinec #fpga
  41. PypelineC @pipelinec ·

    Anyone want to help make a version of @DG3YEV 's real time display but for audio? Have Arty w/ ready to go for testing. Picturing the start of some kind of visualizer 🤩 with more learning along the way 🤓
    x.com/Dg3Yev/status/1796857709

    #pipelinec #fpga #fft #pmod #hardware #audio
  42. PypelineC @[email protected] ·

    Anyone want to help make a #PipelineC version of @DG3YEV 's #FPGA real time #FFT display but for audio? Have Arty w/ #pmod ready to go for testing. Picturing the start of some kind of #hardware #audio visualizer 🤩 with more #DSP learning along the way 🤓
    x.com/Dg3Yev/status/1796857709

    #pipelinec #fpga #fft #pmod #hardware #audio
  43. PypelineC @[email protected] ·

    Anyone want to help make a #PipelineC version of @DG3YEV 's #FPGA real time #FFT display but for audio? Have Arty w/ #pmod ready to go for testing. Picturing the start of some kind of #hardware #audio visualizer 🤩 with more #DSP learning along the way 🤓
    x.com/Dg3Yev/status/1796857709

    #dsp #audio #hardware #pmod #fft #fpga
  44. PypelineC @[email protected] ·

    Anyone want to help make a #PipelineC version of @DG3YEV 's #FPGA real time #FFT display but for audio? Have Arty w/ #pmod ready to go for testing. Picturing the start of some kind of #hardware #audio visualizer 🤩 with more #DSP learning along the way 🤓
    x.com/Dg3Yev/status/1796857709

    #pipelinec #fpga #fft #pmod #hardware #audio
  45. PypelineC @pipelinec ·

    @tsalvo Just saw your work in progress on the stack implementation in 👋 . Great work, how neat! Hope it has gone well and as always happy to help! 🤓 github.com/tsalvo/varvara-fpga

    #cpu #pipelinec #uxn #varvara #analoguepocket #fpga
  46. PypelineC @[email protected] ·

    @tsalvo Just saw your work in progress on the stack #CPU implementation in #PipelineC 👋 . Great work, how neat! Hope it has gone well and as always happy to help! 🤓 #uxn #varvara #AnaloguePocket #FPGA #stackmachine #FPGA #HDL github.com/tsalvo/varvara-fpga

    #cpu #pipelinec #uxn #varvara #analoguepocket #fpga
  47. PypelineC @[email protected] ·

    @tsalvo Just saw your work in progress on the stack #CPU implementation in #PipelineC 👋 . Great work, how neat! Hope it has gone well and as always happy to help! 🤓 #uxn #varvara #AnaloguePocket #FPGA #stackmachine #FPGA #HDL github.com/tsalvo/varvara-fpga

    #hdl #stackmachine #fpga #analoguepocket #varvara #uxn
  48. PypelineC @[email protected] ·

    @tsalvo Just saw your work in progress on the stack #CPU implementation in #PipelineC 👋 . Great work, how neat! Hope it has gone well and as always happy to help! 🤓 #uxn #varvara #AnaloguePocket #FPGA #stackmachine #FPGA #HDL github.com/tsalvo/varvara-fpga

    #cpu #pipelinec #uxn #varvara #analoguepocket #fpga
  49. PypelineC @pipelinec ·

    Dream is more generic pipelined compute accelerator . next ? Want to allow for custom dataflow to-from memories managed by one or more threads. Always looking for anyone who wants to help, plenty of work to do. Come chat on Discord 🤓 discord.gg/7DECDMvbmc

    #hardware #photogrammetry #cpu #hdl #fpga #hls
  50. PypelineC @[email protected] ·

    Dream is more generic pipelined compute accelerator #hardware. #photogrammetry next ? Want to allow for custom dataflow to-from memories managed by one or more #CPU threads. Always looking for anyone who wants to help, plenty of work to do. Come chat on Discord 🤓 discord.gg/7DECDMvbmc
    #HDL #FPGA #HLS #PipelineC

    #hardware #photogrammetry #cpu #hdl #fpga #hls
  51. PypelineC @[email protected] ·

    Dream is more generic pipelined compute accelerator #hardware. #photogrammetry next ? Want to allow for custom dataflow to-from memories managed by one or more #CPU threads. Always looking for anyone who wants to help, plenty of work to do. Come chat on Discord 🤓 discord.gg/7DECDMvbmc
    #HDL #FPGA #HLS #PipelineC

    #pipelinec #hls #fpga #hdl #cpu #photogrammetry
  52. PypelineC @[email protected] ·

    Dream is more generic pipelined compute accelerator #hardware. #photogrammetry next ? Want to allow for custom dataflow to-from memories managed by one or more #CPU threads. Always looking for anyone who wants to help, plenty of work to do. Come chat on Discord 🤓 discord.gg/7DECDMvbmc
    #HDL #FPGA #HLS #PipelineC

    #hardware #photogrammetry #cpu #hdl #fpga #hls
  53. PypelineC @pipelinec ·

    What kind of fixed point (or small floating point) shaders without textures do yall folks know of? I know @BrunoLevy01 had that great link I need to dig into still 🙌 🤓

    x.com/BrunoLevy01/status/17469

    #graphics #fpga #riscv #hardware #hdl #vhdl
  54. PypelineC @[email protected] ·

    What kind of fixed point (or small floating point) shaders without textures do yall #graphics folks know of? I know @BrunoLevy01 had that great link I need to dig into still 🙌 🤓

    #FPGA #RISCV #hardware #hdl #vhdl #verilog #PipelineC #HLS #graphics

    x.com/BrunoLevy01/status/17469

    #graphics #fpga #riscv #hardware #hdl #vhdl
  55. PypelineC @[email protected] ·

    What kind of fixed point (or small floating point) shaders without textures do yall #graphics folks know of? I know @BrunoLevy01 had that great link I need to dig into still 🙌 🤓

    #FPGA #RISCV #hardware #hdl #vhdl #verilog #PipelineC #HLS #graphics

    x.com/BrunoLevy01/status/17469

    #hls #pipelinec #verilog #vhdl #hdl #hardware
  56. PypelineC @[email protected] ·

    What kind of fixed point (or small floating point) shaders without textures do yall #graphics folks know of? I know @BrunoLevy01 had that great link I need to dig into still 🙌 🤓

    #FPGA #RISCV #hardware #hdl #vhdl #verilog #PipelineC #HLS #graphics

    x.com/BrunoLevy01/status/17469

    #graphics #fpga #riscv #hardware #hdl #vhdl
  57. PypelineC @pipelinec ·

    out of the rendering loop ~DMA style: only limited by the direct connection memory bandwidth to-from DDR controller and the compute pipeline 🔥

    #riscv #cpu #graphics #fpga #hardware #hdl
  58. PypelineC @[email protected] ·

    #RISCV #CPU out of the #graphics rendering loop ~DMA style: only limited by the direct connection memory bandwidth to-from DDR controller and the compute pipeline 🔥
    #FPGA #hardware #HDL #PipelineC #HLS #HPC

    #riscv #cpu #graphics #fpga #hardware #hdl
  59. PypelineC @[email protected] ·

    #RISCV #CPU out of the #graphics rendering loop ~DMA style: only limited by the direct connection memory bandwidth to-from DDR controller and the compute pipeline 🔥
    #FPGA #hardware #HDL #PipelineC #HLS #HPC

    #hpc #hls #pipelinec #hdl #hardware #fpga
  60. PypelineC @[email protected] ·

    #RISCV #CPU out of the #graphics rendering loop ~DMA style: only limited by the direct connection memory bandwidth to-from DDR controller and the compute pipeline 🔥
    #FPGA #hardware #HDL #PipelineC #HLS #HPC

    #riscv #cpu #graphics #fpga #hardware #hdl