#pipelinec — Public Fediverse posts

Fun in the frequency domain 🤓 Camera pointed at it's own display also showing audio FFT for cool glitchy visualizer effect. Video processing all done in PipelineC hardware. And how?

https://github.com/JulianKemmerer/PipelineC/wiki/Example:-Video-Pipelines

#hardware #fpga #dsp #rtl #hdl #hls #verilog #vhdl #pipelinec

Fun in the frequency domain 🤓 Camera pointed at it's own display also showing audio FFT for cool glitchy visualizer effect. Video processing all done in PipelineC hardware. And how?

https://github.com/JulianKemmerer/PipelineC/wiki/Example:-Video-Pipelines

#hardware #fpga #dsp #rtl #hdl #hls #verilog #vhdl #pipelinec

Fun in the frequency domain 🤓 Camera pointed at it's own display also showing audio FFT for cool glitchy visualizer effect. Video processing all done in PipelineC hardware. And how?

https://github.com/JulianKemmerer/PipelineC/wiki/Example:-Video-Pipelines

#hardware #fpga #dsp #rtl #hdl #hls #verilog #vhdl #pipelinec

Fun in the frequency domain 🤓 Camera pointed at it's own display also showing audio FFT for cool glitchy visualizer effect. Video processing all done in PipelineC hardware. And how?

https://github.com/JulianKemmerer/PipelineC/wiki/Example:-Video-Pipelines

#hardware #fpga #dsp #rtl #hdl #hls #verilog #vhdl #pipelinec

Fun in the frequency domain 🤓 Camera pointed at it's own display also showing audio FFT for cool glitchy visualizer effect. Video processing all done in PipelineC hardware. And how? github.com/JulianKemmer... #hardware #fpga #dsp #rtl #hdl #hls #verilog #vhdl #pipelinec

@nlnetlabs.bsky.social NLnet Foundation funded open source WireGuard router in FPGA. Featuring PipelineC for cryptography blocks 🤓 github.com/JulianKemmer... #hardware #fpga #rtl #hdl #hls #verilog #vhdl #cryptography #wireguard #pipelinec

@nlnetlabs.bsky.social NLnet Foundation funded open source WireGuard router in FPGA. Featuring PipelineC for cryptography blocks 🤓 github.com/JulianKemmer... #hardware #fpga #rtl #hdl #hls #verilog #vhdl #cryptography #wireguard #pipelinec

@nlnetlabs.bsky.social NLnet Foundation funded open source WireGuard router in FPGA. Featuring PipelineC for cryptography blocks 🤓 github.com/JulianKemmer... #hardware #fpga #rtl #hdl #hls #verilog #vhdl #cryptography #wireguard #pipelinec

@nlnetlabs.bsky.social NLnet Foundation funded open source WireGuard router in FPGA. Featuring PipelineC for cryptography blocks 🤓 github.com/JulianKemmer... #hardware #fpga #rtl #hdl #hls #verilog #vhdl #cryptography #wireguard #pipelinec

@nlnet NLnet Foundation funded open source WireGuard router in FPGA. Featuring PipelineC for cryptography blocks 🤓

https://github.com/JulianKemmerer/PipelineC/wiki/Example:-ChaCha20%E2%80%90Poly1305-for-WireGuard

#hardware #fpga #rtl #hdl #hls #verilog #vhdl #cryptography #wireguard #pipelinec

@nlnet NLnet Foundation funded open source WireGuard router in FPGA. Featuring PipelineC for cryptography blocks 🤓

https://github.com/JulianKemmerer/PipelineC/wiki/Example:-ChaCha20%E2%80%90Poly1305-for-WireGuard

#hardware #fpga #rtl #hdl #hls #verilog #vhdl #cryptography #wireguard #pipelinec

@nlnet NLnet Foundation funded open source WireGuard router in FPGA. Featuring PipelineC for cryptography blocks 🤓

https://github.com/JulianKemmerer/PipelineC/wiki/Example:-ChaCha20%E2%80%90Poly1305-for-WireGuard

#hardware #fpga #rtl #hdl #hls #verilog #vhdl #cryptography #wireguard #pipelinec

@nlnet NLnet Foundation funded open source WireGuard router in FPGA. Featuring PipelineC for cryptography blocks 🤓

https://github.com/JulianKemmerer/PipelineC/wiki/Example:-ChaCha20%E2%80%90Poly1305-for-WireGuard

#hardware #fpga #rtl #hdl #hls #verilog #vhdl #cryptography #wireguard #pipelinec

@nlnet NLnet Foundation funded open source WireGuard router in FPGA. Featuring PipelineC for cryptography blocks 🤓

https://github.com/JulianKemmerer/PipelineC/wiki/Example:-ChaCha20%E2%80%90Poly1305-for-WireGuard

#hardware #fpga #rtl #hdl #hls #verilog #vhdl #cryptography #wireguard #pipelinec

Advent of Code Day 7: very simple design, good intro to #pipelinec. processing all ~hundreds of elements of an entire line each cycle. ~600 million to ~5.3 billion tachyon beams splitting per second. 😎

https://github.com/JulianKemmerer/PipelineC/blob/master/examples/aof25/day7.c

#aoc25 #fpga #hardware #verilog #vhdl #hdl #rtl #hls #asic #eda

Advent of Code Day 7: very simple design, good intro to #pipelinec. processing all ~hundreds of elements of an entire line each cycle. ~600 million to ~5.3 billion tachyon beams splitting per second. 😎 github.com/JulianKemmer... #aoc25 #fpga #hardware #verilog #vhdl #hdl #rtl #hls #asic #eda

github.com/JulianKemmerer...

Check out @dutracgi 's very cool #16APSK #FPGA Modulator written in #PipelineC #HDL !
#dsp #sdr #rf #apsk #dac #deltasigma #space #qam #radio #hardware https://www.linkedin.com/pulse/16-apsk-modulator-fpga-using-pipelinec-hdl-paulo-dutra-79uce/?trackingId=ldQbwhDmRd%2BU7F35jVGjAQ%3D%3D

Come on over to the Discord channel if you want to join the conversation about this fun work 🤓 https://discord.gg/vBUtmBZcxC #FPGA #raspberrypi #pico-ice #PipelineC #HDL #Verilog #VHDL

Have been super pleased with the #ice40 #FPGA and #raspberrypi board that https://pico-ice.tinyvision.ai/ sent me to experiment with. Many thanks and I look forward to putting together a talk for intro users getting started with #PipelineC and boards like the pico-ice 🤓 #HDL #Verilog #VHDL #hardware #embedded

Over at Digital Design HQ #ddhq, I'm documenting and discussing a #hardware #FPGA #I2S #audio #pmod to-from #AXI project. Stop on by 👋 and see how nice it is to work in #PipelineC 🤓 #RTL #HDL #HLS https://discord.gg/ceheSfKzRM

#graphics #demoscene folks: What's possible with just a few hundred bits of memory? Make custom #ASIC #hardware. #PipelineC friends @suarezvictor and @dutracgi have done LARGE #FPGA demos in the past. Now the challenge is to be very SMALL! 🤓
https://tinytapeout.com/competitions/demoscene/

Anyone want to help make a #PipelineC version of @DG3YEV 's #FPGA real time #FFT display but for audio? Have Arty w/ #pmod ready to go for testing. Picturing the start of some kind of #hardware #audio visualizer 🤩 with more #DSP learning along the way 🤓
https://x.com/Dg3Yev/status/1796857709276373211

@tsalvo Just saw your work in progress on the stack #CPU implementation in #PipelineC 👋 . Great work, how neat! Hope it has gone well and as always happy to help! 🤓 #uxn #varvara #AnaloguePocket #FPGA #stackmachine #FPGA #HDL https://github.com/tsalvo/varvara-fpga

Dream is more generic pipelined compute accelerator #hardware. #photogrammetry next ? Want to allow for custom dataflow to-from memories managed by one or more #CPU threads. Always looking for anyone who wants to help, plenty of work to do. Come chat on Discord 🤓 https://discord.gg/7DECDMvbmc
#HDL #FPGA #HLS #PipelineC

What kind of fixed point (or small floating point) shaders without textures do yall #graphics folks know of? I know @BrunoLevy01 had that great link I need to dig into still 🙌 🤓

#FPGA #RISCV #hardware #hdl #vhdl #verilog #PipelineC #HLS #graphics

https://x.com/BrunoLevy01/status/1746927953865322628

#RISCV #CPU out of the #graphics rendering loop ~DMA style: only limited by the direct connection memory bandwidth to-from DDR controller and the compute pipeline 🔥
#FPGA #hardware #HDL #PipelineC #HLS #HPC

#PipelineC pure function autopipelining combined with libraries for sharing hardware resources with ~AXI like buses + arbitration made this all possible. #fpga #hdl #hls #graphics #SoC #RISCV

1/4 as many RV32I @risc_v cores for same or better performance. Threads share #PipelineC auto pipelined ~15 stage kernel() hardware function to offload shader compute. CPU is now bottleneck for moving data around from RAM to pipeline and back.
#FPGA #HDL #RTL #graphics #riscv

C code that each thread is running: https://github.com/JulianKemmerer/PipelineC/blob/5ec0258cae9bf18d2073be2fb59b4a29b3cd98e0/examples/risc-v/gcc_test/frame_buffer_test.c#L43

C code and #PipelineC play nicely together for when hardware and software need to share interfaces/types 🤓

Code for the barrel #RISCV CPUs in #PipelineC https://github.com/JulianKemmerer/PipelineC/blob/master/examples/risc-v/barrel_risc-v.c

Four RV32I @risc_v cores totaling ~333M IPS do work with a 480p frame buffer 🤓. 20 threads, ~software rendering, but focus isn't on CPU core, next up: experiments with custom accelerator pipelines to offload compute 😏 #PipelineC
#FPGA #HDL #RTL #graphics #RISCV Thanks @BrunoLevy01 and friends!

Use #PipelineC to listen to FM #radio with an #FPGA #SDR! Huge thanks to @dutracgi and @Darkknight512 for making this first version a great learning experience. And @deepwavedigital for the fantastic hardware platform and workplace <3
#hardware #hdl #hls #asic
https://github.com/JulianKemmerer/PipelineC/wiki/Example:-FM-Radio-Demodulation

Very cool work from @DutraCGI , love trying to follow along 😅 🤓

#QAM16 Modulator made with #PipelineC simulation with #GHDL and cocotb! Raised Cosine filter with 0.35 rollof and 4 samples/symbol !
#fpga #qam #sdr #dsp

https://x.com/DutraCGI/status/1715912210910724185?s=20

If the problem is given in the right language, doing RTL digital design like #UART RX can be made as simple as a typical #cprogramming problem.
Any more #embedded #software folks out there want to give the puzzle a go? 🤓
#clang #softwaredevelopment #HDL #HLS #RTL #FPGA #ASIC #hardware #microcontroller #pipelinec
https://github.com/JulianKemmerer/PipelineC/wiki/C-Puzzle

@pipelinec Interesting! Right now I'm just trying to understand what #FPGA have to offer. I like all the words in your #github README, tho.

If I turn out to like FPGAs but hate #HDL, I'll check #PipelineC out.