#yosys — Public Fediverse posts

Встреча FPGA-сообщества: онлайн, вечер, пять докладов

Регулярный слет сообщества FPGA-инженеров и им причастных пройдет 26 мая в 19 часов в формате онлайн-трансляции. В программе вечера пять докладов: о Yosys, SystemRDL, Edge AI и анализе вейвформ с LLM. Подробности о темах и спикерах — под катом. А регистрация —

https://habr.com/ru/companies/yadro/articles/1034776/

#fpga #митап #yosys #systemrdl #edgeai

Встреча FPGA-сообщества: онлайн, вечер, пять докладов

Регулярный слет сообщества FPGA-инженеров и им причастных пройдет 26 мая в 19 часов в формате онлайн-трансляции. В программе вечера пять докладов: о Yosys, SystemRDL, Edge AI и анализе вейвформ с LLM. Подробности о темах и спикерах — под катом. А регистрация —

https://habr.com/ru/companies/yadro/articles/1034776/

#fpga #митап #yosys #systemrdl #edgeai

Встреча FPGA-сообщества: онлайн, вечер, пять докладов

Регулярный слет сообщества FPGA-инженеров и им причастных пройдет 26 мая в 19 часов в формате онлайн-трансляции. В программе вечера пять докладов: о Yosys, SystemRDL, Edge AI и анализе вейвформ с LLM. Подробности о темах и спикерах — под катом. А регистрация —

https://habr.com/ru/companies/yadro/articles/1034776/

#fpga #митап #yosys #systemrdl #edgeai

I've been playing around with #LiteX and #migen #HDL lately and I think it's finally starting to sink in that you can really just do almost arbitrary amounts of "stuff" per clock (limitations apply, objects in mirror may appear closer etc).

It's really very fun! And between trellis, #yosys and #nextpnr you can just... Do it without begging any vendor for a free copy of an EDA.

I highly recommend it! It's so much fun!

You can make your own SoC with deranged peripherals!

#electronics #fpga

I've been playing around with #LiteX and #migen #HDL lately and I think it's finally starting to sink in that you can really just do almost arbitrary amounts of "stuff" per clock (limitations apply, objects in mirror may appear closer etc).

It's really very fun! And between trellis, #yosys and #nextpnr you can just... Do it without begging any vendor for a free copy of an EDA.

I highly recommend it! It's so much fun!

You can make your own SoC with deranged peripherals!

#electronics #fpga

I've been playing around with #LiteX and #migen #HDL lately and I think it's finally starting to sink in that you can really just do almost arbitrary amounts of "stuff" per clock (limitations apply, objects in mirror may appear closer etc).

It's really very fun! And between trellis, #yosys and #nextpnr you can just... Do it without begging any vendor for a free copy of an EDA.

I highly recommend it! It's so much fun!

You can make your own SoC with deranged peripherals!

#electronics #fpga

I've been playing around with #LiteX and #migen #HDL lately and I think it's finally starting to sink in that you can really just do almost arbitrary amounts of "stuff" per clock (limitations apply, objects in mirror may appear closer etc).

It's really very fun! And between trellis, #yosys and #nextpnr you can just... Do it without begging any vendor for a free copy of an EDA.

I highly recommend it! It's so much fun!

You can make your own SoC with deranged peripherals!

#electronics #fpga

I've been playing around with #LiteX and #migen #HDL lately and I think it's finally starting to sink in that you can really just do almost arbitrary amounts of "stuff" per clock (limitations apply, objects in mirror may appear closer etc).

It's really very fun! And between trellis, #yosys and #nextpnr you can just... Do it without begging any vendor for a free copy of an EDA.

I highly recommend it! It's so much fun!

You can make your own SoC with deranged peripherals!

#electronics #fpga

This week experimented with adding a matmul & sorting accelerators (and opcodes for both) to PicoRV32 using the PCPI interface. Also added support for those ops to the Spike RISCV simulator. Yes, Claude helped a huge amount with these tasks which would've likely taken weeks otherwise. The design simulates (Verilator) & sythesizes (yosys) and I can generate a bitstream for both GateMateA1 and ECP5 (OrangeCrab board)

#FPGA #yosys #verilator

This week experimented with adding a matmul & sorting accelerators (and opcodes for both) to PicoRV32 using the PCPI interface. Also added support for those ops to the Spike RISCV simulator. Yes, Claude helped a huge amount with these tasks which would've likely taken weeks otherwise. The design simulates (Verilator) & sythesizes (yosys) and I can generate a bitstream for both GateMateA1 and ECP5 (OrangeCrab board)

#FPGA #yosys #verilator

This week experimented with adding a matmul & sorting accelerators (and opcodes for both) to PicoRV32 using the PCPI interface. Also added support for those ops to the Spike RISCV simulator. Yes, Claude helped a huge amount with these tasks which would've likely taken weeks otherwise. The design simulates (Verilator) & sythesizes (yosys) and I can generate a bitstream for both GateMateA1 and ECP5 (OrangeCrab board)

#FPGA #yosys #verilator

This week experimented with adding a matmul & sorting accelerators (and opcodes for both) to PicoRV32 using the PCPI interface. Also added support for those ops to the Spike RISCV simulator. Yes, Claude helped a huge amount with these tasks which would've likely taken weeks otherwise. The design simulates (Verilator) & sythesizes (yosys) and I can generate a bitstream for both GateMateA1 and ECP5 (OrangeCrab board)

#FPGA #yosys #verilator

This is a wiki about processing video in real time using microcontrollers, ASICs and FPGAs. The related paper was accepted for the Open Source Hardware Conference in Chemnitz Germany, Nov 24-25 2025.

Comment on the page by replying to this toot. #Introduction

#OSHOP #OpenSource #Hardware #FPGA #Yosys #Nextpnr #Video #Pipelines #Introduction

https://wiki.pythonlinks.info/video

This is a wiki about processing video in real time using microcontrollers, ASICs and FPGAs. The related paper was accepted for the Open Source Hardware Conference in Chemnitz Germany, Nov 24-25 2025.

Comment on the page by replying to this toot. #Introduction

#OSHOP #OpenSource #Hardware #FPGA #Yosys #Nextpnr #Video #Pipelines #Introduction

https://wiki.pythonlinks.info/video

This is a wiki about processing video in real time using microcontrollers, ASICs and FPGAs. The related paper was accepted for the Open Source Hardware Conference in Chemnitz Germany, Nov 24-25 2025.

Comment on the page by replying to this toot. #Introduction

#OSHOP #OpenSource #Hardware #FPGA #Yosys #Nextpnr #Video #Pipelines #Introduction

https://wiki.pythonlinks.info/video

One step closer to UNIX v1 using open source toolchain: https://github.com/YosysHQ/yosys/pull/5411

#pipdp11 #yosys #gowin #fpga #retrocomputing

One step closer to UNIX v1 using open source toolchain: https://github.com/YosysHQ/yosys/pull/5411

#pipdp11 #yosys #gowin #fpga #retrocomputing

One step closer to UNIX v1 using open source toolchain: https://github.com/YosysHQ/yosys/pull/5411

#pipdp11 #yosys #gowin #fpga #retrocomputing

One step closer to UNIX v1 using open source toolchain: https://github.com/YosysHQ/yosys/pull/5411

#pipdp11 #yosys #gowin #fpga #retrocomputing

One step closer to UNIX v1 using open source toolchain: https://github.com/YosysHQ/yosys/pull/5411

#pipdp11 #yosys #gowin #fpga #retrocomputing

@PaulaMaddox Well, I've got the gui tool installed and I see I can start with a demo that echoes data back via the Ft+ V2... that seems like a great start.

Crossing fingers.

I'm not worried about an upload tool much. More about design lock in or other anti-patterns.

I'd love to get experience with #yosys and #nextpnr and maybe this will be my excuse to try.

@PaulaMaddox Well, I've got the gui tool installed and I see I can start with a demo that echoes data back via the Ft+ V2... that seems like a great start.

Crossing fingers.

I'm not worried about an upload tool much. More about design lock in or other anti-patterns.

I'd love to get experience with #yosys and #nextpnr and maybe this will be my excuse to try.

@PaulaMaddox Well, I've got the gui tool installed and I see I can start with a demo that echoes data back via the Ft+ V2... that seems like a great start.

Crossing fingers.

I'm not worried about an upload tool much. More about design lock in or other anti-patterns.

I'd love to get experience with #yosys and #nextpnr and maybe this will be my excuse to try.

@PaulaMaddox Well, I've got the gui tool installed and I see I can start with a demo that echoes data back via the Ft+ V2... that seems like a great start.

Crossing fingers.

I'm not worried about an upload tool much. More about design lock in or other anti-patterns.

I'd love to get experience with #yosys and #nextpnr and maybe this will be my excuse to try.

@PaulaMaddox Well, I've got the gui tool installed and I see I can start with a demo that echoes data back via the Ft+ V2... that seems like a great start.

Crossing fingers.

I'm not worried about an upload tool much. More about design lock in or other anti-patterns.

I'd love to get experience with #yosys and #nextpnr and maybe this will be my excuse to try.

the first example was to old, the #yosys Software changed the last years. But now I get an example to work. Nearly everything worked out of the box. After adding a udev/rules.d even programming worked!!! #Yeah

#Opensource #fpga #vhdl #verilog

the first example was to old, the #yosys Software changed the last years. But now I get an example to work. Nearly everything worked out of the box. After adding a udev/rules.d even programming worked!!! #Yeah

#Opensource #fpga #vhdl #verilog

Армения посреди Америки, Китая и России: отчет с EDA Connect 2025

Мысль, что Армения удобна тем, что соединяется и с Америкой, и с Китаем - высказал мне один из китайских участников конференции EDA Connect . А мысль, что Армения соединяется еще и с Россией - возникала естественно при просмотре докладов о логическом синтезаторе, статическом анализаторе и верификации с помощью UVM. Помимо докладов, при конференции прошел хакатон по Verilog и FPGA , на который пришли студенты из Ереванского университета, русско-армянского университета, американо-армянского, французско-армянского, европейско-армянского, и других университетов. Занятно, что второй день хакатона проходил в комнате напротив зала, где большое начальство встречалось с Премьер-Министром Армении. Один из студентов хакатона перепутал дверь, и его перенаправила секьюрити.

https://habr.com/ru/articles/891814/

#Армения #Synopsys #Mentor_Graphics #Verilog #SystemVerilog #Gowin #FPGA #Yosys #Utopia #UVM

Армения посреди Америки, Китая и России: отчет с EDA Connect 2025

Мысль, что Армения удобна тем, что соединяется и с Америкой, и с Китаем - высказал мне один из китайских участников конференции EDA Connect . А мысль, что Армения соединяется еще и с Россией - возникала естественно при просмотре докладов о логическом синтезаторе, статическом анализаторе и верификации с помощью UVM. Помимо докладов, при конференции прошел хакатон по Verilog и FPGA , на который пришли студенты из Ереванского университета, русско-армянского университета, американо-армянского, французско-армянского, европейско-армянского, и других университетов. Занятно, что второй день хакатона проходил в комнате напротив зала, где большое начальство встречалось с Премьер-Министром Армении. Один из студентов хакатона перепутал дверь, и его перенаправила секьюрити.

https://habr.com/ru/articles/891814/

#Армения #Synopsys #Mentor_Graphics #Verilog #SystemVerilog #Gowin #FPGA #Yosys #Utopia #UVM

Армения посреди Америки, Китая и России: отчет с EDA Connect 2025

Мысль, что Армения удобна тем, что соединяется и с Америкой, и с Китаем - высказал мне один из китайских участников конференции EDA Connect . А мысль, что Армения соединяется еще и с Россией - возникала естественно при просмотре докладов о логическом синтезаторе, статическом анализаторе и верификации с помощью UVM. Помимо докладов, при конференции прошел хакатон по Verilog и FPGA , на который пришли студенты из Ереванского университета, русско-армянского университета, американо-армянского, французско-армянского, европейско-армянского, и других университетов. Занятно, что второй день хакатона проходил в комнате напротив зала, где большое начальство встречалось с Премьер-Министром Армении. Один из студентов хакатона перепутал дверь, и его перенаправила секьюрити.

https://habr.com/ru/articles/891814/

#Армения #Synopsys #Mentor_Graphics #Verilog #SystemVerilog #Gowin #FPGA #Yosys #Utopia #UVM

Again, almost all the credit should go to @acqrel, she is the one who built the #yosys backend for this thing, I just took my existing core, removed all but 4 registers and programmed it

Again, almost all the credit should go to @acqrel, she is the one who built the #yosys backend for this thing, I just took my existing core, removed all but 4 registers and programmed it

Again, almost all the credit should go to @acqrel, she is the one who built the #yosys backend for this thing, I just took my existing core, removed all but 4 registers and programmed it

Again, almost all the credit should go to @acqrel, she is the one who built the #yosys backend for this thing, I just took my existing core, removed all but 4 registers and programmed it

Again, almost all the credit should go to @acqrel, she is the one who built the #yosys backend for this thing, I just took my existing core, removed all but 4 registers and programmed it

We had a very productive #FSD meeting earlier today! Check out what we accomplished: https://www.fsf.org/blogs/licensing/fsd-meeting-recap-2025-02-21 #FreeSoftware #Licensing #nextpnr #Yosys

We had a very productive #FSD meeting earlier today! Check out what we accomplished: https://www.fsf.org/blogs/licensing/fsd-meeting-recap-2025-02-21 #FreeSoftware #Licensing #nextpnr #Yosys

We had a very productive #FSD meeting earlier today! Check out what we accomplished: https://www.fsf.org/blogs/licensing/fsd-meeting-recap-2025-02-21 #FreeSoftware #Licensing #nextpnr #Yosys

We had a very productive #FSD meeting earlier today! Check out what we accomplished: https://www.fsf.org/blogs/licensing/fsd-meeting-recap-2025-02-21 #FreeSoftware #Licensing #nextpnr #Yosys

We had a very productive #FSD meeting earlier today! Check out what we accomplished: https://www.fsf.org/blogs/licensing/fsd-meeting-recap-2025-02-21 #FreeSoftware #Licensing #nextpnr #Yosys

I started a project page to document my first FPGA project on a long while, mainly so that I don't forget, but could possibly be useful to others... I'll plan to add subsequent projects and make more progress on this one in the next few weeks and months.

"I bought myself a Radiona ULX3S from CrowdSupply, which includes the 85k Lattice ECP5 FPGA, which can be programmed to simulate the open source 32-bit RISC-V CPU with a completely open source LiteX-yosys-nextpnr, toolchain."

https://blog.bomorgan.io/hobbies/hardware/fpgas/litex-riscv-ecp5-ulx3s/

#riscv #foss #fpga #litex #yosys #nextpnr #linux #crowdsupply #radiona #ulx3s #lattice #ecp5

I started a project page to document my first FPGA project on a long while, mainly so that I don't forget, but could possibly be useful to others... I'll plan to add subsequent projects and make more progress on this one in the next few weeks and months.

"I bought myself a Radiona ULX3S from CrowdSupply, which includes the 85k Lattice ECP5 FPGA, which can be programmed to simulate the open source 32-bit RISC-V CPU with a completely open source LiteX-yosys-nextpnr, toolchain."

https://blog.bomorgan.io/hobbies/hardware/fpgas/litex-riscv-ecp5-ulx3s/

#riscv #foss #fpga #litex #yosys #nextpnr #linux #crowdsupply #radiona #ulx3s #lattice #ecp5

I started a project page to document my first FPGA project on a long while, mainly so that I don't forget, but could possibly be useful to others... I'll plan to add subsequent projects and make more progress on this one in the next few weeks and months.

"I bought myself a Radiona ULX3S from CrowdSupply, which includes the 85k Lattice ECP5 FPGA, which can be programmed to simulate the open source 32-bit RISC-V CPU with a completely open source LiteX-yosys-nextpnr, toolchain."

https://blog.bomorgan.io/hobbies/hardware/fpgas/litex-riscv-ecp5-ulx3s/

#riscv #foss #fpga #litex #yosys #nextpnr #linux #crowdsupply #radiona #ulx3s #lattice #ecp5

I started a project page to document my first FPGA project on a long while, mainly so that I don't forget, but could possibly be useful to others... I'll plan to add subsequent projects and make more progress on this one in the next few weeks and months.

"I bought myself a Radiona ULX3S from CrowdSupply, which includes the 85k Lattice ECP5 FPGA, which can be programmed to simulate the open source 32-bit RISC-V CPU with a completely open source LiteX-yosys-nextpnr, toolchain."

https://blog.bomorgan.io/hobbies/hardware/fpgas/litex-riscv-ecp5-ulx3s/

#riscv #foss #fpga #litex #yosys #nextpnr #linux #crowdsupply #radiona #ulx3s #lattice #ecp5

I started a project page to document my first FPGA project on a long while, mainly so that I don't forget, but could possibly be useful to others... I'll plan to add subsequent projects and make more progress on this one in the next few weeks and months.

"I bought myself a Radiona ULX3S from CrowdSupply, which includes the 85k Lattice ECP5 FPGA, which can be programmed to simulate the open source 32-bit RISC-V CPU with a completely open source LiteX-yosys-nextpnr, toolchain."

https://blog.bomorgan.io/hobbies/hardware/fpgas/litex-riscv-ecp5-ulx3s/

#riscv #foss #fpga #litex #yosys #nextpnr #linux #crowdsupply #radiona #ulx3s #lattice #ecp5

@acqrel's #yosys backend for this thing works 👀🎉

@acqrel's #yosys backend for this thing works 👀🎉

@acqrel's #yosys backend for this thing works 👀🎉

@acqrel's #yosys backend for this thing works 👀🎉

@acqrel's #yosys backend for this thing works 👀🎉

Just got a 32-bit RISC-V SoC programmed into the Lattice ECP5 FPGA on Radiona's ULX3S using the completely open source LiteX toolchain, including yosys and nextpnr.

#fosh #foss #oshw #fpga #riscv #linux #litex #yosys #nextpnr

Just got a 32-bit RISC-V SoC programmed into the Lattice ECP5 FPGA on Radiona's ULX3S using the completely open source LiteX toolchain, including yosys and nextpnr.

#fosh #foss #oshw #fpga #riscv #linux #litex #yosys #nextpnr

Just got a 32-bit RISC-V SoC programmed into the Lattice ECP5 FPGA on Radiona's ULX3S using the completely open source LiteX toolchain, including yosys and nextpnr.

#fosh #foss #oshw #fpga #riscv #linux #litex #yosys #nextpnr

Just got a 32-bit RISC-V SoC programmed into the Lattice ECP5 FPGA on Radiona's ULX3S using the completely open source LiteX toolchain, including yosys and nextpnr.

#fosh #foss #oshw #fpga #riscv #linux #litex #yosys #nextpnr

Just got a 32-bit RISC-V SoC programmed into the Lattice ECP5 FPGA on Radiona's ULX3S using the completely open source LiteX toolchain, including yosys and nextpnr.

#fosh #foss #oshw #fpga #riscv #linux #litex #yosys #nextpnr

quick question about #verilog, or maybe more specifically #yosys: i've been messing around with an icebreaker fpga recently, and the ice40up5k chip has four banks of 32k x 8 bit spram built in. i wanted to use this ram in a design, but (either yosys or nextpnr, i'm not sure which is responsible for assigning hdl declarations to actual hardware) won't automatically assign things to this spram, so you have to manually work with it by instantiating a module of type `sb_spram256ka`. my question, then, is why yosys doesn't mind me using here a module that i haven't defined. since i've told it that i'm using an ice40 chip, is it just implicitly defining a bunch of modules?

quick question about #verilog, or maybe more specifically #yosys: i've been messing around with an icebreaker fpga recently, and the ice40up5k chip has four banks of 32k x 8 bit spram built in. i wanted to use this ram in a design, but (either yosys or nextpnr, i'm not sure which is responsible for assigning hdl declarations to actual hardware) won't automatically assign things to this spram, so you have to manually work with it by instantiating a module of type `sb_spram256ka`. my question, then, is why yosys doesn't mind me using here a module that i haven't defined. since i've told it that i'm using an ice40 chip, is it just implicitly defining a bunch of modules?

The person who is porting #Yosys #NextPrN to #Gatemate on the #olimex board, is discussing his work on this Discord channel. #fpga #digitalmath #addition #multiplication #gaussianlogarithms.

https://discord.gg/gD3tCpbM

The person who is porting #Yosys #NextPrN to #Gatemate on the #olimex board, is discussing his work on this Discord channel. #fpga #digitalmath #addition #multiplication #gaussianlogarithms.

https://discord.gg/gD3tCpbM

The person who is porting #Yosys #NextPrN to #Gatemate on the #olimex board, is discussing his work on this Discord channel. #fpga #digitalmath #addition #multiplication #gaussianlogarithms.

https://discord.gg/gD3tCpbM