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#yosys — Public Fediverse posts

Live and recent posts from across the Fediverse tagged #yosys, aggregated by home.social.

  1. plaes @[email protected] ·

    One step closer to UNIX v1 using open source toolchain: github.com/YosysHQ/yosys/pull/

    #pipdp11 #yosys #gowin #fpga #retrocomputing

    #pipdp11 #yosys #gowin #fpga #retrocomputing
  2. plaes @[email protected] ·

    One step closer to UNIX v1 using open source toolchain: github.com/YosysHQ/yosys/pull/

    #pipdp11 #yosys #gowin #fpga #retrocomputing

    #pipdp11 #yosys #gowin #fpga #retrocomputing
  3. Habr @[email protected] ·

    Армения посреди Америки, Китая и России: отчет с EDA Connect 2025

    Мысль, что Армения удобна тем, что соединяется и с Америкой, и с Китаем - высказал мне один из китайских участников конференции EDA Connect . А мысль, что Армения соединяется еще и с Россией - возникала естественно при просмотре докладов о логическом синтезаторе, статическом анализаторе и верификации с помощью UVM. Помимо докладов, при конференции прошел хакатон по Verilog и FPGA , на который пришли студенты из Ереванского университета, русско-армянского университета, американо-армянского, французско-армянского, европейско-армянского, и других университетов. Занятно, что второй день хакатона проходил в комнате напротив зала, где большое начальство встречалось с Премьер-Министром Армении. Один из студентов хакатона перепутал дверь, и его перенаправила секьюрити.

    habr.com/ru/articles/891814/

    #Армения #Synopsys #Mentor_Graphics #Verilog #SystemVerilog #Gowin #FPGA #Yosys #Utopia #UVM

    #uvm #utopia #yosys #fpga #gowin #systemverilog
  4. Bo Morgan @[email protected] ·

    I started a project page to document my first FPGA project on a long while, mainly so that I don't forget, but could possibly be useful to others... I'll plan to add subsequent projects and make more progress on this one in the next few weeks and months.

    "I bought myself a Radiona ULX3S from CrowdSupply, which includes the 85k Lattice ECP5 FPGA, which can be programmed to simulate the open source 32-bit RISC-V CPU with a completely open source LiteX-yosys-nextpnr, toolchain."

    blog.bomorgan.io/hobbies/hardw

    #riscv #foss #fpga #litex #yosys #nextpnr #linux #crowdsupply #radiona #ulx3s #lattice #ecp5

    #riscv #foss #fpga #litex #yosys #nextpnr
  5. Bo Morgan @[email protected] ·

    I started a project page to document my first FPGA project on a long while, mainly so that I don't forget, but could possibly be useful to others... I'll plan to add subsequent projects and make more progress on this one in the next few weeks and months.

    "I bought myself a Radiona ULX3S from CrowdSupply, which includes the 85k Lattice ECP5 FPGA, which can be programmed to simulate the open source 32-bit RISC-V CPU with a completely open source LiteX-yosys-nextpnr, toolchain."

    blog.bomorgan.io/hobbies/hardw

    #riscv #foss #fpga #litex #yosys #nextpnr #linux #crowdsupply #radiona #ulx3s #lattice #ecp5

    #riscv #foss #fpga #litex #yosys #nextpnr
  6. James against the machine @[email protected] ·

    IT'S ALL HAPPENING!

    Open-source FPGA toolchain on macOS, in my good-friend-and-text-editor, Nova.

    I'm still on the hunt for a better way (on a Mac) to synthesize SystemVerilog directly instead of converting it to Verilog first. If YOU know a way, lmkplskthx!

    Nova is a fantastic, extensible tool from @cabel and his pals at @panic

    #fpga #macDevelopment #yosys #verilog #systemVerilog #tangNano #panicNova #nova

    #fpga #macdevelopment #yosys #verilog #systemverilog #tangnano
  7. James against the machine @[email protected] ·

    IT'S ALL HAPPENING!

    Open-source FPGA toolchain on macOS, in my good-friend-and-text-editor, Nova.

    I'm still on the hunt for a better way (on a Mac) to synthesize SystemVerilog directly instead of converting it to Verilog first. If YOU know a way, lmkplskthx!

    Nova is a fantastic, extensible tool from @cabel and his pals at @panic

    #fpga #macDevelopment #yosys #verilog #systemVerilog #tangNano #panicNova #nova

    #fpga #macdevelopment #yosys #verilog #systemverilog #tangnano
  8. YosysHQ @yosyshq ·

    yosys users group - meet-up #002

    September 7th at 18:00 CEST.

    We'll start with a demo of our new formal equivalence checker targetting the flow. Bring your own design to follow along!

    Afterwards we'll have time for your questions and suggestions.
    Feel free to bring a friend!

    Use this link to join:

    meet.jit.si/NoisyAssembliesExp

    The YosysHQ team will be present and are looking forward to meeting you!

    #openlane #asic #yosys #fpga #meetup
  9. YosysHQ @[email protected] ·

    yosys users group - meet-up #002

    September 7th at 18:00 CEST.

    We'll start with a demo of our new formal equivalence checker targetting the #OpenLane #ASIC flow. Bring your own design to follow along!

    Afterwards we'll have time for your questions and suggestions.
    Feel free to bring a friend!

    Use this link to join:

    meet.jit.si/NoisyAssembliesExp

    The YosysHQ team will be present and are looking forward to meeting you!

    #yosys #fpga #meetup

    #openlane #asic #yosys #fpga #meetup