#verilator — Public Fediverse posts

Создаем I2C Master Controller на Verilog. Тестируем ядро

По результатам написания прошлой статьи у нас получился объемный модуль для реализации функций низкоуровневого управления шиной I2C, который формирует управление линиями SCL/SDA, поддерживает мониторинг шины, ведет передачу и прием данных. В этой статье я предлагаю организовать полноценное вдумчивое тестирование всего что получилось. Всем заинтересованным - добро пожаловать под кат! 🙂

https://habr.com/ru/companies/beget/articles/1024342/

#verilog #verilator #iverilog #gtkwave #i2c_master_controller #testbench #icarus_verilog

Создаем I2C Master Controller на Verilog. Тестируем ядро

По результатам написания прошлой статьи у нас получился объемный модуль для реализации функций низкоуровневого управления шиной I2C, который формирует управление линиями SCL/SDA, поддерживает мониторинг шины, ведет передачу и прием данных. В этой статье я предлагаю организовать полноценное вдумчивое тестирование всего что получилось. Всем заинтересованным - добро пожаловать под кат! 🙂

https://habr.com/ru/companies/beget/articles/1024342/

#verilog #verilator #iverilog #gtkwave #i2c_master_controller #testbench #icarus_verilog

Создаем I2C Master Controller на Verilog. Тестируем ядро

По результатам написания прошлой статьи у нас получился объемный модуль для реализации функций низкоуровневого управления шиной I2C, который формирует управление линиями SCL/SDA, поддерживает мониторинг шины, ведет передачу и прием данных. В этой статье я предлагаю организовать полноценное вдумчивое тестирование всего что получилось. Всем заинтересованным - добро пожаловать под кат! 🙂

https://habr.com/ru/companies/beget/articles/1024342/

#verilog #verilator #iverilog #gtkwave #i2c_master_controller #testbench #icarus_verilog

Создаем I2C Master Controller на Verilog. Тестируем ядро

По результатам написания прошлой статьи у нас получился объемный модуль для реализации функций низкоуровневого управления шиной I2C, который формирует управление линиями SCL/SDA, поддерживает мониторинг шины, ведет передачу и прием данных. В этой статье я предлагаю организовать полноценное вдумчивое тестирование всего что получилось. Всем заинтересованным - добро пожаловать под кат! 🙂

https://habr.com/ru/companies/beget/articles/1024342/

#verilog #verilator #iverilog #gtkwave #i2c_master_controller #testbench #icarus_verilog

Making it match the sim.

Clock shows one clock between last data transition and rising edge of we_n, scope shows two.

Getting closer!

#protonpack #FPGA #Alchitry #Verilator #verilog

This week experimented with adding a matmul & sorting accelerators (and opcodes for both) to PicoRV32 using the PCPI interface. Also added support for those ops to the Spike RISCV simulator. Yes, Claude helped a huge amount with these tasks which would've likely taken weeks otherwise. The design simulates (Verilator) & sythesizes (yosys) and I can generate a bitstream for both GateMateA1 and ECP5 (OrangeCrab board)

#FPGA #yosys #verilator

This week experimented with adding a matmul & sorting accelerators (and opcodes for both) to PicoRV32 using the PCPI interface. Also added support for those ops to the Spike RISCV simulator. Yes, Claude helped a huge amount with these tasks which would've likely taken weeks otherwise. The design simulates (Verilator) & sythesizes (yosys) and I can generate a bitstream for both GateMateA1 and ECP5 (OrangeCrab board)

#FPGA #yosys #verilator

This week experimented with adding a matmul & sorting accelerators (and opcodes for both) to PicoRV32 using the PCPI interface. Also added support for those ops to the Spike RISCV simulator. Yes, Claude helped a huge amount with these tasks which would've likely taken weeks otherwise. The design simulates (Verilator) & sythesizes (yosys) and I can generate a bitstream for both GateMateA1 and ECP5 (OrangeCrab board)

#FPGA #yosys #verilator

This week experimented with adding a matmul & sorting accelerators (and opcodes for both) to PicoRV32 using the PCPI interface. Also added support for those ops to the Spike RISCV simulator. Yes, Claude helped a huge amount with these tasks which would've likely taken weeks otherwise. The design simulates (Verilator) & sythesizes (yosys) and I can generate a bitstream for both GateMateA1 and ECP5 (OrangeCrab board)

#FPGA #yosys #verilator

My Nandgame CPU now has an Assembler.

Yes, it's LLM generated.
I run into the problem that I want to solve problem X, for for that, I need to solve Y, Z, Q, a.s.o first.
I needed a shortcut.

Anyway, I now can sum the numbers from 0 to 10.
I need to manually calculate jump positions. No labels.
I have no proper halt instruction and will probably simply use the nand2tetris convention of "these instruction bits need to be 1". Which is fugly for future extensions.

I have no idea how to properly solve this.

https://git.uvok.de/fpga-exper/tree/nandgame/assembler?h=main

#nandgame #nand2tetris #verilator

My Nandgame CPU now has an Assembler.

Yes, it's LLM generated.
I run into the problem that I want to solve problem X, for for that, I need to solve Y, Z, Q, a.s.o first.
I needed a shortcut.

Anyway, I now can sum the numbers from 0 to 10.
I need to manually calculate jump positions. No labels.
I have no proper halt instruction and will probably simply use the nand2tetris convention of "these instruction bits need to be 1". Which is fugly for future extensions.

I have no idea how to properly solve this.

https://git.uvok.de/fpga-exper/tree/nandgame/assembler?h=main

#nandgame #nand2tetris #verilator

My Nandgame CPU now has an Assembler.

Yes, it's LLM generated.
I run into the problem that I want to solve problem X, for for that, I need to solve Y, Z, Q, a.s.o first.
I needed a shortcut.

Anyway, I now can sum the numbers from 0 to 10.
I need to manually calculate jump positions. No labels.
I have no proper halt instruction and will probably simply use the nand2tetris convention of "these instruction bits need to be 1". Which is fugly for future extensions.

I have no idea how to properly solve this.

https://git.uvok.de/fpga-exper/tree/nandgame/assembler?h=main

#nandgame #nand2tetris #verilator

My Nandgame CPU now has an Assembler.

Yes, it's LLM generated.
I run into the problem that I want to solve problem X, for for that, I need to solve Y, Z, Q, a.s.o first.
I needed a shortcut.

Anyway, I now can sum the numbers from 0 to 10.
I need to manually calculate jump positions. No labels.
I have no proper halt instruction and will probably simply use the nand2tetris convention of "these instruction bits need to be 1". Which is fugly for future extensions.

I have no idea how to properly solve this.

https://git.uvok.de/fpga-exper/tree/nandgame/assembler?h=main

#nandgame #nand2tetris #verilator

More makefile rules.
Trying to get #verilator to work

https://git.uvok.de/fpga-exper/tree/Makefile?h=main#n105

#fpga

It turns out I already had the verilator lint support installed in my #vscode

https://github.com/Migilint/vscode-verilog-linter

And once I compiled/installed #verilator (and set up the path, which unfortunately seems to be manual), it is integrated nicely. It doesn't seem to run automatically though as I type.

#codium #fpga #verilog

Набрасываем на Verilator

Эта статья не является прямым продолжение статьи Время собирать пакеты , но затрагивает связанные темы. Учимся создавать артефакты в рамках концепции Инфраструктура как Артефакт. Будем разворачивать Verilator в Kubernetes.

https://habr.com/ru/articles/890004/

#verilator #kubernetes

Из студентов в инженеры: как перестать бояться и полюбить системную верификацию

Привет, Хабр! На связи Михаил Степанов, инженер в группе функциональной верификации YADRO. Еще в прошлом году мы с моим коллегой Романом Казаченко участвовали в хакатоне по разработке микропроцессоров как студенты, а сейчас — помогаем с задачами для SoC Design Challenge как сотрудники компании-организатора. В статье расскажем, что ждет участников трека «Системная верификация СнК» в этом году и как подготовиться к этому испытанию. Если вы не планируете участвовать в хакатоне, но вам интересно, как инженеры тестируют системы на кристалле перед запуском в производство, эта статья тоже будет вам полезна. На примере заданий хакатона я кратко объясню, что такое системная верификация, из каких блоков состоят СнК и какие инструменты используются для их тестирования.

https://habr.com/ru/companies/yadro/articles/885854/

#SoC_design #функциональная_верификация #системная_верификация #QEMU #verilog #verilator #система_на_кристалле #хакатон #SoC_Design_Challenge

Exciting update for the ROHD community! We're pleased to announce the release of ROHD Cosim v0.3.0, now supporting in/out ports and Verilator for enhanced simulation. Also, ROHD v0.6.2 is out, featuring some bug fixes and improved adder syntax in SystemVerilog. https://buff.ly/3WLth4y #rohd #opensource #hardware #hdl #cosim #verilator

🎉 Spade v0.8.0 has been released 🎉

This release extends the standard library, fixes a whole bunch of small pitfalls, and includes several improvements around tests!

The std-lib now has a higher level wrapper around #fpga block-rams, primitives for clock domain crossing, and reduce_* functions added by @0xC01DC0FFEE

Finally, improved #Verilator support allows cool stuff in tests. The video shows this being used to visualize memory accesses in my camera project

Blog: https://blog.spade-lang.org/v0-8-0/

I think that it is very hard to debug complex #verilog circuits. So many things happening at the same time. So I am about to start writing C++ consistency checks for the #Verilator simulator. If this signal is this way, then that signal should be that way. Run a test, if it fails, guess at the bug, write a consistency test, and run it again.

Very different from testing each block, sadly the #J1 CPU + #Forth is one complex circuit.
#Mecrisp

Exploiting Hardware-Level Parallelism in the Manticore Hardware-Accelerated RTL Simulator - Before a chip design is turned from a hardware design language (HDL) like VHDL or ... - https://hackaday.com/2023/05/10/exploiting-hardware-level-parallelism-in-the-manticore-hardware-accelerated-rtl-simulator/ #rtlsimulator #verilator #hardware #hdl

Exploiting Hardware-Level Parallelism in the Manticore Hardware-Accelerated RTL Simulator - Before a chip design is turned from a hardware design language (HDL) like VHDL or ... - https://hackaday.com/2023/05/10/exploiting-hardware-level-parallelism-in-the-manticore-hardware-accelerated-rtl-simulator/ #rtlsimulator #verilator #hardware #hdl

Exploiting Hardware-Level Parallelism in the Manticore Hardware-Accelerated RTL Simulator - Before a chip design is turned from a hardware design language (HDL) like VHDL or ... - https://hackaday.com/2023/05/10/exploiting-hardware-level-parallelism-in-the-manticore-hardware-accelerated-rtl-simulator/ #rtlsimulator #verilator #hardware #hdl

Exploiting Hardware-Level Parallelism in the Manticore Hardware-Accelerated RTL Simulator - Before a chip design is turned from a hardware design language (HDL) like VHDL or ... - https://hackaday.com/2023/05/10/exploiting-hardware-level-parallelism-in-the-manticore-hardware-accelerated-rtl-simulator/ #rtlsimulator #verilator #hardware #hdl

Exploiting Hardware-Level Parallelism in the Manticore Hardware-Accelerated RTL Simulator - Before a chip design is turned from a hardware design language (HDL) like VHDL or ... - https://hackaday.com/2023/05/10/exploiting-hardware-level-parallelism-in-the-manticore-hardware-accelerated-rtl-simulator/ #rtlsimulator #verilator #hardware #hdl

If you’re using @panic ’s Nova to edit your Verilog files, you'll be happy to know that @tsalvo ‘s Verilog extension now supports linting too via verilator…

nova://extension/?id=com.tomsalvo.verilog&name=Verilog

https://github.com/tsalvo/Verilog-Nova-Extension

#FPGA #OpenFPGA #Verilog #Nova #Verilator

Want To Play With FPGAs? Use Your Pico! - Ever want to play with an FPGA, but don’t have the hardware? Now, if you have one ... - https://hackaday.com/2022/12/31/want-to-play-with-fpgas-use-your-pico/ #raspberrypipico #fpgaemulation #raspberrypi #emulation #verilator #verilog #pipico #rp2040 #fpga

I prefer #verilog - it is the C to #VHDL's Java, if you like. One is concise, the other verbose. One gives you plenty of rope to shoot yourself in the foot, the other tires you out. In the famous shootout, the #verilog team got the job done soonest. However, it's possible that in a complex and critical case like aerospace, the #vhdl team would make something more correct.

Many tools allow a free mix of HDLs. But the fastest simulator, #verilator is free and verilog-only.

@profoundlynerdy