#migen — Public Fediverse posts

I've been playing around with #LiteX and #migen #HDL lately and I think it's finally starting to sink in that you can really just do almost arbitrary amounts of "stuff" per clock (limitations apply, objects in mirror may appear closer etc).

It's really very fun! And between trellis, #yosys and #nextpnr you can just... Do it without begging any vendor for a free copy of an EDA.

I highly recommend it! It's so much fun!

You can make your own SoC with deranged peripherals!

#electronics #fpga

I've been playing around with #LiteX and #migen #HDL lately and I think it's finally starting to sink in that you can really just do almost arbitrary amounts of "stuff" per clock (limitations apply, objects in mirror may appear closer etc).

It's really very fun! And between trellis, #yosys and #nextpnr you can just... Do it without begging any vendor for a free copy of an EDA.

I highly recommend it! It's so much fun!

You can make your own SoC with deranged peripherals!

#electronics #fpga

I've been playing around with #LiteX and #migen #HDL lately and I think it's finally starting to sink in that you can really just do almost arbitrary amounts of "stuff" per clock (limitations apply, objects in mirror may appear closer etc).

It's really very fun! And between trellis, #yosys and #nextpnr you can just... Do it without begging any vendor for a free copy of an EDA.

I highly recommend it! It's so much fun!

You can make your own SoC with deranged peripherals!

#electronics #fpga

I've been playing around with #LiteX and #migen #HDL lately and I think it's finally starting to sink in that you can really just do almost arbitrary amounts of "stuff" per clock (limitations apply, objects in mirror may appear closer etc).

It's really very fun! And between trellis, #yosys and #nextpnr you can just... Do it without begging any vendor for a free copy of an EDA.

I highly recommend it! It's so much fun!

You can make your own SoC with deranged peripherals!

#electronics #fpga

I've been playing around with #LiteX and #migen #HDL lately and I think it's finally starting to sink in that you can really just do almost arbitrary amounts of "stuff" per clock (limitations apply, objects in mirror may appear closer etc).

It's really very fun! And between trellis, #yosys and #nextpnr you can just... Do it without begging any vendor for a free copy of an EDA.

I highly recommend it! It's so much fun!

You can make your own SoC with deranged peripherals!

#electronics #fpga

Pro tips when using Migen's SyncFIFO() module in your pipeline design...

I went from 70 MHz max frequency to 100+ MHz by just adding this parameter: `buffered=True`

It helped a lot for timing closure of the design :)

#FPGA #ECP5 #OpenSource #LiteX #Migen #SucréLA #HydraSucréLA

Pro tips when using Migen's SyncFIFO() module in your pipeline design...

I went from 70 MHz max frequency to 100+ MHz by just adding this parameter: `buffered=True`

It helped a lot for timing closure of the design :)

#FPGA #ECP5 #OpenSource #LiteX #Migen #SucréLA #HydraSucréLA

Pro tips when using Migen's SyncFIFO() module in your pipeline design...

I went from 70 MHz max frequency to 100+ MHz by just adding this parameter: `buffered=True`

It helped a lot for timing closure of the design :)

#FPGA #ECP5 #OpenSource #LiteX #Migen #SucréLA #HydraSucréLA

Pro tips when using Migen's SyncFIFO() module in your pipeline design...

I went from 70 MHz max frequency to 100+ MHz by just adding this parameter: `buffered=True`

It helped a lot for timing closure of the design :)

#FPGA #ECP5 #OpenSource #LiteX #Migen #SucréLA #HydraSucréLA

Playing with #litex #litescope FPGA logic analyzer. That stuff works super well. What the #FOSS #fpga people (#litex #migen #oss-cad #yosys #openocd and all the others hidden in the toolchain) have done is amazing. The board is a colorlight 5a-75b with an ECP5.
https://kraut.zone/w/k2qy5PXbBuHhozcDf9QgbP

Code: https://github.com/bjonnh/alscope

Playing with #litex #litescope FPGA logic analyzer. That stuff works super well. What the #FOSS #fpga people (#litex #migen #oss-cad #yosys #openocd and all the others hidden in the toolchain) have done is amazing. The board is a colorlight 5a-75b with an ECP5.
https://kraut.zone/w/k2qy5PXbBuHhozcDf9QgbP

Code: https://github.com/bjonnh/alscope

Playing with #litex #litescope FPGA logic analyzer. That stuff works super well. What the #FOSS #fpga people (#litex #migen #oss-cad #yosys #openocd and all the others hidden in the toolchain) have done is amazing. The board is a colorlight 5a-75b with an ECP5.
https://kraut.zone/w/k2qy5PXbBuHhozcDf9QgbP

Code: https://github.com/bjonnh/alscope

Playing with #litex #litescope FPGA logic analyzer. That stuff works super well. What the #FOSS #fpga people (#litex #migen #oss-cad #yosys #openocd and all the others hidden in the toolchain) have done is amazing. The board is a colorlight 5a-75b with an ECP5.
https://kraut.zone/w/k2qy5PXbBuHhozcDf9QgbP

Code: https://github.com/bjonnh/alscope

Playing with #litex #litescope FPGA logic analyzer. That stuff works super well. What the #FOSS #fpga people (#litex #migen #oss-cad #yosys #openocd and all the others hidden in the toolchain) have done is amazing. The board is a colorlight 5a-75b with an ECP5.
https://kraut.zone/w/k2qy5PXbBuHhozcDf9QgbP

Code: https://github.com/bjonnh/alscope

#migen question: how can i get, for instance, pin one of the PMOD connector, without writing up _io defs?

/cc @cr1901