#ecp5 — Public Fediverse posts

The @RadionaOrg ULX3S hub site now honors device dark mode! Sunglasses no longer needed 😎

I also added a Tiny Tapeout section, as (pending a few Pull Request merges) @latticesemi #ECP5 FPGA support for testing your ASIC design on the #ULX3S is coming to @tinytapeout

explanation is that I am still waiting for the 2.5V LDO *with the correct footprint* to arrive :p

#fpga #ecp5

It's hard to find time to post updates on all the progress I am making on the SucréLA #opensource #FPGA based Logic Analyzer 🥵

But it's going forward full steam! 🚂 🚄

Lots of fixes and robustification pushed. 🔧 ✅

It's now working pretty well in PulseView sampling as fast as 128 Msps which is pretty good for a first 2-boards-plugged-together-prototype. 😍

I'm even mostly using it to debug itself now! 🤳

#ecp5 #soc #oshw #SucreLA #fpga

So, to "conclude" yesterday's debug session, it seems that increasing the number of parallel libusb async bulk tranfers from 16 to 32 fixes the issue.

No more late USB reads from the host!
If someone has theories on how to "calibrate" this number of parallel transfers ... is there a formula somewhere?
I still don't understand yet why 32 was not enough and what makes those fail.

#usb #SucreLA #fpga #ecp5 #opensource #logicielslibres

I found the issue! 🥳

Can you see it? :) 🔬 🐛

#opensource #fpga #ecp5 #oshw #SucreLA #logicielslibres #electronics #soc

I'm dogfooding SucréLA! 🐶

I'm currently using it to .... debug itself!

This is showing HSPI packets and the timing of the MCU IRQ handlers for HSPI and USB.

So cool to use it for real and to debug itself :)

#opensource #fpga #ecp5 #oshw #SucreLA #logicielslibres #electronics #soc

SucréLA open-source sw/hw/gateware Logic Analyzer now supports a new exciting feature: x2 and x4 oversampling ! 🥳

Meaning that while the capture pipeline in the SoC runs @ X MHz on N probes, it can now also sample:
* N/2 probes @ 2*X MHz 😍
or
* N/4 probes @ 4*X MHz 🥵

While continuously streaming data to the host PC running sigrok/PulseView via USB 3.0 ⚡

Wanna see how this feature has been developed? 🫣

https://gitlab.com/yannsionneau/SucreLA/-/commit/fbba0ced39b5d9e3c3f4cf9f92c592914d8afee2 🤓

#opensource #fpga #ecp5 #logicielslibres #oshw #soc #SucreLA

I'm making lots of progress on the HydraSucréLA bringup! 🎺

Open source sw/hw/gateware logic analyzer incoming!

It's already capturing 🎉 🥳

#opensource #hardware #fpga #ecp5 #LiteX

Icepi Zero is an open source FPGA board in a Raspberry Pi Zero-sized form factor (crowdfunding)

Nearly a decade ago, Raspberry Pi showed that it’s possible to cram a fully functional computer into a tiny package that’s about the size of a stick of chewing gum or about the size of a USB flash drive. In time since the first Raspberry Pi Zero launched we’ve seen a bunch of updates as well as third-party boards with a similar design but different hardware.

But the Icepi Zero stands out for a […]

#crowdfunding #ecp5 #fpga #icepiZero #openHardware #openSource #raspberryPiZero #sbc

Read more: https://liliputing.com/icepi-zero-is-an-open-source-fpga-board-in-a-raspberry-pi-zero-sized-form-factor/

If someone wants to help me debug my Lattice ECP5 SSPI programming issue: I uploaded the pulseview (logic analyzer) dumps of the SPI link: https://limewire.com/d/8Xdrk#iWBdBVyut2

You can open this with pulseview and add a SPI decoder.

#fpga #ecp5 #opensource #SucreLA

Do you know some source code out there that programs a Lattice ECP5 FPGA via SSPI interface? (and not jtag nor spi flash nor parallel itf)

I am trying to implement it and so far I think I'm really close but something does not work yet... 🤔

PS: I've read countless times the sysCONFIG manual 😭

#ecp5 #lattice #fpga #opensource

Pro tips when using Migen's SyncFIFO() module in your pipeline design...

I went from 70 MHz max frequency to 100+ MHz by just adding this parameter: `buffered=True`

It helped a lot for timing closure of the design :)

#FPGA #ECP5 #OpenSource #LiteX #Migen #SucréLA #HydraSucréLA

Pro tips when using Migen's SyncFIFO() module in your pipeline design...

I went from 70 MHz max frequency to 100+ MHz by just adding this parameter: `buffered=True`

It helped a lot for timing closure of the design :)

#FPGA #ECP5 #OpenSource #LiteX #Migen #SucréLA #HydraSucréLA

Pro tips when using Migen's SyncFIFO() module in your pipeline design...

I went from 70 MHz max frequency to 100+ MHz by just adding this parameter: `buffered=True`

It helped a lot for timing closure of the design :)

#FPGA #ECP5 #OpenSource #LiteX #Migen #SucréLA #HydraSucréLA

Pro tips when using Migen's SyncFIFO() module in your pipeline design...

I went from 70 MHz max frequency to 100+ MHz by just adding this parameter: `buffered=True`

It helped a lot for timing closure of the design :)

#FPGA #ECP5 #OpenSource #LiteX #Migen #SucréLA #HydraSucréLA

I started a project page to document my first FPGA project on a long while, mainly so that I don't forget, but could possibly be useful to others... I'll plan to add subsequent projects and make more progress on this one in the next few weeks and months.

"I bought myself a Radiona ULX3S from CrowdSupply, which includes the 85k Lattice ECP5 FPGA, which can be programmed to simulate the open source 32-bit RISC-V CPU with a completely open source LiteX-yosys-nextpnr, toolchain."

https://blog.bomorgan.io/hobbies/hardware/fpgas/litex-riscv-ecp5-ulx3s/

#riscv #foss #fpga #litex #yosys #nextpnr #linux #crowdsupply #radiona #ulx3s #lattice #ecp5

I started a project page to document my first FPGA project on a long while, mainly so that I don't forget, but could possibly be useful to others... I'll plan to add subsequent projects and make more progress on this one in the next few weeks and months.

"I bought myself a Radiona ULX3S from CrowdSupply, which includes the 85k Lattice ECP5 FPGA, which can be programmed to simulate the open source 32-bit RISC-V CPU with a completely open source LiteX-yosys-nextpnr, toolchain."

https://blog.bomorgan.io/hobbies/hardware/fpgas/litex-riscv-ecp5-ulx3s/

#riscv #foss #fpga #litex #yosys #nextpnr #linux #crowdsupply #radiona #ulx3s #lattice #ecp5

I started a project page to document my first FPGA project on a long while, mainly so that I don't forget, but could possibly be useful to others... I'll plan to add subsequent projects and make more progress on this one in the next few weeks and months.

"I bought myself a Radiona ULX3S from CrowdSupply, which includes the 85k Lattice ECP5 FPGA, which can be programmed to simulate the open source 32-bit RISC-V CPU with a completely open source LiteX-yosys-nextpnr, toolchain."

https://blog.bomorgan.io/hobbies/hardware/fpgas/litex-riscv-ecp5-ulx3s/

#riscv #foss #fpga #litex #yosys #nextpnr #linux #crowdsupply #radiona #ulx3s #lattice #ecp5

I started a project page to document my first FPGA project on a long while, mainly so that I don't forget, but could possibly be useful to others... I'll plan to add subsequent projects and make more progress on this one in the next few weeks and months.

"I bought myself a Radiona ULX3S from CrowdSupply, which includes the 85k Lattice ECP5 FPGA, which can be programmed to simulate the open source 32-bit RISC-V CPU with a completely open source LiteX-yosys-nextpnr, toolchain."

https://blog.bomorgan.io/hobbies/hardware/fpgas/litex-riscv-ecp5-ulx3s/

#riscv #foss #fpga #litex #yosys #nextpnr #linux #crowdsupply #radiona #ulx3s #lattice #ecp5

I started a project page to document my first FPGA project on a long while, mainly so that I don't forget, but could possibly be useful to others... I'll plan to add subsequent projects and make more progress on this one in the next few weeks and months.

"I bought myself a Radiona ULX3S from CrowdSupply, which includes the 85k Lattice ECP5 FPGA, which can be programmed to simulate the open source 32-bit RISC-V CPU with a completely open source LiteX-yosys-nextpnr, toolchain."

https://blog.bomorgan.io/hobbies/hardware/fpgas/litex-riscv-ecp5-ulx3s/

#riscv #foss #fpga #litex #yosys #nextpnr #linux #crowdsupply #radiona #ulx3s #lattice #ecp5

https://www.reddit.com/r/FPGA/comments/1hvtgn9/fpga_developers_forum_2025_call_for_abstracts/

#fpga #conference #cfp #gatemate #ice40 #ecp5 #xilinx #altera #lattice

The 50€ #olimex #Gatemate board is a great value.

https://www.olimex.com/Products/FPGA/GateMate/

The extension boards make it a very viable choice.

https://github.com/intergalaktik/Extension_Boards_for_Olimex_GateMate
@olimex #fpga #ECP5 #pico-ice

Routing in progress!

#ECP5 #HydraUSB3 #SucreLA

Routing in progress!

#ECP5 #HydraUSB3 #SucreLA

Routing in progress!

#ECP5 #HydraUSB3 #SucreLA

Routing in progress!

#ECP5 #HydraUSB3 #SucreLA

Routing in progress!

#ECP5 #HydraUSB3 #SucreLA

Clearly the #LatticeSemi #ECP5 (and iCE40) #FPGA dominates the landscape of #yosys / #nextpnr compatible dev kits but where are the #Nexus board? Anyone knows why? Availability, unfamiliarity, value, performance?

Clearly the #LatticeSemi #ECP5 (and iCE40) #FPGA dominates the landscape of #yosys / #nextpnr compatible dev kits but where are the #Nexus board? Anyone knows why? Availability, unfamiliarity, value, performance?

Clearly the #LatticeSemi #ECP5 (and iCE40) #FPGA dominates the landscape of #yosys / #nextpnr compatible dev kits but where are the #Nexus board? Anyone knows why? Availability, unfamiliarity, value, performance?

AHHHH! I finally got a ring oscillator working on #ECP5 with the #Yosys / #Nextpnr tool chain (I’m not complaining, I’m happy they exist and I’m doing something unorthodox)

You have to instantiate the inverters as LUTs directly *AND* you have to build the latest tools yourself (I had two different binaries segfault on the design).

https://github.com/YosysHQ/nextpnr/issues/1194#issuecomment-1684724413
#verilog #fpga #ncl #asynclogic

I am building a many core #Forth processor on Lattice Semiconductor FPGAs using the open source #Yosys tools. The first products released will be two 4 core processors. 16K* 16 bit words or 10.6K * 24 bit words. Every pair of processors will communicate using 10Kbits of dual port RAM. The processors will run on the $35 #PicoIce and $30 #Upduino boards. Later there will be hundreds of cores on the larger #ULX3S #ECP5 boards.

My climate persona: @UncensoredNews
#fpga #ManyCore #introduction

Heya #fpga #embedded crowd!

Is there any #ECP5 dev board/module out there, that basically breaks out most of the IOs of the LFE5U-85?

I'm looking for something like the Colorlight i9, but for my project, i need to have the LFE5U-85.

#latticesemi #yosys #pmod

Heya #fpga #embedded crowd!

Is there any #ECP5 dev board/module out there, that basically breaks out most of the IOs of the LFE5U-85?

I'm looking for something like the Colorlight i9, but for my project, i need to have the LFE5U-85.

#latticesemi #yosys #pmod

Heya #fpga #embedded crowd!

Is there any #ECP5 dev board/module out there, that basically breaks out most of the IOs of the LFE5U-85?

I'm looking for something like the Colorlight i9, but for my project, i need to have the LFE5U-85.

#latticesemi #yosys #pmod

Heya #fpga #embedded crowd!

Is there any #ECP5 dev board/module out there, that basically breaks out most of the IOs of the LFE5U-85?

I'm looking for something like the Colorlight i9, but for my project, i need to have the LFE5U-85.

#latticesemi #yosys #pmod

Heya #fpga #embedded crowd!

Is there any #ECP5 dev board/module out there, that basically breaks out most of the IOs of the LFE5U-85?

I'm looking for something like the Colorlight i9, but for my project, i need to have the LFE5U-85.

#latticesemi #yosys #pmod

New Part Day: LED Driver is FPGA Dev Board in Disguise - Our new part of the day is the ColorLight 5A-75B, a board that’s meant to drive eight of those ubiqu... more: https://hackaday.com/2020/01/24/new-part-day-led-driver-is-fpga-dev-board-in-disguise/ #reverseengineering #hackadaycolumns #opensource #icestorm #devkit #parts #fpga #ecp5

for everyone interested in #fpga and #opensourcehardware: radiona.org (makerspace i'm member of) recently published details about our #fpga #ECP5 development board: https://radiona.org/ulx3s/
it has been in development for some time now and already has few testers around the world but now we have "user friendly" page with details. we''re collecting interest/preorders now and first batch of boards should be available in the next few months.

Have you heard that #ECP5 FPGAs are now supported by open source toolchain? Exciting!

https://forum.mystorm.uk/t/ot-large-ecp5-fpgas-now-supported-by-open-source-tooling/488?u=biged

Which also means there's a new open source router for FPGAs which is timing driven and, as it happens, faster.

@vertigo @ddipaola