#icepizero — Public Fediverse posts on home.social

2026-10-07

Success!

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UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1171242884.8%TRELLIS_FF177242880.7%TRELLIS_IO111975.6%
TimingClockAchievedConstraint$glbnet$clkp39.04 MHz25 MHz$glbnet$clkt345.18 MHz250 MHz
Code

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1');

        uart_data : out std_logic_vector(7 downto 0) := (others => '0');
        uart_ready : in std_logic;
        uart_valid : out std_logic := '0'
    );
end my_code;

architecture rtl of my_code is
    alias red   : std_logic_vector(7 downto 0) is background_color(23 downto 16);
    alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8);
    alias blue  : std_logic_vector(7 downto 0) is background_color(7 downto 0);

    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant example_text : string := "Hello Fediverse! <3";
    constant example_text_row : integer := 15;
    constant example_text_col : integer := 15;

    constant uart_text : string := "Hello Fediverse on UART!" & LF;
begin
    char <= character'pos(example_text(col + 1 - example_text_col))
        when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0;

    red   <= std_logic_vector(to_unsigned(col*4, 8));
    green <= std_logic_vector(to_unsigned(py, 8));
    blue  <= std_logic_vector(resize(frame_counter, 8));

    foreground_color <= (others => '1');

    process(clk)
        variable old_vsync : std_logic := '0';

        variable uart_counter : integer range uart_text'range := 1;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                frame_counter <= frame_counter + 1;
            end if;
            old_vsync := vsync;

            uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8));
            uart_valid <= '1';
            if uart_ready = '1' and uart_valid = '1' then
                if uart_counter < uart_text'length then
                    uart_counter := uart_counter + 1;
                else
                    uart_counter := 1;
                end if;
            end if;
        end if;
    end process;
end architecture;

#FPGA #Icepi-Zero #HDL #VHDL

#fpga #icepizero #hdl #vhdl

JCM @[email protected]

2026-08-23

Fully initialized!!! :D

(the screenshot only shows the responses from the SD card, because I am too lazy to write proper UART)

#FPGA #VHDL #HDL #Icepi-Zero #these-two-additional-steps-were-surpringly-light-on-my-state-machine

#fpga #vhdl #hdl #icepizero #thesetwoadditionalstepsweresurpringlylightonmystatemachine

JCM @[email protected]

2026-08-22

OMGGGG, first few steps of SD card initalization work!!!

#this-one-probably-wins-the-price-of-the-worst-ever-state-machine-I-wrote #it's-basically-two-different-state-machines-frankensteined-together #VHDL #HDL #Icepi-Zero #FPGA

#thisoneprobablywinsthepriceoftheworsteverstatemachineiwrote #itsbasicallytwodifferentstatemachinesfrankensteinedtogether #vhdl #hdl #icepizero #fpga

JCM @[email protected]

2026-08-04

printf debugging? LED debugging!

#FPGA #Icepi-Zero

#fpga #icepizero

JCM @[email protected]

2026-06-27

Managed to go from

Info:                   DP16KD:       0/     56     0%
Info:               MULT18X18D:       1/     28     3%
Info:               TRELLIS_FF:    1612/  24288     6%
Info:             TRELLIS_COMB:    5705/  24288    23%
Info: Max frequency for clock '$glbnet$main_clk': 25.20 MHz (PASS at 25.00 MHz)

to

Info:                   DP16KD:       1/     56     1%
Info:               MULT18X18D:       1/     28     3%
Info:               TRELLIS_FF:     515/  24288     2%
Info:             TRELLIS_COMB:    2480/  24288    10%
Info: Max frequency for clock '$glbnet$main_clk': 57.34 MHz (PASS at 25.00 MHz)

by replacing my hacky register-based string templating solution with a (still hacky) RAM-based one and by setting ranges on all my integer.

Feels good~

RE: https://wafrn.jcm.re/fediverse/post/627f72e6-73a3-415e-b5a7-88dbeb959b1a
#vhdl #icepi-zero #fpga #hdl #hardware-development #this-is-gonna-be-so-incredibly-cursed-in-the-end-xD

#vhdl #icepizero #fpga #hdl #hardwaredevelopment #thisisgonnabesoincrediblycursedintheendxd

Icepi Zero Bot @[email protected]

2026-06-26

@[email protected] asked

Success!

UART Output

UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1024242884.2%TRELLIS_FF157242880.6%TRELLIS_IO111975.6%
TimingClockAchievedConstraint$glbnet$clkp39.77 MHz25 MHz$glbnet$clkt321.34 MHz250 MHz
Code

module my_code #(
    param WIDTH: p32 = 640,
    param HEIGHT: p32 = 480,
    param CONSOLE_COLUMNS: p32 = WIDTH / 8,
    param CONSOLE_ROWS: p32 = HEIGHT / 8
) (
    clk: input clock,
    rst: input reset,

    px: input u32,
    py: input u32,
    hsync: input logic,
    vsync: input logic,

    col: input u32,
    row: input u32,

    char: output u32,
    foreground_color: output logic<24>,
    background_color: output logic<24>,

    uart_data: output logic<8>,
    uart_ready: input logic,
    uart_valid: output logic
) {
    var frame_counter: u32;
    var old_vsync: logic;

    var red: logic<8>;
    var green: logic<8>;
    var blue: logic<8>;

    always_comb {
        red   = (col * 4) as u8;
        green = py as u8;
        blue  = frame_counter as u8;

        background_color = {red, green, blue};
        foreground_color = 24'hff_ff_ff;

        char = 0;
        if(row == 10) {
            if(col == 5) { char = 8'h56; }
            if(col == 6) { char = 8'h65; }
            if(col == 7) { char = 8'h72; }
            if(col == 8) { char = 8'h79; }
            if(col == 9) { char = 8'h6c; }
        }

        uart_data = 0;
        uart_valid = 0;
    }

    always_ff (clk, rst) {
        if_reset {
            frame_counter = 0;
            old_vsync = 0;
        } else {
            if(!vsync && old_vsync) {
                frame_counter = frame_counter + 1;
            }
            old_vsync = vsync;
        }
    }
}

#FPGA #Icepi-Zero #HDL #Veryl

#fpga #icepizero #hdl #veryl

Open Source Hardware News @[email protected]

2026-06-18

Which Verilog TMDS encoding library do you recommend that I use on the Ice Pi Zero? Here is my review of the options.

https://wiki.pythonlinks.info/dvi-rtl-libraries

#Verilog #VHDL #tMDS #IcePiZero

#verilog #vhdl #tmds #icepizero

Icepi Zero Bot @[email protected]

2026-06-11

@[email protected] asked

Success!

UART Output

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Hello Fediverse on UART!
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Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
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Hello Fediverse on UART!
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Hello Fediverse on UART!
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Hello Fediverse on UART!
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Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
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Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
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Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
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Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
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Hello Fediverse on UART!
Hello Fediverse on UART!
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Hello Fediverse on UART!
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Hello Fediverse on UART!
Hello Fediverse on UART!
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Hello Fediverse on UART!
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Hello Fediverse on UART!
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Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
He

UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1178242884.9%TRELLIS_FF176242880.7%TRELLIS_IO111975.6%
TimingClockAchievedConstraint$glbnet$clkp40.37 MHz25 MHz$glbnet$clkt285.63 MHz250 MHz
Code

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1');

        uart_data : out std_logic_vector(7 downto 0) := (others => '0');
        uart_ready : in std_logic;
        uart_valid : out std_logic := '0'
    );
end my_code;

architecture rtl of my_code is
    alias red   : std_logic_vector(7 downto 0) is background_color(23 downto 16);
    alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8);
    alias blue  : std_logic_vector(7 downto 0) is background_color(7 downto 0);

    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant example_text : string := "Hello Fediverse! <3";
    constant example_text_row : integer := 15;
    constant example_text_col : integer := 15;

    constant uart_text : string := "Hello Fediverse on UART!" & LF;
begin
    char <= character'pos(example_text(col + 1 - example_text_col))
        when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0;

    red   <= std_logic_vector(to_unsigned(col*4, 8)) xor std_logic_vector(resize(frame_counter, 8));
    green <= std_logic_vector(to_unsigned(py, 8)) xor std_logic_vector(to_unsigned(px, 8));
    blue  <= std_logic_vector(resize(frame_counter, 8));

    foreground_color <= (others => '1');

    process(clk)
        variable old_vsync : std_logic := '0';

        variable uart_counter : integer range uart_text'range := 1;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                frame_counter <= frame_counter + 1;
            end if;
            old_vsync := vsync;

            uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8));
            uart_valid <= '1';
            if uart_ready = '1' and uart_valid = '1' then
                if uart_counter < uart_text'length then
                    uart_counter := uart_counter + 1;
                else
                    uart_counter := 1;
                end if;
            end if;
        end if;
    end process;
end architecture;

#FPGA #Icepi-Zero #HDL #VHDL

#fpga #icepizero #hdl #vhdl

Icepi Zero Bot @[email protected]

2026-06-11

@[email protected] asked

Success!

UART Output

UtilizationCellUsedAvailableUsageDCCA2563.6%DTR11100.0%EHXPLLL1250.0%TRELLIS_COMB1238242885.1%TRELLIS_FF158242880.7%TRELLIS_IO111975.6%
TimingClockAchievedConstraint$glbnet$clkp40.71 MHz25 MHz$glbnet$clkt319.69 MHz250 MHz
Code

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1');

        uart_data : out std_logic_vector(7 downto 0) := (others => '0');
        uart_ready : in std_logic;
        uart_valid : out std_logic := '0'
    );
end my_code;

architecture rtl of my_code is
    alias red   : std_logic_vector(7 downto 0) is background_color(23 downto 16);
    alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8);
    alias blue  : std_logic_vector(7 downto 0) is background_color(7 downto 0);

    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    signal example_text : string(1 to 13) := "temp = ???? C";
    constant example_text_row : integer := 15;
    constant example_text_col : integer := 15;

    type temperature_map_t is array (0 to 63) of string(1 to 4);
    constant temperature_map : temperature_map_t := (
        0 =>  " -58",
        1 =>  " -56",
        2 =>  " -54",
        3 =>  " -52",
        4 =>  " -45",
        5 =>  " -44",
        6 =>  " -43",
        7 =>  " -42",
        8 =>  " -41",
        9 =>  " -40",
        10 => "- 39",
        11 => "- 38",
        12 => "- 37",
        13 => "- 36",
        14 => "- 30",
        15 => "- 20",
        16 => "- 10",
        17 => "-  4",
        18 => "   0",
        19 => "+  4",
        20 => "+ 10",
        21 => "+ 21",
        22 => "+ 22",
        23 => "+ 23",
        24 => "+ 24",
        25 => "+ 25",
        26 => "+ 26",
        27 => "+ 27",
        28 => "+ 28",
        29 => "+ 29",
        30 => "+ 40",
        31 => "+ 50",
        32 => "+ 60",
        33 => "+ 70",
        34 => "+ 76",
        35 => "+ 80",
        36 => "+ 81",
        37 => "+ 82",
        38 => "+ 83",
        39 => "+ 84",
        40 => "+ 85",
        41 => "+ 86",
        42 => "+ 87",
        43 => "+ 88",
        44 => "+ 89",
        45 => "+ 95",
        46 => "+ 96",
        47 => "+ 97",
        48 => "+ 98",
        49 => "+ 99",
        50 => "+100",
        51 => "+101",
        52 => "+102",
        53 => "+103",
        54 => "+104",
        55 => "+105",
        56 => "+106",
        57 => "+107",
        58 => "+108",
        59 => "+116",
        60 => "+120",
        61 => "+124",
        62 => "+128",
        63 => "+132"
    );

    component DTR is
        port (
            STARTPULSE : in std_logic;
            DTROUT7 : out std_logic;
            DTROUT6 : out std_logic;
            DTROUT5 : out std_logic;
            DTROUT4 : out std_logic;
            DTROUT3 : out std_logic;
            DTROUT2 : out std_logic;
            DTROUT1 : out std_logic;
            DTROUT0 : out std_logic
        );
    end component;
    signal temp : unsigned(5 downto 0) := (others => '0');
    signal startpulse : std_logic := '0';
begin
    char <= character'pos(example_text(col + 1 - example_text_col))
        when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0;

    red   <= std_logic_vector(to_unsigned(col*4, 8));
    green <= std_logic_vector(to_unsigned(py, 8));
    blue  <= std_logic_vector(resize(frame_counter, 8));

    foreground_color <= (others => '1');

    dtr_inst: DTR
        port map (
            STARTPULSE => startpulse,
            DTROUT7 => open,
            DTROUT6 => open,
            DTROUT5 => temp(5),
            DTROUT4 => temp(4),
            DTROUT3 => temp(3),
            DTROUT2 => temp(2),
            DTROUT1 => temp(1),
            DTROUT0 => temp(0)
        );
    example_text(8 to 11) <= temperature_map(to_integer(temp));

    process(clk)
        variable old_vsync : std_logic := '0';
    begin
        if rising_edge(clk) then
            startpulse <= '0';
            if vsync = '0' and old_vsync = '1' then
                frame_counter <= frame_counter + 1;
                startpulse <= '1';
            end if;
            old_vsync := vsync;
        end if;
    end process;
end architecture;

#FPGA #Icepi-Zero #HDL #VHDL

#fpga #icepizero #hdl #vhdl

Icepi Zero Bot @[email protected]

2026-06-11

@[email protected] asked

Success!

UART Output

UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%MULT18X18D2287.1%TRELLIS_COMB29372428812.1%TRELLIS_FF160242880.7%TRELLIS_IO111975.6%
TimingClockAchievedConstraint$glbnet$clkp30.03 MHz25 MHz$glbnet$clkt341.41 MHz250 MHz
Code

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1');

        uart_data : out std_logic_vector(7 downto 0) := (others => '0');
        uart_ready : in std_logic;
        uart_valid : out std_logic := '0'
    );
end my_code;

architecture rtl of my_code is
    constant IMAGE_WIDTH : integer := 32;
    constant IMAGE_HEIGHT : integer := 25;

    type image_type is array (IMAGE_HEIGHT*IMAGE_WIDTH*12-1 downto 0) of std_logic;
    constant image : image_type := x"00000000000000000000000000000000000000000000000123400000000000111200000000000000000000000000000000000000000000000000000000000000000000000000044645700000000022344700000000000000000000000000000000000000000000000000000000000000000000000000056845700100000033556800100000000000000000000000000000000000000000000000000000000000000000000000145744611100000034555800000000000000000000000000000000000000000000000000000000000000000000000000033533522423422444633500011075364300000000000000000000000000000000000000000000000000000000000000012334568979b457345123000964eb7da73211100000000000000000000000000000000000000000000000000000000003448abaddadd8ab79a578211c86fa7fa7c86c867430000000000000000000000000000000000000000000000000000005788bcaddadd8ab8ab689777eddebae96f96f9696400000000000000000000000000000000000000000000000011122289a89a9cdadd9aaabb79a777cccca9d85d85b643100000000000000000000000000000000000000000000002217657659aaabcacdaddbcdbcd7ab456888866754532210000000000000000000000000000000000000000000000000332765765789acdadeaddadd9cd58923444522200000011133333300000000000000000000000000000000000000000011154377688978a9bcacd9cc7ac7ad347000000433999bbbddcaaa0000000000000000000000000000000000000000001223443452235679bcabc9bc9ab68b46a124444bbbeddeedddd7770000000000000000000000000000000000000005679bd7ac78b769678cdddeecddacc7ae47a567888cccdddccc8881110000000000001110000000000003333331111115668ab69b89c88a668bcddeecee9bc67b56a99bcccaaa999555111111000000555aaacccbbb333222777eeeeeeccccdddddbbb445abceefeffeeeeeeeeedeedeeddebbcbbcdddeeebbbbbbcccbbb666dddeffdeffffdddccceeedefbdfeffdefbeffff999cccdefadfbefcefdefcefbefbefdeeeefadfbefffffffcefeffcccfffadf4cfdeffffdefeffbdf4cfadf3cf3cfbefeeedddbdf3bf3cf4cf6cf3cf5cf4cf7cfcef4cf4cfdefdff5cfbefdddcccdef3cf9dfdef4cfbdf9df4cf7cf3cf4cf6cfefffffadf4cfadfcef9df4cfdefadf2bf9df4cf3cf8cfdef4cfcefccd888fff9df3bf9cf3af7bf6af5af5af7bfadf3afadffff8cf2bf3bfcefadf3bfadf8cf3bfbdf4bf9cf5bf7bf3afdefbbb444ddddef48f37f47f37f26f58f37f57fbcf89f47fcdf79f79fbdfeffbcf38f6af49f38fabf48fbcf9af27f37feefaaa000aaafff79f37fbcf57f37f8af37f68fccfddf57f89f58f9bfffffffbcf37fddfddf47f57f47fbcfddf37f47ffff999000344eeeddfbcfeffddfcdfdefabfeefffffffdefeefddfeefddeccdddf9afeeffffddfddfddfeeffffbcfbcffff77800000099aeeeeeeddeddeddeeeeeefdee89abbcddeccdddddde99a99aeeffffeefdddeeeddeddeccdcddeeefffddd45600000022456866845745745755767956822423544723534645723433477978a679446567457446346346568679558112";

    constant SPEED : integer := 8;

    signal position_x : integer range -SPEED to WIDTH + SPEED := 0;
    signal position_y : integer range -SPEED to HEIGHT + SPEED := 0;

    signal random_bit : std_logic := '0';
    signal color : std_logic_vector(23 downto 0) := x"FFFFFF";

    component OSCG is
        generic (
            DIV : integer := 128
        );
        port (
            OSC : out std_logic
        );
    end component;

    signal pos : integer range 0 to IMAGE_HEIGHT*IMAGE_WIDTH*12;
    signal r, g, b : std_logic_vector(3 downto 0);
begin
    char <= 0;

    pos <= IMAGE_HEIGHT*IMAGE_WIDTH*12 - 1 - 12*(py - position_y)*(px - position_x);
    r <= image(pos) & image(pos - 1) & image(pos - 2) & image(pos - 3);
    g <= image(pos - 4) & image(pos - 5) & image(pos - 6) & image(pos - 7);
    b <= image(pos - 8) & image(pos - 9) & image(pos - 10) & image(pos - 11);

    background_color <= r & r & g & g & b & b
        when
            px >= position_x and px < position_x + IMAGE_WIDTH and
            py >= position_y and py < position_y + IMAGE_HEIGHT
        else x"000000";
    foreground_color <= (others => '1');

    rng : OSCG port map (
        OSC => random_bit
    );

    process(clk)
        variable old_vsync : std_logic := '0';
        variable speed_x : integer range -SPEED to SPEED := SPEED;
        variable speed_y : integer range -SPEED to SPEED := SPEED;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                if position_x + speed_x + IMAGE_WIDTH >= WIDTH then
                    speed_x := -SPEED;
                    position_x <= WIDTH - IMAGE_WIDTH - 1;

                    color <= color(22 downto 0) & random_bit;
                elsif position_x + speed_x < 0 then
                    speed_x := SPEED;
                    position_x <= 0;

                    color <= color(22 downto 0) & random_bit;
                else
                    position_x <= position_x + speed_x;
                end if;

                if position_y + speed_y + IMAGE_HEIGHT >= HEIGHT then
                    speed_y := -SPEED;
                    position_y <= HEIGHT - IMAGE_HEIGHT - 1;

                    color <= color(22 downto 0) & random_bit;
                elsif position_y + speed_y < 0 then
                    speed_y := SPEED;
                    position_y <= 0;

                    color <= color(22 downto 0) & random_bit;
                else
                    position_y <= position_y + speed_y;
                end if;
            end if;
            old_vsync := vsync;
        end if;
    end process;
end architecture;

#FPGA #Icepi-Zero #HDL #VHDL

#fpga #icepizero #hdl #vhdl

Icepi Zero Bot @[email protected]

2026-06-11

@[email protected] asked

Success!

UART Output

UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB417242881.7%TRELLIS_FF128242880.5%TRELLIS_IO111975.6%
TimingClockAchievedConstraint$glbnet$clkp130.92 MHz25 MHz$glbnet$clkt374.53 MHz250 MHz
Code

#[no_mangle(all)]
entity my_code(
    clk: clock,
    rst: bool,
    px: int<32>,
    py: int<32>,
    hsync: bool,
    vsync: bool,
    col: int<32>,
    row: int<32>,
    char: inv &int<32>,
    foreground_color: inv &uint<24>,
    background_color: inv &uint<24>,
    uart_data: inv &uint<8>,
    uart_ready: bool,
    uart_valid: inv bool,
) {
    set char = &87;
    set foreground_color = &0xFFFFFFu24;
    set background_color = &0xFF7AFFu24;
    set uart_data = &0x00;
    set uart_valid = &false;
}

#FPGA #Icepi-Zero #HDL #Spade

#fpga #icepizero #hdl #spade

Icepi Zero Bot @[email protected]

2026-06-06

@[email protected]

@[email protected] asked

Success!

UART Output

... [TRUNCATED] ...
T!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
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Hello Fediverse on UART!
Hello Fediverse on UART!
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Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
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Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
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Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
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Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
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Hello Fediverse on UAR

UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1171242884.8%TRELLIS_FF177242880.7%TRELLIS_IO111975.6%
TimingClockAchievedConstraint$glbnet$clkp39.04 MHz25 MHz$glbnet$clkt345.18 MHz250 MHz
Code

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1');

        uart_data : out std_logic_vector(7 downto 0) := (others => '0');
        uart_ready : in std_logic;
        uart_valid : out std_logic := '0'
    );
end my_code;

architecture rtl of my_code is
    alias red   : std_logic_vector(7 downto 0) is background_color(23 downto 16);
    alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8);
    alias blue  : std_logic_vector(7 downto 0) is background_color(7 downto 0);

    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant example_text : string := "Hello Fediverse! <3";
    constant example_text_row : integer := 15;
    constant example_text_col : integer := 15;

    constant uart_text : string := "Hello Fediverse on UART!" & LF;
begin
    char <= character'pos(example_text(col + 1 - example_text_col))
        when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0;

    red   <= std_logic_vector(to_unsigned(col*4, 8));
    green <= std_logic_vector(to_unsigned(py, 8));
    blue  <= std_logic_vector(resize(frame_counter, 8));

    foreground_color <= (others => '1');

    process(clk)
        variable old_vsync : std_logic := '0';

        variable uart_counter : integer range uart_text'range := 1;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                frame_counter <= frame_counter + 1;
            end if;
            old_vsync := vsync;

            uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8));
            uart_valid <= '1';
            if uart_ready = '1' and uart_valid = '1' then
                if uart_counter < uart_text'length then
                    uart_counter := uart_counter + 1;
                else
                    uart_counter := 1;
                end if;
            end if;
        end if;
    end process;
end architecture;

#FPGA #Icepi-Zero #HDL #VHDL

#fpga #icepizero #hdl #vhdl

Icepi Zero Bot @[email protected]

2026-05-24

@[email protected]

@[email protected] asked

Success!

UART Output

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UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1171242884.8%TRELLIS_FF177242880.7%TRELLIS_IO111975.6%
TimingClockAchievedConstraint$glbnet$clkp39.04 MHz25 MHz$glbnet$clkt345.18 MHz250 MHz
Code

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1');

        uart_data : out std_logic_vector(7 downto 0) := (others => '0');
        uart_ready : in std_logic;
        uart_valid : out std_logic := '0'
    );
end my_code;

architecture rtl of my_code is
    alias red   : std_logic_vector(7 downto 0) is background_color(23 downto 16);
    alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8);
    alias blue  : std_logic_vector(7 downto 0) is background_color(7 downto 0);

    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant example_text : string := "Hello Fediverse! <3";
    constant example_text_row : integer := 15;
    constant example_text_col : integer := 15;

    constant uart_text : string := "Hello Fediverse on UART!" & LF;
begin
    char <= character'pos(example_text(col + 1 - example_text_col))
        when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0;

    red   <= std_logic_vector(to_unsigned(col*4, 8));
    green <= std_logic_vector(to_unsigned(py, 8));
    blue  <= std_logic_vector(resize(frame_counter, 8));

    foreground_color <= (others => '1');

    process(clk)
        variable old_vsync : std_logic := '0';

        variable uart_counter : integer range uart_text'range := 1;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                frame_counter <= frame_counter + 1;
            end if;
            old_vsync := vsync;

            uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8));
            uart_valid <= '1';
            if uart_ready = '1' and uart_valid = '1' then
                if uart_counter < uart_text'length then
                    uart_counter := uart_counter + 1;
                else
                    uart_counter := 1;
                end if;
            end if;
        end if;
    end process;
end architecture;

#FPGA #Icepi-Zero #HDL #VHDL

#fpga #icepizero #hdl #vhdl

Icepi Zero Bot @[email protected]

2026-05-23

@[email protected]

@[email protected] asked

Success!

UART Output

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UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1171242884.8%TRELLIS_FF177242880.7%TRELLIS_IO111975.6%
TimingClockAchievedConstraint$glbnet$clkp39.04 MHz25 MHz$glbnet$clkt345.18 MHz250 MHz
Code

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1');

        uart_data : out std_logic_vector(7 downto 0) := (others => '0');
        uart_ready : in std_logic;
        uart_valid : out std_logic := '0'
    );
end my_code;

architecture rtl of my_code is
    alias red   : std_logic_vector(7 downto 0) is background_color(23 downto 16);
    alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8);
    alias blue  : std_logic_vector(7 downto 0) is background_color(7 downto 0);

    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant example_text : string := "Hello Fediverse! <3";
    constant example_text_row : integer := 15;
    constant example_text_col : integer := 15;

    constant uart_text : string := "Hello Fediverse on UART!" & LF;
begin
    char <= character'pos(example_text(col + 1 - example_text_col))
        when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0;

    red   <= std_logic_vector(to_unsigned(col*4, 8));
    green <= std_logic_vector(to_unsigned(py, 8));
    blue  <= std_logic_vector(resize(frame_counter, 8));

    foreground_color <= (others => '1');

    process(clk)
        variable old_vsync : std_logic := '0';

        variable uart_counter : integer range uart_text'range := 1;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                frame_counter <= frame_counter + 1;
            end if;
            old_vsync := vsync;

            uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8));
            uart_valid <= '1';
            if uart_ready = '1' and uart_valid = '1' then
                if uart_counter < uart_text'length then
                    uart_counter := uart_counter + 1;
                else
                    uart_counter := 1;
                end if;
            end if;
        end if;
    end process;
end architecture;

#FPGA #Icepi-Zero #HDL #VHDL

#fpga #icepizero #hdl #vhdl

Icepi Zero Bot @[email protected]

2026-05-22

@[email protected]

@[email protected] asked

Success!

UART Output

... [TRUNCATED] ...
iverse on UART!
Hello Fediverse on UART!
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Hello Fed

UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1171242884.8%TRELLIS_FF177242880.7%TRELLIS_IO111975.6%
TimingClockAchievedConstraint$glbnet$clkp39.04 MHz25 MHz$glbnet$clkt345.18 MHz250 MHz
Code

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1');

        uart_data : out std_logic_vector(7 downto 0) := (others => '0');
        uart_ready : in std_logic;
        uart_valid : out std_logic := '0'
    );
end my_code;

architecture rtl of my_code is
    alias red   : std_logic_vector(7 downto 0) is background_color(23 downto 16);
    alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8);
    alias blue  : std_logic_vector(7 downto 0) is background_color(7 downto 0);

    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant example_text : string := "Hello Fediverse! <3";
    constant example_text_row : integer := 15;
    constant example_text_col : integer := 15;

    constant uart_text : string := "Hello Fediverse on UART!" & LF;
begin
    char <= character'pos(example_text(col + 1 - example_text_col))
        when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0;

    red   <= std_logic_vector(to_unsigned(col*4, 8));
    green <= std_logic_vector(to_unsigned(py, 8));
    blue  <= std_logic_vector(resize(frame_counter, 8));

    foreground_color <= (others => '1');

    process(clk)
        variable old_vsync : std_logic := '0';

        variable uart_counter : integer range uart_text'range := 1;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                frame_counter <= frame_counter + 1;
            end if;
            old_vsync := vsync;

            uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8));
            uart_valid <= '1';
            if uart_ready = '1' and uart_valid = '1' then
                if uart_counter < uart_text'length then
                    uart_counter := uart_counter + 1;
                else
                    uart_counter := 1;
                end if;
            end if;
        end if;
    end process;
end architecture;

#FPGA #Icepi-Zero #HDL #VHDL

#fpga #icepizero #hdl #vhdl

Icepi Zero Bot @[email protected]

2026-05-22

@[email protected]

@[email protected] asked

Success!

UART Output

... [TRUNCATED] ...

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UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB696242882.9%TRELLIS_FF150242880.6%TRELLIS_IO111975.6%
TimingClockAchievedConstraint$glbnet$clkp84.79 MHz25 MHz$glbnet$clkt335.68 MHz250 MHz
Code

module my_code #(
    parameter int WIDTH = 640,
    parameter int HEIGHT = 480,
    parameter int CONSOLE_COLUMNS = WIDTH / 8,
    parameter int CONSOLE_ROWS = HEIGHT / 8
)(
    input  logic clk,
    input  logic rst,

    input  int px,
    input  int py,
    input  logic hsync,
    input  logic vsync,

    input  int col,
    input  int row,

    output int char,
    output logic [23:0] foreground_color,
    output logic [23:0] background_color,

    output logic [7:0] uart_data,
    input  logic uart_ready,
    output logic uart_valid
);
    // NO inline initializations to avoid TOK_CONSTVAL parser errors
    logic [31:0] frame_counter;
    logic old_vsync;
    logic [6:0] msg_idx;
    logic sending;

    // Registers to lock the UART VU meter levels across a single frame
    logic [4:0] l_samp;
    logic [4:0] r_samp;

    // Combinational logic variables
    logic [7:0] x_mod1;
    logic [7:0] x_mod2;
    logic [4:0] tri1;
    logic [4:0] tri2;
    logic [5:0] total_h;
    logic [5:0] dot_h;
    logic [5:0] inv_row;

    logic [7:0] u_mod1;
    logic [7:0] u_mod2;
    logic [4:0] u_tri1;
    logic [4:0] u_tri2;

    always_comb begin
        // ---------------------------------------------------------
        // 1. VIDEO: Hardware Spectrum Analyzer
        // ---------------------------------------------------------

        // Generate two counter-propagating waves of different speeds.
        // Bitwise AND with 3F limits the wave period to 64 columns.
        x_mod1 = (col[7:0] + frame_counter[7:0]) & 8'h3F;
        x_mod2 = (col[7:0] - frame_counter[8:1]) & 8'h3F;

        // Turn the ramping counters into absolute triangle waves (0 to 31)
        tri1 = x_mod1[5] ? (~x_mod1[4:0]) : x_mod1[4:0];
        tri2 = x_mod2[5] ? (~x_mod2[4:0]) : x_mod2[4:0];

        // Sum the waves to get a morphing interference pattern (0 to 62 max height)
        total_h = {1'b0, tri1} + {1'b0, tri2};

        // Calculate the position of the floating "peak" dot
        dot_h = total_h + 6'd2;

        // Invert the row coordinate so row 0 is the bottom of the screen
        inv_row = 6'd59 - row[5:0];

        // Render the equalizer bars
        if (col[0] == 1'b1) begin
            // Leave a 1-character gap between every frequency band
            char = 8'h20; // ' '
            foreground_color = 24'd0;
            background_color = 24'd0;
        end else if (inv_row < total_h) begin
            // Draw the main LED bar
            char = 8'h3D; // '=' character gives it a segmented LED look
            background_color = 24'd0;

            // Heatmap color gradient based on height
            if (inv_row < 6'd15)
                foreground_color = 24'h00FF00; // Green
            else if (inv_row < 6'd30)
                foreground_color = 24'hFFFF00; // Yellow
            else if (inv_row < 6'd45)
                foreground_color = 24'hFF8000; // Orange
            else
                foreground_color = 24'hFF0000; // Red

        end else if (inv_row == dot_h) begin
            // Draw the floating peak indicator
            char = 8'h2D; // '-'
            foreground_color = 24'hFFFFFF; // White
            background_color = 24'd0;
        end else begin
            // Empty space above the bar
            char = 8'h20; // ' '
            foreground_color = 24'd0;
            background_color = 24'd0;
        end

        // ---------------------------------------------------------
        // 2. UART: Stereo VU Meter Sampling
        // ---------------------------------------------------------

        // Sample the triangle waves at the center of the screen independently of the 
        // video generation logic, so the UART doesn't change mid-frame.
        u_mod1 = (frame_counter[7:0]) & 8'h3F;
        u_mod2 = (-frame_counter[8:1]) & 8'h3F;
        u_tri1 = u_mod1[5] ? (~u_mod1[4:0]) : u_mod1[4:0];
        u_tri2 = u_mod2[5] ? (~u_mod2[4:0]) : u_mod2[4:0];

        // ---------------------------------------------------------
        // 3. UART: ASCII Output FSM
        // ---------------------------------------------------------

        if (msg_idx == 7'd0)       uart_data = 8'h5B; // '['
        else if (msg_idx == 7'd1)  uart_data = 8'h4C; // 'L'
        else if (msg_idx == 7'd2)  uart_data = 8'h5D; // ']'
        else if (msg_idx == 7'd3)  uart_data = 8'h20; // ' '
        else if (msg_idx == 7'd4)  uart_data = 8'h7C; // '|'
        else if (msg_idx >= 7'd5 && msg_idx <= 7'd36) begin
            // 32-character Left channel bar
            if ((msg_idx - 7'd5) < {2'b00, l_samp}) 
                uart_data = 8'h23; // '#'
            else 
                uart_data = 8'h2D; // '-'
        end
        else if (msg_idx == 7'd37) uart_data = 8'h7C; // '|'
        else if (msg_idx == 7'd38) uart_data = 8'h20; // ' '
        else if (msg_idx == 7'd39) uart_data = 8'h5B; // '['
        else if (msg_idx == 7'd40) uart_data = 8'h52; // 'R'
        else if (msg_idx == 7'd41) uart_data = 8'h5D; // ']'
        else if (msg_idx == 7'd42) uart_data = 8'h20; // ' '
        else if (msg_idx == 7'd43) uart_data = 8'h7C; // '|'
        else if (msg_idx >= 7'd44 && msg_idx <= 7'd75) begin
            // 32-character Right channel bar
            if ((msg_idx - 7'd44) < {2'b00, r_samp}) 
                uart_data = 8'h23; // '#'
            else 
                uart_data = 8'h2D; // '-'
        end
        else if (msg_idx == 7'd76) uart_data = 8'h7C; // '|'
        else if (msg_idx == 7'd77) uart_data = 8'h0D; // '\r'
        else if (msg_idx == 7'd78) uart_data = 8'h0A; // '\n'
        else uart_data = 8'h20; // Space
    end

    // --- SEQUENTIAL LOGIC ---
    always_ff @(posedge clk) begin
        if (rst) begin
            frame_counter <= 0;
            old_vsync <= 0;
            msg_idx <= 0;
            uart_valid <= 1'b0;
            sending <= 1'b0;
            l_samp <= 0;
            r_samp <= 0;
        end else begin
            // Track frames on the falling edge of vsync
            if (vsync == 1'b0 && old_vsync == 1'b1) begin
                frame_counter <= frame_counter + 1;

                // Latch the VU meter samples so they stay stable during UART transmission
                l_samp <= u_tri1;
                r_samp <= u_tri2;

                // Trigger one line of UART output per frame
                sending <= 1'b1; 
            end
            old_vsync <= vsync;

            // UART Handshaking FSM
            if (sending) begin
                uart_valid <= 1'b1;

                if (uart_ready && uart_valid) begin
                    if (msg_idx == 7'd79) begin
                        msg_idx <= 0;
                        uart_valid <= 1'b0;
                        sending <= 1'b0; // Wait for the next vsync frame
                    end else begin
                        msg_idx <= msg_idx + 1;
                    end
                end
            end else begin
                uart_valid <= 1'b0;
            end
        end
    end
endmodule

#FPGA #Icepi-Zero #HDL #SystemVerilog

#fpga #icepizero #hdl #systemverilog

Icepi Zero Bot @[email protected]

2026-05-22

@[email protected]

@[email protected] asked

Success!

UART Output

** FPGA PLASMA DEMO ** Frame=00000131!
\0\0** FPGA PLASMA DEMO ** Frame=0000013C!
\0\0** FPGA PLASMA DEMO ** Frame=00000146!
\0\0** FPGA PLASMA DEMO ** Frame=00000150!
\0\0** FPGA PLASMA DEMO ** Frame=0000015A!
\0\0** FPGA PLASMA DEMO ** Frame=00000164!
\0\0** FPGA PLASMA DEMO ** Frame=0000016F!
\0\0** FPGA PLASMA DEMO ** Frame=00000179!
\0\0** FPGA PLASMA DEMO ** Frame=00000183!
\0\0** FPGA PLASMA DEMO ** Frame=0000018D!
\0\0** FPGA PLASMA DEMO ** Frame=00000197!
\0\0** FPGA PLASMA DEMO ** Frame=000001A2!
\0\0** FPGA PLASMA DEMO ** Frame=000001AC!
\0\0** FPGA PLASMA DEMO ** Frame=000001B6!
\0\0** FPGA PLASMA DEMO ** Frame=000001C0!
\0\0** FPGA PLASMA DEMO ** Frame=000001CA!
\0\0** FPGA PLASMA DEMO ** Frame=000001D5!
\0\0** FPGA PLASMA DEMO ** Frame=000001DF!
\0\0** FPGA PLASMA DEMO ** Frame=000001E9!
\0\0** FPGA PLASMA DEMO ** Frame=000001F3!
\0\0** FPGA PLASMA DEMO ** Frame=000001FD!
\0\0** FPGA PLASMA DEMO ** Frame=00000208!
\0\0** FPGA PLASMA DEMO ** Frame=00000212!
\0\0** FPGA PLASMA DEMO ** Frame=0000021C!
\0\0** FPGA PLASMA DEMO ** Frame=00000226!
\0\0** FPGA PLASMA DEMO ** Frame=00000230!
\0\0** FPGA PLASMA DEMO ** Frame=0000023B!
\0\0** FPGA PLASMA DEMO ** Frame=00000245!
\0\0** FPGA PLASMA DEMO ** Frame=0000024F!
\0\0** FPGA PLASMA DEMO ** Frame=00000259!
\0\0** FPGA PLASMA DEMO ** Frame=00000263!
\0\0** FPGA PLASMA DEMO ** Frame=0000026E!
\0\0** FPGA PLASMA DEMO ** Frame=00000278!
\0\0** FPGA PLASMA DEMO ** Frame=00000282!
\0\0** FPGA PLASMA DEMO ** Frame=0000028C!
\0\0** FPGA PLASMA DEMO ** Frame=00000296!
\0\0** FPGA PLASMA DEMO ** Frame=000002A1!
\0\0** FPGA PLASMA DEMO ** Frame=000002AB!
\0\0** FPGA PLASMA DEMO ** Frame=000002B5!
\0\0** FPGA PLASMA DEMO ** Frame=000002BF!
\0\0** FPGA PLASMA DEMO ** Frame=000002C9!
\0\0** FPGA PLASMA DEMO ** Frame=000002D4!
\0\0** FPGA PLASMA DEMO ** Frame=000002DE!
\0\0** FPGA PLASMA DEMO ** Frame=000002E8!
\0\0** FPGA PLASMA DEMO ** Frame=000002F2!
\0\0** FPGA PLASMA DEMO ** Frame=000002FC!
\0\0** FPGA PLASMA DEMO ** Frame=00000307!
\0\0** FPGA PLASMA DEMO ** Frame=00000311!
\0\0** FPGA PLASMA DEMO ** Frame=0000031B!
\0\0** FPGA PLASMA DEMO ** Frame=00000325!
\0\0** FPGA PLASMA DEMO ** Frame=0000032F!
\0\0** FPGA PLASMA DEMO ** Frame=00000339!
\0\0** FPGA PLASMA DEMO ** Frame=00000344!
\0\0** FPGA PLASMA DEMO ** Frame=0000034E!
\0\0** FPGA PLASMA DEMO ** Frame=00000358!
\0\0** FPGA PLASMA DEMO ** Frame=00000362!
\0\0** FPGA PLASMA DEMO ** Frame=0000036C!
\0\0** FPGA PLASMA DEMO ** Frame=00000377!
\0\0** FPGA PLASMA DEMO ** Frame=00000381!
\0\0** FPGA PLASMA DEMO ** Frame=0000038B!
\0\0** FPGA PLASMA DEMO ** Frame=00000395!
\0\0** FPGA PLASMA DEMO ** Frame=0000039F!
\0\0** FPGA PLASMA DEMO ** Frame=000003AA!
\0\0** FPGA PLASMA DEMO ** Frame=000003B4!
\0\0** FPGA PLASMA DEMO ** Frame=000003BE!
\0\0** FPGA PLASMA DEMO ** Frame=000003C8!
\0\0** FPGA PLASMA DEMO ** Frame=000003D2!
\0\0** FPGA PLASMA DEMO ** Frame=000003DD!
\0\0** FPGA PLASMA DEMO ** Frame=000003E7!
\0\0** FPGA PLASMA DEMO ** Frame=000003F1!
\0\0** FPGA PLASMA DEMO ** Frame=000003FB!
\0\0** FPGA PLASMA DEMO ** Frame=00000405!
\0\0** FPGA PLASMA DEMO ** Frame=00000410!
\0\0** FPGA PLASMA DEMO ** Frame=0000041A!
\0\0** FPGA PLASMA DEMO ** Frame=00000424!
\0\0** FPGA PLASMA DEMO ** Frame=0000042E!
\0\0** FPGA PLASMA DEMO ** Frame=00000438!
\0\0** FPGA PLASMA DEMO ** Frame=00000443!
\0\0** FPGA PLASMA DEMO ** Frame=0000044D!
\0\0** FPGA PLASMA DEMO ** Frame=00000457!
\0\0** FPGA PLASMA DEMO ** Frame=00000461!
\0\0** FPGA PLASMA DEMO ** Frame=0000046B!
\0\0** FPGA PLASMA DEMO ** Frame=00000476!
\0\0** FPGA PLASMA DEMO ** Frame=00000480!
\0\0** FPGA PLASMA DEMO ** Frame=0000048A!
\0\0** FPGA PLASMA DEMO ** Frame=00000494!
\0\0** FPGA PLASMA DEMO ** Frame=0000049E!
\0\0** FPGA PLASMA DEMO ** Frame=000004A9!
\0\0** FPGA PLASMA DEMO ** Frame=000004B3!
\0\0** FPGA PLASMA DEMO ** Frame=000004BD!
\0\0** FPGA PLASMA DEMO ** Frame=000004C7!
\0\0** FPGA PLASMA DEMO ** Frame=000004D1!
\0\0** FPGA PLASMA DEMO ** Frame=000004DC!
\0\0** FPGA PLASMA DEMO ** Frame=000004E6!
\0\0** FPGA PLASMA DEMO ** Frame=000004F0!
\0\0** FPGA PLASMA DEMO ** Frame=000004FA!
\0\0** FPGA PLASMA DEMO ** Frame=00000504!
\0\0** FPGA PLASMA DEMO ** Frame=0000050F!
\0\0** FPGA PLASMA DEMO ** Frame=00000519!
\0\0** FPGA PLASMA DEMO ** Frame=00000523!
\0\0** FPGA PLASMA DEMO ** Frame=0000052D!
\0\0** FPGA PLASMA DEMO ** Frame=00000537!
\0\0** FPGA PLASMA DEMO ** Frame=00000542!
\0\0** FPGA PLASMA DEMO ** Frame=0000054C!
\0\0** FPGA PLASMA DEMO ** Frame=00000556!
\0\0** FPGA PLASMA DEMO ** Frame=00000560!
\0\0** FPGA PLASMA DEMO ** Frame=0000056A!
\0\0** FPGA PLASMA DEMO ** Frame=00000575!
\0\0** FPGA PLASMA DEMO ** Frame=0000057F!
\0\0** FPGA PLASMA DEMO ** Frame=00000589!
\0\0** FPGA PLASMA DEMO ** Frame=00000593!
\0\0** FPGA PLASMA DEMO ** Frame=0000059D!
\0\0** FPGA PLASMA DEMO ** Frame=000005A8!
\0\0** FPGA PLASMA DEMO ** Frame=000005B2!
\0\0** FPGA PLASMA DEMO ** Frame=000005BC!
\0\0** FPGA PLASMA DEMO ** Frame=000005C6!
\0\0** FPGA PLASMA DEMO ** Frame=000005D0!
\0\0** FPGA PLASMA DEMO ** Frame=000005DB!
\0\0** FPGA PLASMA DEMO ** Frame=000005E5!
\0\0** FPGA PLASMA DEMO ** Frame=000005EF!
\0\0** FPGA PLASMA DEMO ** Frame=000005F9!
\0\0** FPGA PLASMA DEMO ** Frame=00000603!
\0\0** FPGA PLASMA DEMO ** Frame=0000060E!
\0\0** FPGA PLASMA DEMO ** Frame=00000618!
\0\0** FPGA PLASMA DEMO ** Frame=00000622!
\0\0** FPGA PLASMA DEMO ** Frame=0000062C!
\0\0** FPGA PLASMA DEMO ** Frame=00000636!
\0\0** FPGA PLASMA DEMO ** Frame=00000641!
\0\0** FPGA PLASMA DEMO ** Frame=0000064B!
\0\0** FPGA PLASMA DEMO ** Frame=00000655!
\0\0** FPGA PLASMA DEMO ** Frame=0000065F!
\0\0** FPGA PLASMA DEMO ** Frame=00000669!
\0\0** FPGA PLASMA DEMO ** Frame=00000674!
\0\0** FPGA PLASMA DEMO ** Frame=0000067E!
\0\0** FPGA PLASMA DEMO ** Frame=00000688!
\0\0** FPGA PLASMA DEMO ** Frame=00000692!
\0\0** FPGA PLASMA DEMO ** Frame=0000069C!
\0\0** FPGA PLASMA DEMO ** Frame=000006A7!
\0\0** FPGA PLASMA DEMO ** Frame=000006B1!
\0\0** FPGA PLASMA DEMO ** Frame=000006BB!
\0\0** FPGA PLASMA DEMO ** Frame=000006C5!
\0\0** FPGA PLASMA DEMO ** Frame=000006CF!
\0\0** FPGA PLASMA DEMO ** Frame=000006DA!
\0\0** FPGA PLASMA DEMO ** Frame=000006E4!
\0\0** FPGA PLASMA DEMO ** Frame=000006EE!
\0\0** FPGA PLASMA DEMO ** Frame=000006F8!
\0\0** FPGA PLASMA DEMO ** Frame=00000702!
\0\0** FPGA PLASMA DEMO ** Frame=0000070D!
\0\0** FPGA PLASMA DEMO ** Frame=00000717!
\0\0** FPGA PLASMA DEMO ** Frame=00000721!
\0\0** FPGA PLASMA DEMO ** Frame=0000072B!
\0\0** FPGA PLASMA DEMO ** Frame=00000735!
\0\0** FPGA PLASMA DEMO ** Frame=00000740!
\0\0** FPGA PLASMA DEMO ** Frame=0000074A!
\0\0** FPGA PLASMA DEMO ** Frame=00000754!
\0\0** FPGA PLASMA DEMO ** Frame=0000075E!
\0\0** FPGA PLASMA DEMO ** Frame=00000768!
\0\0** FPGA PLASMA DEMO ** Frame=00000773!
\0\0** FPGA PLASMA DEMO ** Frame=0000077D!
\0\0** FPGA PLASMA DEMO ** Frame=00000787!
\0\0** FPGA PLASMA DEMO ** Frame=00000791!
\0\0** FPGA PLASMA DEMO ** Frame=0000079B!
\0\0** FPGA PLASMA DEMO ** Frame=000007A6!
\0\0** FPGA PLASMA DEMO ** Frame=000007B0!
\0\0** FPGA PLASMA DEMO ** Frame=000007BA!
\0\0** FPGA PLASMA DEMO ** Frame=000007C4!
\0\0** FPGA PLASMA DEMO ** Frame=000007CE!
\0\0** FPGA PLASMA DEMO ** Frame=000007D9!
\0\0** FPGA PLASMA DEMO ** Frame=000007E3!
\0\0** FPGA PLASMA DEMO ** Frame=000007ED!
\0\0** FPGA PLASMA DEMO ** Frame=000007F7!
\0\0** FPGA PLASMA DEMO ** Frame=00000801!
\0\0** FPGA PLASMA DEMO ** Frame=0000080C!
\0\0** FPGA PLASMA DEMO ** Frame=00000816!
\0\0** FPGA PLASMA DEMO ** Frame=00000820!
\0\0

UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1699242887.0%TRELLIS_FF253242881.0%TRELLIS_IO111975.6%
TimingClockAchievedConstraint$glbnet$clkp39.66 MHz25 MHz$glbnet$clkt320.41 MHz250 MHz
Code

module my_code #(
    parameter int WIDTH = 640,
    parameter int HEIGHT = 480,
    parameter int CONSOLE_COLUMNS = WIDTH / 8,
    parameter int CONSOLE_ROWS = HEIGHT / 8
)(
    input  logic clk,
    input  logic rst,
    input  int px,
    input  int py,
    input  logic hsync,
    input  logic vsync,
    input  int col,
    input  int row,
    output int char,
    output logic [23:0] foreground_color,
    output logic [23:0] background_color,
    output logic [7:0] uart_data,
    input  logic uart_ready,
    output logic uart_valid
);
    // -------------------------------------------------------------
    // Animated XOR-plasma background + pulsing banner + UART beacon
    // -------------------------------------------------------------
    logic [31:0] frame_counter = '0;
    logic        old_vsync     = '0;

    // ---- Plasma color computation -------------------------------
    logic [7:0] t;
    logic [7:0] r, g, b;
    logic [7:0] px8, py8;
    logic [7:0] dx, dy, dist;

    assign t   = frame_counter[7:0];
    assign px8 = px[7:0];
    assign py8 = py[7:0];
    // crude radial distance from a moving center
    assign dx  = px8 - t;
    assign dy  = py8 + t;
    assign dist = dx ^ dy;

    assign r = dist + t;
    assign g = (px8 ^ py8) + (t << 1);
    assign b = (px8 + py8) - t;

    // ---- Banner overlay -----------------------------------------
    // Console grid: 80 cols x 60 rows. Banner: row 28, "** PLASMA DEMO **"
    // 17 chars centered -> start col = (80-17)/2 = 31
    int rel_b;
    int rel_f;
    int hex_nib;
    logic [7:0] hex_char;

    assign rel_b = col - 31;
    assign rel_f = col - 34;

    // pick the hex nibble corresponding to rel_f position 5..12
    always_comb begin
        case (rel_f)
            5:  hex_nib = frame_counter[31:28];
            6:  hex_nib = frame_counter[27:24];
            7:  hex_nib = frame_counter[23:20];
            8:  hex_nib = frame_counter[19:16];
            9:  hex_nib = frame_counter[15:12];
            10: hex_nib = frame_counter[11:8];
            11: hex_nib = frame_counter[7:4];
            12: hex_nib = frame_counter[3:0];
            default: hex_nib = 8'h0;
        endcase
        if (hex_nib < 8'd10)
            hex_char = 8'h30 + hex_nib;       // '0'..'9'
        else
            hex_char = 8'h41 + (hex_nib - 8'd10); // 'A'..'F'
    end

    always_comb begin
        background_color = {r, g, b};
        foreground_color = 24'hFFFFFF;
        char = 0;

        // ---- Title banner on row 28 -----------------------------
        if (row == 28) begin
            case (rel_b)
                0:  char = "*";
                1:  char = "*";
                2:  char = " ";
                3:  char = "P";
                4:  char = "L";
                5:  char = "A";
                6:  char = "S";
                7:  char = "M";
                8:  char = "A";
                9:  char = " ";
                10: char = "D";
                11: char = "E";
                12: char = "M";
                13: char = "O";
                14: char = " ";
                15: char = "*";
                16: char = "*";
                default: char = 0;
            endcase
            if (rel_b >= 0 && rel_b < 17)
                foreground_color = {t, 8'hFF, ~t};
        end

        // ---- Frame counter line on row 30 -----------------------
        if (row == 30) begin
            case (rel_f)
                0:  char = "F";
                1:  char = "R";
                2:  char = "M";
                3:  char = ":";
                4:  char = " ";
                5:  char = hex_char;
                6:  char = hex_char;
                7:  char = hex_char;
                8:  char = hex_char;
                9:  char = hex_char;
                10: char = hex_char;
                11: char = hex_char;
                12: char = hex_char;
                default: char = 0;
            endcase
            if (rel_f >= 0 && rel_f <= 12)
                foreground_color = 24'h00FF66;
        end

        // ---- Footer "YOSYS + SV = LOVE" on row 56 ---------------
        if (row == 56) begin
            case (col - 32)
                0:  char = "Y";
                1:  char = "O";
                2:  char = "S";
                3:  char = "Y";
                4:  char = "S";
                5:  char = " ";
                6:  char = "+";
                7:  char = " ";
                8:  char = "S";
                9:  char = "V";
                10: char = " ";
                11: char = "=";
                12: char = " ";
                13: char = "L";
                14: char = "O";
                15: char = "V";
                16: char = "E";
                default: char = 0;
            endcase
            if ((col - 32) >= 0 && (col - 32) < 17)
                foreground_color = {8'hFF, t, t};
        end
    end

    // -------------------------------------------------------------
    // UART beacon: send "** FPGA PLASMA DEMO ** Frame=XXXXXXXX\r\n"
    // -------------------------------------------------------------
    // 42 bytes total
    localparam int MSG_LEN = 42;
    logic [5:0]  msg_idx     = '0;
    logic        sending     = 1'b0;
    logic [23:0] throttle    = '0;
    logic [31:0] sent_frame  = '0;

    logic [7:0] msg_byte;
    logic [3:0] nib;

    always_comb begin
        nib = 4'h0;
        case (msg_idx)
            6'd0:  msg_byte = "*";
            6'd1:  msg_byte = "*";
            6'd2:  msg_byte = " ";
            6'd3:  msg_byte = "F";
            6'd4:  msg_byte = "P";
            6'd5:  msg_byte = "G";
            6'd6:  msg_byte = "A";
            6'd7:  msg_byte = " ";
            6'd8:  msg_byte = "P";
            6'd9:  msg_byte = "L";
            6'd10: msg_byte = "A";
            6'd11: msg_byte = "S";
            6'd12: msg_byte = "M";
            6'd13: msg_byte = "A";
            6'd14: msg_byte = " ";
            6'd15: msg_byte = "D";
            6'd16: msg_byte = "E";
            6'd17: msg_byte = "M";
            6'd18: msg_byte = "O";
            6'd19: msg_byte = " ";
            6'd20: msg_byte = "*";
            6'd21: msg_byte = "*";
            6'd22: msg_byte = " ";
            6'd23: msg_byte = "F";
            6'd24: msg_byte = "r";
            6'd25: msg_byte = "a";
            6'd26: msg_byte = "m";
            6'd27: msg_byte = "e";
            6'd28: msg_byte = "=";
            6'd29: begin msg_byte = 8'h00; nib = sent_frame[31:28]; end
            6'd30: begin msg_byte = 8'h00; nib = sent_frame[27:24]; end
            6'd31: begin msg_byte = 8'h00; nib = sent_frame[23:20]; end
            6'd32: begin msg_byte = 8'h00; nib = sent_frame[19:16]; end
            6'd33: begin msg_byte = 8'h00; nib = sent_frame[15:12]; end
            6'd34: begin msg_byte = 8'h00; nib = sent_frame[11:8];  end
            6'd35: begin msg_byte = 8'h00; nib = sent_frame[7:4];   end
            6'd36: begin msg_byte = 8'h00; nib = sent_frame[3:0];   end
            6'd37: msg_byte = "!";
            6'd38: msg_byte = "\r";
            6'd39: msg_byte = "\n";
            default: msg_byte = 8'h00;
        endcase
        if (msg_idx >= 6'd29 && msg_idx <= 6'd36) begin
            if (nib < 4'd10)
                msg_byte = 8'h30 + {4'b0, nib};
            else
                msg_byte = 8'h41 + {4'b0, nib} - 8'd10;
        end

        uart_data  = msg_byte;
        uart_valid = sending && (msg_idx < MSG_LEN[5:0]);
    end

    always_ff @(posedge clk) begin
        if (vsync == 1'b0 && old_vsync == 1'b1) begin
            frame_counter <= frame_counter + 1;
        end
        old_vsync <= vsync;

        if (sending) begin
            if (uart_ready && uart_valid) begin
                if (msg_idx == MSG_LEN[5:0] - 1) begin
                    sending <= 1'b0;
                    msg_idx <= '0;
                end else begin
                    msg_idx <= msg_idx + 1;
                end
            end
        end else begin
            throttle <= throttle + 1;
            if (throttle[22] == 1'b1) begin
                sending    <= 1'b1;
                throttle   <= '0;
                sent_frame <= frame_counter;
            end
        end
    end
endmodule

#FPGA #Icepi-Zero #HDL #SystemVerilog

#fpga #icepizero #hdl #systemverilog

Icepi Zero Bot @[email protected]

2026-05-22

@[email protected]

@[email protected] asked

Success!

UART Output

... [TRUNCATED] ...
] |-----------------------*--------|
[FM: 0751] |-----------------------*--------|
[FM: 0752] |----------------------*---------|
[FM: 0753] |----------------------*---------|
[FM: 0754] |---------------------*----------|
[FM: 0755] |---------------------*----------|
[FM: 0756] |--------------------*-----------|
[FM: 0757] |--------------------*-----------|
[FM: 0758] |-------------------*------------|
[FM: 0759] |-------------------*------------|
[FM: 075A] |------------------*-------------|
[FM: 075B] |------------------*-------------|
[FM: 075C] |-----------------*--------------|
[FM: 075D] |-----------------*--------------|
[FM: 075E] |----------------*---------------|
[FM: 075F] |----------------*---------------|
[FM: 0760] |---------------*----------------|
[FM: 0761] |---------------*----------------|
[FM: 0762] |--------------*-----------------|
[FM: 0763] |--------------*-----------------|
[FM: 0764] |-------------*------------------|
[FM: 0765] |-------------*------------------|
[FM: 0766] |------------*-------------------|
[FM: 0767] |------------*-------------------|
[FM: 0768] |-----------*--------------------|
[FM: 0769] |-----------*--------------------|
[FM: 076A] |----------*---------------------|
[FM: 076B] |----------*---------------------|
[FM: 076C] |---------*----------------------|
[FM: 076D] |---------*----------------------|
[FM: 076E] |--------*-----------------------|
[FM: 076F] |--------*-----------------------|
[FM: 0770] |-------*------------------------|
[FM: 0771] |-------*------------------------|
[FM: 0772] |------*-------------------------|
[FM: 0773] |------*-------------------------|
[FM: 0774] |-----*--------------------------|
[FM: 0775] |-----*--------------------------|
[FM: 0776] |----*---------------------------|
[FM: 0777] |----*---------------------------|
[FM: 0778] |---*----------------------------|
[FM: 0779] |---*----------------------------|
[FM: 077A] |--*-----------------------------|
[FM: 077B] |--*-----------------------------|
[FM: 077C] |-*------------------------------|
[FM: 077D] |-*------------------------------|
[FM: 077E] |*-------------------------------|
[FM: 077F] |*-------------------------------|
[FM: 0780] |*-------------------------------|
[FM: 0781] |*-------------------------------|
[FM: 0782] |-*------------------------------|
[FM: 0783] |-*------------------------------|
[FM: 0784] |--*-----------------------------|
[FM: 0785] |--*-----------------------------|
[FM: 0786] |---*----------------------------|
[FM: 0787] |---*----------------------------|
[FM: 0788] |----*---------------------------|
[FM: 0789] |----*---------------------------|
[FM: 078A] |-----*--------------------------|
[FM: 078B] |-----*--------------------------|
[FM: 078C] |------*-------------------------|
[FM: 078D] |------*-------------------------|
[FM: 078E] |-------*------------------------|
[FM: 078F] |-------*------------------------|
[FM: 0790] |--------*-----------------------|
[FM: 0791] |--------*-----------------------|
[FM: 0792] |---------*----------------------|
[FM: 0793] |---------*----------------------|
[FM: 0794] |----------*---------------------|
[FM: 0795] |----------*---------------------|
[FM: 0796] |-----------*--------------------|
[FM: 0797] |-----------*--------------------|
[FM: 0798] |------------*-------------------|
[FM: 0799] |------------*-------------------|
[FM: 079A] |-------------*------------------|
[FM: 079B] |-------------*------------------|
[FM: 079C] |--------------*-----------------|
[FM: 079D] |--------------*-----------------|
[FM: 079E] |---------------*----------------|
[FM: 079F] |---------------*----------------|
[FM: 07A0] |----------------*---------------|
[FM: 07A1] |----------------*---------------|
[FM: 07A2] |-----------------*--------------|
[FM: 07A3] |-----------------*--------------|
[FM: 07A4] |------------------*-------------|
[FM: 07A5] |------------------*-------------|
[FM: 07A6] |-------------------*------------|
[FM: 07A7] |-------------------*------------|
[FM: 07A8] |--------------------*-----------|
[FM: 07A9] |--------------------*-----------|
[FM: 07AA] |---------------------*----------|
[FM: 07AB] |---------------------*----------|
[FM: 07AC] |----------------------*---------|
[FM: 07AD] |----------------------*---------|
[FM: 07AE] |-----------------------*--------|
[FM: 07AF] |-----------------------*--------|
[FM: 07B0] |------------------------*-------|
[FM: 07B1] |------------------------*-------|
[FM: 07B2] |-------------------------*------|
[FM: 07B3] |-------------------------*------|
[FM: 07B4] |--------------------------*-----|
[FM: 07B5] |--------------------------*-----|
[FM: 07B6] |---------------------------*----|
[FM: 07B7] |---------------------------*----|
[FM: 07B8] |----------------------------*---|
[FM: 07B9] |----------------------------*---|
[FM: 07BA] |-----------------------------*--|
[FM: 07BB] |-----------------------------*--|
[FM: 07BC] |------------------------------*-|
[FM: 07BD] |------------------------------*-|
[FM: 07BE] |-------------------------------*|
[FM: 07BF] |-------------------------------*|
[FM: 07C0] |-------------------------------*|
[FM: 07C1] |-------------------------------*|
[FM: 07C2] |------------------------------*-|
[FM: 07C3] |------------------------------*-|
[FM: 07C4] |-----------------------------*--|
[FM: 07C5] |-----------------------------*--|
[FM: 07C6] |----------------------------*---|
[FM: 07C7] |----------------------------*---|
[FM: 07C8] |---------------------------*----|
[FM: 07C9] |---------------------------*----|
[FM: 07CA] |--------------------------*-----|
[FM: 07CB] |--------------------------*-----|
[FM: 07CC] |-------------------------*------|
[FM: 07CD] |-------------------------*------|
[FM: 07CE] |------------------------*-------|
[FM: 07CF] |------------------------*-------|
[FM: 07D0] |-----------------------*--------|
[FM: 07D1] |-----------------------*--------|
[FM: 07D2] |----------------------*---------|
[FM: 07D3] |----------------------*---------|
[FM: 07D4] |---------------------*----------|
[FM: 07D5] |---------------------*----------|
[FM: 07D6] |--------------------*-----------|
[FM: 07D7] |--------------------*-----------|
[FM: 07D8] |-------------------*------------|
[FM: 07D9] |-------------------*------------|
[FM: 07DA] |------------------*-------------|
[FM: 07DB] |------------------*-------------|
[FM: 07DC] |-----------------*--------------|
[FM: 07DD] |-----------------*--------------|
[FM: 07DE] |----------------*---------------|
[FM: 07DF] |----------------*---------------|
[FM: 07E0] |---------------*----------------|
[FM: 07E1] |---------------*----------------|
[FM: 07E2] |--------------*-----------------|
[FM: 07E3] |--------------*-----------------|
[FM: 07E4] |-------------*------------------|
[FM: 07E5] |-------------*------------------|
[FM: 07E6] |------------*-------------------|
[FM: 07E7] |------------*-------------------|
[FM: 07E8] |-----------*--------------------|
[FM: 07E9] |-----------*--------------------|
[FM: 07EA] |----------*---------------------|
[FM: 07EB] |----------*---------------------|
[FM: 07EC] |---------*----------------------|
[FM: 07ED] |---------*----------------------|
[FM: 07EE] |--------*-----------------------|
[FM: 07EF] |--------*-----------------------|
[FM: 07F0] |-------*------------------------|
[FM: 07F1] |-------*------------------------|
[FM: 07F2] |------*-------------------------|
[FM: 07F3] |------*-------------------------|
[FM: 07F4] |-----*--------------------------|
[FM: 07F5] |-----*--------------------------|
[FM: 07F6] |----*---------------------------|
[FM: 07F7] |----*---------------------------|
[FM: 07F8] |---*----------------------------|
[FM: 07F9] |---*----------------------------|
[FM: 07FA] |--*-----------------------------|
[FM: 07FB] |--*-----------------------------|
[FM: 07FC] |-*------------------------------|
[FM: 07FD] |-*------------------------------|
[FM: 07FE] |*-------------------------------|
[FM: 07FF] |*-------------------------------|
[FM: 0800] |*-------------------------------|
[FM: 0801] |*-------------------------------|
[FM: 0802] |-*------------------------------|
[FM: 0803] |-*------------------------------|
[FM: 0804] |--*-----------------------------|
[FM: 0805] |--*-----------------------------|
[FM: 0806] |---*----------------------------|
[FM: 0807] |---*----------------------------|
[FM: 0808] |----*---------------------------|
[FM: 0809] |----*---------------------------|
[FM: 080A] |-----*--------------------------|
[FM: 080B] |-----*--------------------------|
[FM: 080C] |------*-------------------------|
[FM: 080D] |------*-------------------------|
[FM: 080E] |-------*------------------------|
[FM: 080F] |-------*------------------------|
[FM: 0810] |--------*-----------------------|
[FM: 0811] |--------*-----------------------|
[FM: 0812] |---------*----------------------|
[FM: 0813] |---------*----------------------|
[FM: 0814] |----------*---------------------|
[FM: 0815] |----------*---------------------|
[FM: 0816] |-----------*--------------------|
[FM: 0817] |-----------*--------------------|
[FM: 0818] |------------*-------------------|
[FM: 0819] |------------*-------------------|
[FM: 081A] |-------------*------------------|
[FM: 081B] |-------------*------------------|
[FM: 081C] |--------------*-----------------|
[FM: 081D] |--------------*-----------------|
[FM: 081E] |---------------*----------------|
[FM: 081F] |---------------*----------------|
[FM: 0820] |----------------*---------------|
[FM: 0821] |----------------*---------------|
[FM: 0822] |-----------------*--------------|
[FM: 0823] |-----------------*--------------|
[FM: 0824] |------------------*-------------|

UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%MULT18X18D2287.1%TRELLIS_COMB1139242884.7%TRELLIS_FF182242880.7%TRELLIS_IO111975.6%
TimingClockAchievedConstraint$glbnet$clkp40.32 MHz25 MHz$glbnet$clkt368.6 MHz250 MHz
Code

module my_code #(
    parameter int WIDTH = 640,
    parameter int HEIGHT = 480,
    parameter int CONSOLE_COLUMNS = WIDTH / 8,
    parameter int CONSOLE_ROWS = HEIGHT / 8
)(
    input  logic clk,
    input  logic rst,

    input  int px,
    input  int py,
    input  logic hsync,
    input  logic vsync,

    input  int col,
    input  int row,

    output int char,
    output logic [23:0] foreground_color,
    output logic [23:0] background_color,

    output logic [7:0] uart_data,
    input  logic uart_ready,
    output logic uart_valid
);
    // NO inline initialization to prevent TOK_CONSTVAL errors
    logic [31:0] frame_counter;
    logic old_vsync;
    logic [5:0] msg_idx;
    logic sending;

    // --- HELPER FUNCTION: Hex to ASCII (Verilog-2001 compatible) ---
    function [7:0] hex2ascii;
        input [3:0] hex_val;
        begin
            if (hex_val < 4'd10)
                hex2ascii = 8'h30 + {4'h0, hex_val};
            else
                hex2ascii = 8'h41 + ({4'h0, hex_val} - 8'd10);
        end
    endfunction

    // --- COMBINATIONAL LOGIC ---
    logic [7:0] xor_fractal;
    logic [7:0] anim_pattern;
    logic [5:0] tri_wave;
    logic [4:0] star_pos;
    logic [5:0] bar_pos;

    logic [31:0] r_calc;
    logic [31:0] g_calc;
    logic [31:0] b_calc;

    always_comb begin
        // 1. VIDEO: Hardware XOR Fractal (Munching Squares)
        xor_fractal = col[7:0] ^ row[7:0];
        anim_pattern = xor_fractal - frame_counter[7:0];

        case (anim_pattern[7:6])
            2'b00: char = 8'h20; // ' '
            2'b01: char = 8'h2E; // '.'
            2'b10: char = 8'h2B; // '+'
            2'b11: char = 8'h23; // '#'
            default: char = 8'h20;
        endcase

        // Safe 32-bit math, then extract 8 bits
        r_calc = col * 3;
        g_calc = row * 5;
        b_calc = frame_counter * 2;

        foreground_color = {r_calc[7:0], g_calc[7:0], b_calc[7:0]};
        background_color = ~foreground_color;

        // 2. UART: ASCII Oscilloscope (Triangle Wave)
        tri_wave = frame_counter[6:1];
        star_pos = tri_wave[5] ? ~tri_wave[4:0] : tri_wave[4:0];
        bar_pos = msg_idx - 6'd12;

        if (msg_idx < 6'd11) begin
            case(msg_idx)
                6'd0:  uart_data = 8'h5B; // '['
                6'd1:  uart_data = 8'h46; // 'F'
                6'd2:  uart_data = 8'h4D; // 'M'
                6'd3:  uart_data = 8'h3A; // ':'
                6'd4:  uart_data = 8'h20; // ' '
                6'd5:  uart_data = hex2ascii(frame_counter[15:12]);
                6'd6:  uart_data = hex2ascii(frame_counter[11:8]);
                6'd7:  uart_data = hex2ascii(frame_counter[7:4]);
                6'd8:  uart_data = hex2ascii(frame_counter[3:0]);
                6'd9:  uart_data = 8'h5D; // ']'
                6'd10: uart_data = 8'h20; // ' '
                default: uart_data = 8'h20;
            endcase
        end else if (msg_idx == 6'd11 || msg_idx == 6'd44) begin
            uart_data = 8'h7C; // '|'
        end else if (msg_idx >= 6'd12 && msg_idx <= 6'd43) begin
            if (bar_pos == {1'b0, star_pos}) begin
                uart_data = 8'h2A; // '*'
            end else begin
                uart_data = 8'h2D; // '-'
            end
        end else if (msg_idx == 6'd45) begin
            uart_data = 8'h0D; // '\r'
        end else begin
            uart_data = 8'h0A; // '\n'
        end
    end

    // --- SEQUENTIAL LOGIC ---
    always_ff @(posedge clk) begin
        if (rst) begin
            frame_counter <= 0;
            old_vsync <= 0;
            msg_idx <= 0;
            uart_valid <= 1'b0;
            sending <= 1'b0;
        end else begin
            // Track frames on the falling edge of vsync
            if (vsync == 1'b0 && old_vsync == 1'b1) begin
                frame_counter <= frame_counter + 1;
                sending <= 1'b1; // Trigger one line of UART output per frame
            end
            old_vsync <= vsync;

            // UART Handshaking FSM
            if (sending) begin
                uart_valid <= 1'b1;

                if (uart_ready && uart_valid) begin
                    if (msg_idx == 6'd46) begin
                        msg_idx <= 0;
                        uart_valid <= 1'b0;
                        sending <= 1'b0; // Wait for the next vsync
                    end else begin
                        msg_idx <= msg_idx + 1;
                    end
                end
            end else begin
                uart_valid <= 1'b0;
            end
        end
    end
endmodule

#FPGA #Icepi-Zero #HDL #SystemVerilog

#fpga #icepizero #hdl #systemverilog

Icepi Zero Bot @[email protected]

2026-05-22

@[email protected]

@[email protected] asked

Success!

UART Output

UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1024242884.2%TRELLIS_FF157242880.6%TRELLIS_IO111975.6%
TimingClockAchievedConstraint$glbnet$clkp39.77 MHz25 MHz$glbnet$clkt321.34 MHz250 MHz
Code

module my_code #(
    param WIDTH: u32 = 640,
    param HEIGHT: u32 = 480,
    param CONSOLE_COLUMNS: u32 = WIDTH / 8,
    param CONSOLE_ROWS: u32 = HEIGHT / 8
) (
    clk: input clock,
    rst: input reset,

    px: input u32,
    py: input u32,
    hsync: input logic,
    vsync: input logic,

    col: input u32,
    row: input u32,

    char: output u32,
    foreground_color: output logic<24>,
    background_color: output logic<24>,

    uart_data: output logic<8>,
    uart_ready: input logic,
    uart_valid: output logic
) {
    var frame_counter: u32;
    var old_vsync: logic;

    var red: logic<8>;
    var green: logic<8>;
    var blue: logic<8>;

    always_comb {
        red   = (col * 4) as u8;
        green = py as u8;
        blue  = frame_counter as u8;

        background_color = {red, green, blue};
        foreground_color = 24'hff_ff_ff;

        char = 0;
        if(row == 10) {
            if(col == 5) { char = 8'h56; }
            if(col == 6) { char = 8'h65; }
            if(col == 7) { char = 8'h72; }
            if(col == 8) { char = 8'h79; }
            if(col == 9) { char = 8'h6c; }
        }

        uart_data = 0;
        uart_valid = 0;
    }

    always_ff (clk, rst) {
        if_reset {
            frame_counter = 0;
            old_vsync = 0;
        } else {
            if(!vsync && old_vsync) {
                frame_counter = frame_counter + 1;
            }
            old_vsync = vsync;
        }
    }
}

#FPGA #Icepi-Zero #HDL #Veryl

#fpga #icepizero #hdl #veryl

Icepi Zero Bot @[email protected]

2026-05-22

@[email protected]

@[email protected] asked

Success!

UART Output

... [TRUNCATED] ...

Hello Fediverse on UART!
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UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1171242884.8%TRELLIS_FF177242880.7%TRELLIS_IO111975.6%
TimingClockAchievedConstraint$glbnet$clkp39.04 MHz25 MHz$glbnet$clkt345.18 MHz250 MHz
Code

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1');

        uart_data : out std_logic_vector(7 downto 0) := (others => '0');
        uart_ready : in std_logic;
        uart_valid : out std_logic := '0'
    );
end my_code;

architecture rtl of my_code is
    alias red   : std_logic_vector(7 downto 0) is background_color(23 downto 16);
    alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8);
    alias blue  : std_logic_vector(7 downto 0) is background_color(7 downto 0);

    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant example_text : string := "Hello Fediverse! <3";
    constant example_text_row : integer := 15;
    constant example_text_col : integer := 15;

    constant uart_text : string := "Hello Fediverse on UART!" & LF;
begin
    char <= character'pos(example_text(col + 1 - example_text_col))
        when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0;

    red   <= std_logic_vector(to_unsigned(col*4, 8));
    green <= std_logic_vector(to_unsigned(py, 8));
    blue  <= std_logic_vector(resize(frame_counter, 8));

    foreground_color <= (others => '1');

    process(clk)
        variable old_vsync : std_logic := '0';

        variable uart_counter : integer range uart_text'range := 1;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                frame_counter <= frame_counter + 1;
            end if;
            old_vsync := vsync;

            uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8));
            uart_valid <= '1';
            if uart_ready = '1' and uart_valid = '1' then
                if uart_counter < uart_text'length then
                    uart_counter := uart_counter + 1;
                else
                    uart_counter := 1;
                end if;
            end if;
        end if;
    end process;
end architecture;

#FPGA #Icepi-Zero #HDL #VHDL

#fpga #icepizero #hdl #vhdl

Icepi Zero Bot @[email protected]

2026-05-22

@[email protected]

@[email protected] asked

Success!

UART Output

... [TRUNCATED] ...
!
Hello Fediverse on UART!
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UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1171242884.8%TRELLIS_FF177242880.7%TRELLIS_IO111975.6%
TimingClockAchievedConstraint$glbnet$clkp39.04 MHz25 MHz$glbnet$clkt345.18 MHz250 MHz
Code

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1');

        uart_data : out std_logic_vector(7 downto 0) := (others => '0');
        uart_ready : in std_logic;
        uart_valid : out std_logic := '0'
    );
end my_code;

architecture rtl of my_code is
    alias red   : std_logic_vector(7 downto 0) is background_color(23 downto 16);
    alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8);
    alias blue  : std_logic_vector(7 downto 0) is background_color(7 downto 0);

    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant example_text : string := "Hello Fediverse! <3";
    constant example_text_row : integer := 15;
    constant example_text_col : integer := 15;

    constant uart_text : string := "Hello Fediverse on UART!" & LF;
begin
    char <= character'pos(example_text(col + 1 - example_text_col))
        when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0;

    red   <= std_logic_vector(to_unsigned(col*4, 8));
    green <= std_logic_vector(to_unsigned(py, 8));
    blue  <= std_logic_vector(resize(frame_counter, 8));

    foreground_color <= (others => '1');

    process(clk)
        variable old_vsync : std_logic := '0';

        variable uart_counter : integer range uart_text'range := 1;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                frame_counter <= frame_counter + 1;
            end if;
            old_vsync := vsync;

            uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8));
            uart_valid <= '1';
            if uart_ready = '1' and uart_valid = '1' then
                if uart_counter < uart_text'length then
                    uart_counter := uart_counter + 1;
                else
                    uart_counter := 1;
                end if;
            end if;
        end if;
    end process;
end architecture;

#FPGA #Icepi-Zero #HDL #VHDL

#fpga #icepizero #hdl #vhdl

Icepi Zero Bot @[email protected]

2026-05-22

@[email protected]

@[email protected] asked

Success!

UART Output

... [TRUNCATED] ...
 on UART!
Hello Fediverse on UART!
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Hello Fediverse on UART!
Hello Fediverse on UART!
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Hello Fediverse

UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1171242884.8%TRELLIS_FF177242880.7%TRELLIS_IO111975.6%
TimingClockAchievedConstraint$glbnet$clkp39.04 MHz25 MHz$glbnet$clkt345.18 MHz250 MHz
Code

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1');

        uart_data : out std_logic_vector(7 downto 0) := (others => '0');
        uart_ready : in std_logic;
        uart_valid : out std_logic := '0'
    );
end my_code;

architecture rtl of my_code is
    alias red   : std_logic_vector(7 downto 0) is background_color(23 downto 16);
    alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8);
    alias blue  : std_logic_vector(7 downto 0) is background_color(7 downto 0);

    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant example_text : string := "Hello Fediverse! <3";
    constant example_text_row : integer := 15;
    constant example_text_col : integer := 15;

    constant uart_text : string := "Hello Fediverse on UART!" & LF;
begin
    char <= character'pos(example_text(col + 1 - example_text_col))
        when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0;

    red   <= std_logic_vector(to_unsigned(col*4, 8));
    green <= std_logic_vector(to_unsigned(py, 8));
    blue  <= std_logic_vector(resize(frame_counter, 8));

    foreground_color <= (others => '1');

    process(clk)
        variable old_vsync : std_logic := '0';

        variable uart_counter : integer range uart_text'range := 1;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                frame_counter <= frame_counter + 1;
            end if;
            old_vsync := vsync;

            uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8));
            uart_valid <= '1';
            if uart_ready = '1' and uart_valid = '1' then
                if uart_counter < uart_text'length then
                    uart_counter := uart_counter + 1;
                else
                    uart_counter := 1;
                end if;
            end if;
        end if;
    end process;
end architecture;

#FPGA #Icepi-Zero #HDL #VHDL

#fpga #icepizero #hdl #vhdl

Icepi Zero Bot @[email protected]

2026-05-22

@[email protected]

@[email protected] asked

Success!

UART Output

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UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1171242884.8%TRELLIS_FF177242880.7%TRELLIS_IO111975.6%
TimingClockAchievedConstraint$glbnet$clkp39.04 MHz25 MHz$glbnet$clkt345.18 MHz250 MHz
Code

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1');

        uart_data : out std_logic_vector(7 downto 0) := (others => '0');
        uart_ready : in std_logic;
        uart_valid : out std_logic := '0'
    );
end my_code;

architecture rtl of my_code is
    alias red   : std_logic_vector(7 downto 0) is background_color(23 downto 16);
    alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8);
    alias blue  : std_logic_vector(7 downto 0) is background_color(7 downto 0);

    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant example_text : string := "Hello Fediverse! <3";
    constant example_text_row : integer := 15;
    constant example_text_col : integer := 15;

    constant uart_text : string := "Hello Fediverse on UART!" & LF;
begin
    char <= character'pos(example_text(col + 1 - example_text_col))
        when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0;

    red   <= std_logic_vector(to_unsigned(col*4, 8));
    green <= std_logic_vector(to_unsigned(py, 8));
    blue  <= std_logic_vector(resize(frame_counter, 8));

    foreground_color <= (others => '1');

    process(clk)
        variable old_vsync : std_logic := '0';

        variable uart_counter : integer range uart_text'range := 1;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                frame_counter <= frame_counter + 1;
            end if;
            old_vsync := vsync;

            uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8));
            uart_valid <= '1';
            if uart_ready = '1' and uart_valid = '1' then
                if uart_counter < uart_text'length then
                    uart_counter := uart_counter + 1;
                else
                    uart_counter := 1;
                end if;
            end if;
        end if;
    end process;
end architecture;

#FPGA #Icepi-Zero #HDL #VHDL

#fpga #icepizero #hdl #vhdl

Icepi Zero Bot @[email protected]

2026-05-22

@[email protected]

@[email protected] asked

Success!

UART Output

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UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1171242884.8%TRELLIS_FF177242880.7%TRELLIS_IO111975.6%
TimingClockAchievedConstraint$glbnet$clkp39.04 MHz25 MHz$glbnet$clkt345.18 MHz250 MHz
Code

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1');

        uart_data : out std_logic_vector(7 downto 0) := (others => '0');
        uart_ready : in std_logic;
        uart_valid : out std_logic := '0'
    );
end my_code;

architecture rtl of my_code is
    alias red   : std_logic_vector(7 downto 0) is background_color(23 downto 16);
    alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8);
    alias blue  : std_logic_vector(7 downto 0) is background_color(7 downto 0);

    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant example_text : string := "Hello Fediverse! <3";
    constant example_text_row : integer := 15;
    constant example_text_col : integer := 15;

    constant uart_text : string := "Hello Fediverse on UART!" & LF;
begin
    char <= character'pos(example_text(col + 1 - example_text_col))
        when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0;

    red   <= std_logic_vector(to_unsigned(col*4, 8));
    green <= std_logic_vector(to_unsigned(py, 8));
    blue  <= std_logic_vector(resize(frame_counter, 8));

    foreground_color <= (others => '1');

    process(clk)
        variable old_vsync : std_logic := '0';

        variable uart_counter : integer range uart_text'range := 1;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                frame_counter <= frame_counter + 1;
            end if;
            old_vsync := vsync;

            uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8));
            uart_valid <= '1';
            if uart_ready = '1' and uart_valid = '1' then
                if uart_counter < uart_text'length then
                    uart_counter := uart_counter + 1;
                else
                    uart_counter := 1;
                end if;
            end if;
        end if;
    end process;
end architecture;

#FPGA #Icepi-Zero #HDL #VHDL

#fpga #icepizero #hdl #vhdl

Icepi Zero Bot @[email protected]

2026-05-22

@[email protected]

@[email protected] asked

Success!

UART Output

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UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1171242884.8%TRELLIS_FF177242880.7%TRELLIS_IO111975.6%
TimingClockAchievedConstraint$glbnet$clkp39.04 MHz25 MHz$glbnet$clkt345.18 MHz250 MHz
Code

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1');

        uart_data : out std_logic_vector(7 downto 0) := (others => '0');
        uart_ready : in std_logic;
        uart_valid : out std_logic := '0'
    );
end my_code;

architecture rtl of my_code is
    alias red   : std_logic_vector(7 downto 0) is background_color(23 downto 16);
    alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8);
    alias blue  : std_logic_vector(7 downto 0) is background_color(7 downto 0);

    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant example_text : string := "Hello Fediverse! <3";
    constant example_text_row : integer := 15;
    constant example_text_col : integer := 15;

    constant uart_text : string := "Hello Fediverse on UART!" & LF;
begin
    char <= character'pos(example_text(col + 1 - example_text_col))
        when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0;

    red   <= std_logic_vector(to_unsigned(col*4, 8));
    green <= std_logic_vector(to_unsigned(py, 8));
    blue  <= std_logic_vector(resize(frame_counter, 8));

    foreground_color <= (others => '1');

    process(clk)
        variable old_vsync : std_logic := '0';

        variable uart_counter : integer range uart_text'range := 1;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                frame_counter <= frame_counter + 1;
            end if;
            old_vsync := vsync;

            uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8));
            uart_valid <= '1';
            if uart_ready = '1' and uart_valid = '1' then
                if uart_counter < uart_text'length then
                    uart_counter := uart_counter + 1;
                else
                    uart_counter := 1;
                end if;
            end if;
        end if;
    end process;
end architecture;

#FPGA #Icepi-Zero #HDL #VHDL

#fpga #icepizero #hdl #vhdl

Icepi Zero Bot @[email protected]

2026-05-22

@[email protected]

@[email protected] asked

Success!

UART Output

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UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1171242884.8%TRELLIS_FF177242880.7%TRELLIS_IO111975.6%
TimingClockAchievedConstraint$glbnet$clkp39.04 MHz25 MHz$glbnet$clkt345.18 MHz250 MHz
Code

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1');

        uart_data : out std_logic_vector(7 downto 0) := (others => '0');
        uart_ready : in std_logic;
        uart_valid : out std_logic := '0'
    );
end my_code;

architecture rtl of my_code is
    alias red   : std_logic_vector(7 downto 0) is background_color(23 downto 16);
    alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8);
    alias blue  : std_logic_vector(7 downto 0) is background_color(7 downto 0);

    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant example_text : string := "Hello Fediverse! <3";
    constant example_text_row : integer := 15;
    constant example_text_col : integer := 15;

    constant uart_text : string := "Hello Fediverse on UART!" & LF;
begin
    char <= character'pos(example_text(col + 1 - example_text_col))
        when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0;

    red   <= std_logic_vector(to_unsigned(col*4, 8));
    green <= std_logic_vector(to_unsigned(py, 8));
    blue  <= std_logic_vector(resize(frame_counter, 8));

    foreground_color <= (others => '1');

    process(clk)
        variable old_vsync : std_logic := '0';

        variable uart_counter : integer range uart_text'range := 1;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                frame_counter <= frame_counter + 1;
            end if;
            old_vsync := vsync;

            uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8));
            uart_valid <= '1';
            if uart_ready = '1' and uart_valid = '1' then
                if uart_counter < uart_text'length then
                    uart_counter := uart_counter + 1;
                else
                    uart_counter := 1;
                end if;
            end if;
        end if;
    end process;
end architecture;

#FPGA #Icepi-Zero #HDL #VHDL

#fpga #icepizero #hdl #vhdl

Icepi Zero Bot @[email protected]

2026-05-22

@[email protected]

@[email protected] asked

Success!

UART Output

... [TRUNCATED] ...
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Hello Fediverse! <3
Hello Fediverse! <3
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UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1191242884.9%TRELLIS_FF177242880.7%TRELLIS_IO111975.6%
TimingClockAchievedConstraint$glbnet$clkp41.75 MHz25 MHz$glbnet$clkt333.22 MHz250 MHz
Code

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1');

        uart_data : out std_logic_vector(7 downto 0) := (others => '0');
        uart_ready : in std_logic;
        uart_valid : out std_logic := '0'
    );
end my_code;

architecture rtl of my_code is
    alias red   : std_logic_vector(7 downto 0) is background_color(23 downto 16);
    alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8);
    alias blue  : std_logic_vector(7 downto 0) is background_color(7 downto 0);

    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant example_text : string(1 to 20) := "Hello Fediverse! <3" & LF;
    constant example_text_row : integer := 15;
    constant example_text_col : integer := 15;
begin
    char <= character'pos(example_text(col + 1 - example_text_col))
        when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0;

    red   <= std_logic_vector(to_unsigned(col*4, 8));
    green <= std_logic_vector(to_unsigned(py, 8));
    blue  <= std_logic_vector(resize(frame_counter, 8));

    foreground_color <= (others => '1');

    process(clk)
        variable old_vsync : std_logic := '0';

        variable uart_counter : integer range example_text'range := 1;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                frame_counter <= frame_counter + 1;
            end if;
            old_vsync := vsync;

            uart_data <= std_logic_vector(to_unsigned(character'pos(example_text(uart_counter)), 8));
            uart_valid <= '1';
            if uart_ready = '1' and uart_valid = '1' then
                if uart_counter < example_text'length then
                    uart_counter := uart_counter + 1;
                else
                    uart_counter := 1;
                end if;
            end if;
        end if;
    end process;
end architecture;

#FPGA #Icepi-Zero #HDL #VHDL

#fpga #icepizero #hdl #vhdl

Icepi Zero Bot @[email protected]

2026-05-22

@[email protected]

@[email protected] asked

Success!

UART Output

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BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2ٕ͕BU2

UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1375242885.7%TRELLIS_FF230242880.9%TRELLIS_IO111975.6%
TimingClockAchievedConstraint$glbnet$clkp39.66 MHz25 MHz$glbnet$clkt338.87 MHz250 MHz
Code

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1');

        uart_data : out std_logic_vector(7 downto 0) := (others => '0');
        uart_ready : in std_logic;
        uart_valid : out std_logic := '0'
    );
end my_code;

architecture rtl of my_code is
    alias red   : std_logic_vector(7 downto 0) is background_color(23 downto 16);
    alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8);
    alias blue  : std_logic_vector(7 downto 0) is background_color(7 downto 0);

    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant example_text : string(1 to 19) := "Hello Fediverse! <3";
    constant example_text_row : integer := 15;
    constant example_text_col : integer := 15;
begin
    char <= character'pos(example_text(col + 1 - example_text_col))
        when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0;

    red   <= std_logic_vector(to_unsigned(col*4, 8));
    green <= std_logic_vector(to_unsigned(py, 8));
    blue  <= std_logic_vector(resize(frame_counter, 8));

    foreground_color <= (others => '1');

    process(clk)
        variable old_vsync : std_logic := '0';

        variable uart_counter : integer range example_text'range := 1;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                frame_counter <= frame_counter + 1;
            end if;
            old_vsync := vsync;

            uart_data <= std_logic_vector(to_unsigned(character'pos(example_text(uart_counter)), 8));
            uart_valid <= '1';
            if uart_ready = '1' and uart_valid = '1' then
                if uart_counter < example_text'length then
                    uart_counter := uart_counter + 1;
                else
                    uart_counter := 1;
                end if;
            end if;
        end if;
    end process;
end architecture;

#FPGA #Icepi-Zero #HDL #VHDL

#fpga #icepizero #hdl #vhdl

Icepi Zero Bot @[email protected]

2026-05-22

@[email protected]

@[email protected] asked

Success!

UART Output

UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB359242881.5%TRELLIS_FF113242880.5%TRELLIS_IO101975.1%
TimingClockAchievedConstraint$glbnet$clkp140.29 MHz25 MHz$glbnet$clkt363.5 MHz250 MHz
Code

#[no_mangle(all)]
entity my_code(
    clk: clock,
    rst: bool,
    px: int<32>,
    py: int<32>,
    hsync: bool,
    vsync: bool,
    col: int<32>,
    row: int<32>,
    char: inv &int<32>,
    foreground_color: inv &uint<24>,
    background_color: inv &uint<24>,
) {
    set char = &0;
    set foreground_color = &0xFFFFFFu24;
    set background_color = &0xFF7AFFu24;
}

#FPGA #Icepi-Zero #HDL #Spade

#fpga #icepizero #hdl #spade

Icepi Zero Bot @[email protected]

2026-05-21

@[email protected]

@[email protected] asked

Success!

UART Output

UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1837242887.6%TRELLIS_FF167242880.7%TRELLIS_IO101975.1%
TimingClockAchievedConstraint$glbnet$clkp47.17 MHz25 MHz$glbnet$clkt350.51 MHz250 MHz
Code

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity bouncing_text is
    generic(
        CONSOLE_COLUMNS : integer;
        CONSOLE_ROWS : integer;
        SPEED : integer := 1;
        TEXT : string;
        INIT_X : integer := 0;
        INIT_Y : integer := 0
    );
    port (
        clk   : in std_logic;
        reset : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;
        vsync : in std_logic;

        bounce_x : out std_logic;
        bounce_y : out std_logic;
        char : out integer range 0 to 127 := 0
    );
end entity bouncing_text;

architecture rtl of bouncing_text is
    signal position_x : integer range -SPEED to CONSOLE_COLUMNS + SPEED := INIT_X;
    signal position_y : integer range -SPEED to CONSOLE_ROWS + SPEED := INIT_Y;
begin
    char <= character'pos(TEXT(col + 1 - position_x))
        when col >= position_x and col < TEXT'length + position_x and row = position_y else 0;

    process(clk)
        variable old_vsync : std_logic := '0';
        variable speed_x : integer range -SPEED to SPEED := SPEED;
        variable speed_y : integer range -SPEED to SPEED := SPEED;
    begin
        if rising_edge(clk) then
            bounce_x <= '0';
            bounce_y <= '0';
            if vsync = '0' and old_vsync = '1' then
                if position_x + speed_x + TEXT'length >= CONSOLE_COLUMNS then
                    speed_x := -SPEED;
                    position_x <= CONSOLE_COLUMNS - TEXT'length - 1;
                    bounce_x <= '1';
                elsif position_x + speed_x < 0 then
                    speed_x := SPEED;
                    position_x <= 0;
                    bounce_x <= '1';
                else
                    position_x <= position_x + speed_x;
                end if;

                if position_y + speed_y + 1 >= CONSOLE_ROWS then
                    speed_y := -SPEED;
                    position_y <= CONSOLE_ROWS - 1 - 1;
                    bounce_y <= '1';
                elsif position_y + speed_y < 0 then
                    speed_y := SPEED;
                    position_y <= 0;
                    bounce_y <= '1';
                else
                    position_y <= position_y + speed_y;
                end if;
            end if;
            old_vsync := vsync;
        end if;
    end process;
end architecture;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1')
    );
end my_code;

architecture rtl of my_code is
    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant text1 : string(1 to 19) := "I am back! Miau~ :3";
    constant text2 : string(1 to 13) := "*pat pat pat*";
    constant text3 : string(1 to 15) := "nyaaaaaaaaaarge";

    signal char1, char2, char3 : integer range 0 to 127 := 0;

    type rgb_key_array_t is array (0 to 4) of std_logic_vector(23 downto 0);
    constant rgb_key_array : rgb_key_array_t := (x"5bcffa", x"f5abb9", x"ffffff", x"f5abb9", x"5bcffa");
begin
    bounce1 : entity work.bouncing_text
        generic map ( CONSOLE_COLUMNS => CONSOLE_COLUMNS, CONSOLE_ROWS => CONSOLE_ROWS, TEXT => text1, INIT_X => 0, INIT_Y => 0 )
        port map ( clk => clk, reset => rst, col => col, row => row, vsync => vsync, bounce_x => open, bounce_y => open, char => char1 );
    bounce2 : entity work.bouncing_text
        generic map ( CONSOLE_COLUMNS => CONSOLE_COLUMNS, CONSOLE_ROWS => CONSOLE_ROWS, TEXT => text2, INIT_X => 15, INIT_Y => 3 )
        port map ( clk => clk, reset => rst, col => col, row => row, vsync => vsync, bounce_x => open, bounce_y => open, char => char2 );
    bounce3 : entity work.bouncing_text
        generic map ( CONSOLE_COLUMNS => CONSOLE_COLUMNS, CONSOLE_ROWS => CONSOLE_ROWS, TEXT => text3, INIT_X => 5, INIT_Y => 10 )
        port map ( clk => clk, reset => rst, col => col, row => row, vsync => vsync, bounce_x => open, bounce_y => open, char => char3 );

    char <= char1 + char2 + char3;

    foreground_color <= (others => '0');
    background_color <= rgb_key_array((py / (HEIGHT / 5)) mod 5);
end architecture;

#FPGA #Icepi-Zero #HDL #VHDL

#fpga #icepizero #hdl #vhdl

Icepi Zero Bot @[email protected]

2026-05-21

@[email protected]

@[email protected] asked

Success!

UART Output

UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1464242886.0%TRELLIS_FF150242880.6%TRELLIS_IO101975.1%
TimingClockAchievedConstraint$glbnet$clkp47.84 MHz25 MHz$glbnet$clkt320.62 MHz250 MHz
Code

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity bouncing_text is
    generic(
        CONSOLE_COLUMNS : integer;
        CONSOLE_ROWS : integer;
        SPEED : integer := 1;
        TEXT : string;
        INIT_X : integer := 0;
        INIT_Y : integer := 0
    );
    port (
        clk   : in std_logic;
        reset : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;
        vsync : in std_logic;

        bounce_x : out std_logic;
        bounce_y : out std_logic;
        char : out integer range 0 to 127 := 0
    );
end entity bouncing_text;

architecture rtl of bouncing_text is
    signal position_x : integer range -SPEED to CONSOLE_COLUMNS + SPEED := INIT_X;
    signal position_y : integer range -SPEED to CONSOLE_ROWS + SPEED := INIT_Y;
begin
    char <= character'pos(TEXT(col + 1 - position_x))
        when col >= position_x and col < TEXT'length + position_x and row = position_y else 0;

    process(clk)
        variable old_vsync : std_logic := '0';
        variable speed_x : integer range -SPEED to SPEED := SPEED;
        variable speed_y : integer range -SPEED to SPEED := SPEED;
    begin
        if rising_edge(clk) then
            bounce_x <= '0';
            bounce_y <= '0';
            if vsync = '0' and old_vsync = '1' then
                if position_x + speed_x + TEXT'length >= CONSOLE_COLUMNS then
                    speed_x := -SPEED;
                    position_x <= CONSOLE_COLUMNS - TEXT'length - 1;
                    bounce_x <= '1';
                elsif position_x + speed_x < 0 then
                    speed_x := SPEED;
                    position_x <= 0;
                    bounce_x <= '1';
                else
                    position_x <= position_x + speed_x;
                end if;

                if position_y + speed_y + 1 >= CONSOLE_ROWS then
                    speed_y := -SPEED;
                    position_y <= CONSOLE_ROWS - 1 - 1;
                    bounce_y <= '1';
                elsif position_y + speed_y < 0 then
                    speed_y := SPEED;
                    position_y <= 0;
                    bounce_y <= '1';
                else
                    position_y <= position_y + speed_y;
                end if;
            end if;
            old_vsync := vsync;
        end if;
    end process;
end architecture;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1')
    );
end my_code;

architecture rtl of my_code is
    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant text1 : string(1 to 19) := "I am back! Miau~ :3";
    constant text2 : string(1 to 13) := "*pat pat pat*";

    signal char1, char2 : integer range 0 to 127 := 0;

    type rgb_key_array_t is array (0 to 4) of std_logic_vector(23 downto 0);
    constant rgb_key_array : rgb_key_array_t := (x"5bcffa", x"f5abb9", x"ffffff", x"f5abb9", x"5bcffa");

    signal random_bit : std_logic := '0';
    signal color : std_logic_vector(23 downto 0) := x"000000";

    component OSCG is
        generic (
            DIV : integer := 128
        );
        port (
            OSC : out std_logic
        );
    end component;
begin
    bounce1 : entity work.bouncing_text
        generic map (
            CONSOLE_COLUMNS => CONSOLE_COLUMNS, CONSOLE_ROWS => CONSOLE_ROWS,
            TEXT => text1, INIT_X => 0, INIT_Y => 0
        )
        port map (
            clk => clk, reset => rst,
            col => col, row => row, vsync => vsync,
            bounce_x => open, bounce_y => open,
            char => char1
        );
    bounce2 : entity work.bouncing_text
        generic map (
            CONSOLE_COLUMNS => CONSOLE_COLUMNS, CONSOLE_ROWS => CONSOLE_ROWS,
            TEXT => text2, INIT_X => 15, INIT_Y => 3
        )
        port map (
            clk => clk, reset => rst,
            col => col, row => row, vsync => vsync,
            bounce_x => open, bounce_y => open,
            char => char2
        );

    char <= char1 + char2;

    foreground_color <= color;
    background_color <= rgb_key_array((py / (HEIGHT / 5)) mod 5);

    rng : OSCG port map (
        OSC => random_bit
    );
end architecture;

#FPGA #Icepi-Zero #HDL #VHDL

#fpga #icepizero #hdl #vhdl

Icepi Zero Bot @[email protected]

2026-05-21

@[email protected]

@[email protected] asked

Success!

UART Output

UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB966242884.0%TRELLIS_FF133242880.5%TRELLIS_IO101975.1%
TimingClockAchievedConstraint$glbnet$clkp56.02 MHz25 MHz$glbnet$clkt365.1 MHz250 MHz
Code

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity bouncing_text is
    generic(
        CONSOLE_COLUMNS : integer;
        CONSOLE_ROWS : integer;
        SPEED : integer := 1;
        TEXT : string;
        INIT_X : integer := 0;
        INIT_Y : integer := 0
    );
    port (
        clk   : in std_logic;
        reset : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;
        vsync : in std_logic;

        bounce_x : out std_logic;
        bounce_y : out std_logic;
        char : out integer range 0 to 127 := 0
    );
end entity bouncing_text;

architecture rtl of bouncing_text is
    signal position_x : integer range -SPEED to CONSOLE_COLUMNS + SPEED := INIT_X;
    signal position_y : integer range -SPEED to CONSOLE_ROWS + SPEED := INIT_Y;
begin
    char <= character'pos(TEXT(col + 1 - position_x))
        when col >= position_x and col < TEXT'length + position_x and row = position_y else 0;

    process(clk)
        variable old_vsync : std_logic := '0';
        variable speed_x : integer range -SPEED to SPEED := SPEED;
        variable speed_y : integer range -SPEED to SPEED := SPEED;
    begin
        if rising_edge(clk) then
            bounce_x <= '0';
            bounce_y <= '0';
            if vsync = '0' and old_vsync = '1' then
                if position_x + speed_x + TEXT'length >= CONSOLE_COLUMNS then
                    speed_x := -SPEED;
                    position_x <= CONSOLE_COLUMNS - TEXT'length - 1;
                    bounce_x <= '1';
                elsif position_x + speed_x < 0 then
                    speed_x := SPEED;
                    position_x <= 0;
                    bounce_x <= '1';
                else
                    position_x <= position_x + speed_x;
                end if;

                if position_y + speed_y + 1 >= CONSOLE_ROWS then
                    speed_y := -SPEED;
                    position_y <= CONSOLE_ROWS - 1 - 1;
                    bounce_y <= '1';
                elsif position_y + speed_y < 0 then
                    speed_y := SPEED;
                    position_y <= 0;
                    bounce_y <= '1';
                else
                    position_y <= position_y + speed_y;
                end if;
            end if;
            old_vsync := vsync;
        end if;
    end process;
end architecture;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1')
    );
end my_code;

architecture rtl of my_code is
    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant text1 : string(1 to 19) := "I am back! Miau~ :3";
    constant text2 : string(1 to 19) := "I am back! Miau~ :3";

    type rgb_key_array_t is array (0 to 4) of std_logic_vector(23 downto 0);
    constant rgb_key_array : rgb_key_array_t := (x"5bcffa", x"f5abb9", x"ffffff", x"f5abb9", x"5bcffa");

    signal random_bit : std_logic := '0';
    signal color : std_logic_vector(23 downto 0) := x"000000";

    component OSCG is
        generic (
            DIV : integer := 128
        );
        port (
            OSC : out std_logic
        );
    end component;
begin
    bounce1 : entity work.bouncing_text
        generic map (
            CONSOLE_COLUMNS => CONSOLE_COLUMNS,
            CONSOLE_ROWS => CONSOLE_ROWS,
            TEXT => text1
        )
        port map (
            clk => clk,
            reset => rst,

            col => col,
            row => row,
            vsync => vsync,

            bounce_x => open,
            bounce_y => open,
            char => char
        );

    foreground_color <= color;
    background_color <= rgb_key_array((py / (HEIGHT / 5)) mod 5);

    rng : OSCG port map (
        OSC => random_bit
    );
end architecture;

#FPGA #Icepi-Zero #HDL #VHDL

#fpga #icepizero #hdl #vhdl

Icepi Zero Bot @[email protected]

2026-05-21

@[email protected]

@[email protected] asked

Success!

UART Output

UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB966242884.0%TRELLIS_FF133242880.5%TRELLIS_IO101975.1%
TimingClockAchievedConstraint$glbnet$clkp56.02 MHz25 MHz$glbnet$clkt365.1 MHz250 MHz
Code

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity bouncing_text is
    generic(
        CONSOLE_COLUMNS : integer;
        CONSOLE_ROWS : integer;
        SPEED : integer := 1;
        TEXT : string;
        INIT_X : integer := 0;
        INIT_Y : integer := 0
    );
    port (
        clk   : in std_logic;
        reset : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;
        vsync : in std_logic;

        bounce_x : out std_logic;
        bounce_y : out std_logic;
        char : out integer range 0 to 127 := 0
    );
end entity bouncing_text;

architecture rtl of bouncing_text is
    signal position_x : integer range -SPEED to CONSOLE_COLUMNS + SPEED := INIT_X;
    signal position_y : integer range -SPEED to CONSOLE_ROWS + SPEED := INIT_Y;
begin
    char <= character'pos(TEXT(col + 1 - position_x))
        when col >= position_x and col < TEXT'length + position_x and row = position_y else 0;

    process(clk)
        variable old_vsync : std_logic := '0';
        variable speed_x : integer range -SPEED to SPEED := SPEED;
        variable speed_y : integer range -SPEED to SPEED := SPEED;
    begin
        if rising_edge(clk) then
            bounce_x <= '0';
            bounce_y <= '0';
            if vsync = '0' and old_vsync = '1' then
                if position_x + speed_x + TEXT'length >= CONSOLE_COLUMNS then
                    speed_x := -SPEED;
                    position_x <= CONSOLE_COLUMNS - TEXT'length - 1;
                    bounce_x <= '1';
                elsif position_x + speed_x < 0 then
                    speed_x := SPEED;
                    position_x <= 0;
                    bounce_x <= '1';
                else
                    position_x <= position_x + speed_x;
                end if;

                if position_y + speed_y + 1 >= CONSOLE_ROWS then
                    speed_y := -SPEED;
                    position_y <= CONSOLE_ROWS - 1 - 1;
                    bounce_y <= '1';
                elsif position_y + speed_y < 0 then
                    speed_y := SPEED;
                    position_y <= 0;
                    bounce_y <= '1';
                else
                    position_y <= position_y + speed_y;
                end if;
            end if;
            old_vsync := vsync;
        end if;
    end process;
end architecture;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1')
    );
end my_code;

architecture rtl of my_code is
    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant text1 : string(1 to 19) := "I am back! Miau~ :3";
    constant text2 : string(1 to 19) := "I am back! Miau~ :3";

    type rgb_key_array_t is array (0 to 4) of std_logic_vector(23 downto 0);
    constant rgb_key_array : rgb_key_array_t := (x"5bcffa", x"f5abb9", x"ffffff", x"f5abb9", x"5bcffa");

    signal random_bit : std_logic := '0';
    signal color : std_logic_vector(23 downto 0) := x"000000";

    component OSCG is
        generic (
            DIV : integer := 128
        );
        port (
            OSC : out std_logic
        );
    end component;
begin
    bounce1 : entity work.bouncing_text
        generic map (
            CONSOLE_COLUMNS => CONSOLE_COLUMNS,
            CONSOLE_ROWS => CONSOLE_ROWS,
            TEXT => text1
        )
        port map (
            clk => clk,
            reset => rst,

            col => col,
            row => row,
            vsync => vsync,

            bounce_x => open,
            bounce_y => open,
            char => char
        );

    foreground_color <= color;
    background_color <= rgb_key_array((py / (HEIGHT / 5)) mod 5);

    rng : OSCG port map (
        OSC => random_bit
    );
end architecture;

#FPGA #Icepi-Zero #HDL #VHDL

#fpga #icepizero #hdl #vhdl

Icepi Zero Bot @[email protected]

2026-05-21

@[email protected]

@[email protected] asked

Success!

UART Output

UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%OSCG11100.0%TRELLIS_COMB1305242885.4%TRELLIS_FF177242880.7%TRELLIS_IO101975.1%
TimingClockAchievedConstraint$glbnet$clkp40.2 MHz25 MHz$glbnet$clkt350.02 MHz250 MHz
Code

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1')
    );
end my_code;

architecture rtl of my_code is
    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant example_text : string(1 to 19) := "I am back! Miau~ :3";

    type rgb_key_array_t is array (0 to 4) of std_logic_vector(23 downto 0);
    constant rgb_key_array : rgb_key_array_t := (x"5bcffa", x"f5abb9", x"ffffff", x"f5abb9", x"5bcffa");

    constant SPEED : integer := 1;

    signal position_x : integer range -SPEED to CONSOLE_COLUMNS + SPEED := 0;
    signal position_y : integer range -SPEED to CONSOLE_ROWS + SPEED := 0;

    signal random_bit : std_logic := '0';
    signal color : std_logic_vector(23 downto 0) := x"000000";

    component OSCG is
        generic (
            DIV : integer := 128
        );
        port (
            OSC : out std_logic
        );
    end component;
begin
    char <= character'pos(example_text(col + 1 - position_x))
        when col >= position_x and col < example_text'length + position_x and row = position_y else 0;

    foreground_color <= color;
    background_color <= rgb_key_array((py / (HEIGHT / 5)) mod 5);

    rng : OSCG port map (
        OSC => random_bit
    );

    process(clk)
        variable old_vsync : std_logic := '0';
        variable speed_x : integer range -SPEED to SPEED := SPEED;
        variable speed_y : integer range -SPEED to SPEED := SPEED;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                if position_x + speed_x + example_text'length >= CONSOLE_COLUMNS then
                    speed_x := -SPEED;
                    position_x <= CONSOLE_COLUMNS - example_text'length - 1;

                    color <= color(22 downto 0) & random_bit;
                elsif position_x + speed_x < 0 then
                    speed_x := SPEED;
                    position_x <= 0;

                    color <= color(22 downto 0) & random_bit;
                else
                    position_x <= position_x + speed_x;
                end if;

                if position_y + speed_y + 1 >= CONSOLE_ROWS then
                    speed_y := -SPEED;
                    position_y <= CONSOLE_ROWS - 1 - 1;

                    color <= color(22 downto 0) & random_bit;
                elsif position_y + speed_y < 0 then
                    speed_y := SPEED;
                    position_y <= 0;

                    color <= color(22 downto 0) & random_bit;
                else
                    position_y <= position_y + speed_y;
                end if;
            end if;
            old_vsync := vsync;
        end if;
    end process;
end architecture;

#FPGA #Icepi-Zero #HDL #VHDL

#fpga #icepizero #hdl #vhdl

Icepi Zero Bot @[email protected]

2026-05-20

@[email protected]

@[email protected] asked

Success!

UART Output

UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%OSCG11100.0%TRELLIS_COMB1231242885.1%TRELLIS_FF177242880.7%TRELLIS_IO101975.1%
TimingClockAchievedConstraint$glbnet$clkp41.34 MHz25 MHz$glbnet$clkt356.38 MHz250 MHz
Code

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1')
    );
end my_code;

architecture rtl of my_code is
    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant example_text : string(1 to 13) := "I am back~ ;3";

    type rgb_key_array_t is array (0 to 4) of std_logic_vector(23 downto 0);
    constant rgb_key_array : rgb_key_array_t := (x"5bcffa", x"f5abb9", x"ffffff", x"f5abb9", x"5bcffa");

    constant SPEED : integer := 1;

    signal position_x : integer range -SPEED to CONSOLE_COLUMNS + SPEED := 0;
    signal position_y : integer range -SPEED to CONSOLE_ROWS + SPEED := 0;

    signal random_bit : std_logic := '0';
    signal color : std_logic_vector(23 downto 0) := x"000000";

    component OSCG is
        generic (
            DIV : integer := 128
        );
        port (
            OSC : out std_logic
        );
    end component;
begin
    char <= character'pos(example_text(col + 1 - position_x))
        when col >= position_x and col < example_text'length + position_x and row = position_y else 0;

    foreground_color <= color;
    background_color <= rgb_key_array((py / (HEIGHT / 5)) mod 5);

    rng : OSCG port map (
        OSC => random_bit
    );

    process(clk)
        variable old_vsync : std_logic := '0';
        variable speed_x : integer range -SPEED to SPEED := SPEED;
        variable speed_y : integer range -SPEED to SPEED := SPEED;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                if position_x + speed_x + example_text'length >= CONSOLE_COLUMNS then
                    speed_x := -SPEED;
                    position_x <= CONSOLE_COLUMNS - example_text'length - 1;

                    color <= color(22 downto 0) & random_bit;
                elsif position_x + speed_x < 0 then
                    speed_x := SPEED;
                    position_x <= 0;

                    color <= color(22 downto 0) & random_bit;
                else
                    position_x <= position_x + speed_x;
                end if;

                if position_y + speed_y + 1 >= CONSOLE_ROWS then
                    speed_y := -SPEED;
                    position_y <= CONSOLE_ROWS - 1 - 1;

                    color <= color(22 downto 0) & random_bit;
                elsif position_y + speed_y < 0 then
                    speed_y := SPEED;
                    position_y <= 0;

                    color <= color(22 downto 0) & random_bit;
                else
                    position_y <= position_y + speed_y;
                end if;
            end if;
            old_vsync := vsync;
        end if;
    end process;
end architecture;

#FPGA #Icepi-Zero #HDL #VHDL

#fpga #icepizero #hdl #vhdl

Icepi Zero Bot @[email protected]

2026-05-20

@[email protected]

@[email protected] asked

Success!

UART Output

UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%MULT18X18D1283.6%OSCG11100.0%TRELLIS_COMB1447242886.0%TRELLIS_FF180242880.7%TRELLIS_IO101975.1%
TimingClockAchievedConstraint$glbnet$clkp34.93 MHz25 MHz$glbnet$clkt319.28 MHz250 MHz
Code

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1')
    );
end my_code;

architecture rtl of my_code is
    constant IMAGE_WIDTH : integer := 117;
    constant IMAGE_HEIGHT : integer := 52;

    type image_type is array (0 to IMAGE_HEIGHT-1) of std_logic_vector(0 to IMAGE_WIDTH-1);
    constant image : image_type := (
"000000000111111111111111111111111111111111111111111111000000000000000000011111111111111111111111111111111100000000000",
"000000000111111111111111111111111111111111111111111111000000000000000000111111111111111111111111111111111111100000000",
"000000000111111111111111111111111111111111111111111111000000000000000001111111111111111111111111111111111111111000000",
"000000000111111111111111111111111111111111111111111111100000000000000011111111111111111111111111111111111111111110000",
"000000001111111111111111111111111111111111111111111111100000000000000011111111111111111111111111111111111111111111000",
"000000001111111111111111111111111111111111111111111111100000000000000111111111111111111111111111111111111111111111100",
"000000001111111111111111111111111111111111111111111111110000000000001111111111111111111111111111111111111111111111110",
"000000001111111111110000000111111111111111111111111111110000000000011111111111111111111111110000000111111111111111111",
"000000011111111111110000000000111111111111111111111111110000000000011111111111111111111111110000000000111111111111111",
"000000011111111111110000000000011111111111111111111111111000000000111111111111111111111111110000000000011111111111111",
"000000011111111111100000000000001111111111111111111111111000000001111111111111011111111111100000000000001111111111111",
"000000011111111111100000000000000111111111111011111111111000000011111111111110011111111111100000000000000111111111111",
"000000111111111111100000000000000111111111111011111111111100000111111111111100111111111111100000000000000111111111111",
"000000111111111111100000000000000111111111111011111111111100000111111111111000111111111111100000000000000111111111111",
"000000111111111111000000000000001111111111111001111111111100001111111111110000111111111111100000000000001111111111111",
"000000111111111111000000000000001111111111111001111111111110011111111111110000111111111111000000000000001111111111111",
"000001111111111111000000000000001111111111110001111111111110111111111111100000111111111111000000000000001111111111111",
"000001111111111111000000000000011111111111110000111111111110111111111111000001111111111111000000000000011111111111110",
"000001111111111111000000000000111111111111110000111111111111111111111110000001111111111111000000000000111111111111110",
"000001111111111110000000000001111111111111100000111111111111111111111100000001111111111110000000000001111111111111100",
"000001111111111110000000000111111111111111000000011111111111111111111000000001111111111110000000000111111111111111000",
"000011111111111110000000111111111111111110000000011111111111111111110000000011111111111110000000111111111111111110000",
"000011111111111111111111111111111111111100000000011111111111111111100000000011111111111111111111111111111111111100000",
"000011111111111111111111111111111111111000000000001111111111111111100000000011111111111111111111111111111111111000000",
"000011111111111111111111111111111111110000000000001111111111111111000000000011111111111111111111111111111111110000000",
"000111111111111111111111111111111111000000000000000111111111111110000000000111111111111111111111111111111111000000000",
"000111111111111111111111111111111100000000000000000111111111111100000000000111111111111111111111111111111100000000000",
"000111111111111111111111111111100000000000000000000111111111111000000000000111111111111111111111111111100000000000000",
"000111111111111111111111111100000000000000000000000011111111110000000000000111111111111111111111111100000000000000000",
"000111111111111111111100000000000000000000000000000011111111100000000000000111111111111111111100000000000000000000000",
"000000000000000000000000000000000000000000000000000011111111100000000000000000000000000000000000000000000000000000000",
"000000000000000000000000000000000000000000000000000001111111000000000000000000000000000000000000000000000000000000000",
"000000000000000000000000000000000000000000000000000001111110000000000000000000000000000000000000000000000000000000000",
"000000000000000000000000000000000000000000000000000001111100000000000000000000000000000000000000000000000000000000000",
"000000000000000000000000000000000000000000000000000000111000000000000000000000000000000000000000000000000000000000000",
"000000000000000000000000000000000000000000000000000000110000000000000000000000000000000000000000000000000000000000000",
"000000000000000000000000000001111111111111111111111111111111111111111111111111111000000000000000000000000000000000000",
"000000000000000000011111111111111111111111111111111111111111111111111111111111111111111111100000000000000000000000000",
"000000000000111111111111111111111111111111111111111111111111111111111111111111111111111111111111110000000000000000000",
"000000011111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100000000000000",
"000011111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110000000000",
"011111111111111111111110011111001111111001111111000000011111111100000011111111100000001111111111111111111111100000000",
"111111111111111111111110011111001111111001111111001111001111111100111111111111001111100111111111111111111111110000000",
"111111111111111111111111001110011111111001111111001111100111111100111111111110011111110011111111111111111111111000000",
"111111111111111111111111101100111111111001111111001111100111111100000011111110011111110011111111111111111111111000000",
"111111111111111111111111100101111111111001111111001111100111111100111111111110011111110011111111111111111111110000000",
"011111111111111111111111110001111111111001111111001111001111111100111111111111001111100111111111111111111111100000000",
"000011111111111111111111111011111111111001111111000000011111111100000011111111100000001111111111111111111110000000000",
"000000011111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100000000000000",
"000000000000111111111111111111111111111111111111111111111111111111111111111111111111111111111111110000000000000000000",
"000000000000000000011111111111111111111111111111111111111111111111111111111111111111111111110000000000000000000000000",
"000000000000000000000000000001111111111111111111111111111111111111111111111111111100000000000000000000000000000000000"
    );

    constant SPEED : integer := 8;

    signal position_x : integer range -SPEED to WIDTH + SPEED := 0;
    signal position_y : integer range -SPEED to HEIGHT + SPEED := 0;

    signal random_bit : std_logic := '0';
    signal color : std_logic_vector(23 downto 0) := x"FFFFFF";

    component OSCG is
        generic (
            DIV : integer := 128
        );
        port (
            OSC : out std_logic
        );
    end component;
begin
    char <= 0;

    background_color <= color when image(py - position_y)(px - position_x) = '1' and
            px >= position_x and px < position_x + IMAGE_WIDTH and
            py >= position_y and py < position_y + IMAGE_HEIGHT
        else x"000000";
    foreground_color <= (others => '1');

    rng : OSCG port map (
        OSC => random_bit
    );

    process(clk)
        variable old_vsync : std_logic := '0';
        variable speed_x : integer range -SPEED to SPEED := SPEED;
        variable speed_y : integer range -SPEED to SPEED := SPEED;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                if position_x + speed_x + IMAGE_WIDTH >= WIDTH then
                    speed_x := -SPEED;
                    position_x <= WIDTH - IMAGE_WIDTH - 1;

                    color <= color(22 downto 0) & random_bit;
                elsif position_x + speed_x < 0 then
                    speed_x := SPEED;
                    position_x <= 0;

                    color <= color(22 downto 0) & random_bit;
                else
                    position_x <= position_x + speed_x;
                end if;

                if position_y + speed_y + IMAGE_HEIGHT >= HEIGHT then
                    speed_y := -SPEED;
                    position_y <= HEIGHT - IMAGE_HEIGHT - 1;

                    color <= color(22 downto 0) & random_bit;
                elsif position_y + speed_y < 0 then
                    speed_y := SPEED;
                    position_y <= 0;

                    color <= color(22 downto 0) & random_bit;
                else
                    position_y <= position_y + speed_y;
                end if;
            end if;
            old_vsync := vsync;
        end if;
    end process;
end architecture;

#FPGA #Icepi-Zero #HDL #VHDL

#fpga #icepizero #hdl #vhdl

Icepi Zero Bot @[email protected]

2026-02-18

@[email protected] asked

Sucess!

UtilizationCellUsedAvailableUsage DCCA2563.6% EHXPLLL1250% TRELLIS_COMB1901242887.8% TRELLIS_FF176242880.7% TRELLIS_IO101975.1%
TimingClockAchievedConstraint $glbnet$clkp37.98 MHz25 MHz $glbnet$clkt281.21 MHz250 MHz
Code

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity my_code is
generic(
WIDTH : integer := 640;
HEIGHT : integer := 480;
CONSOLE_COLUMNS : integer := WIDTH / 8;
CONSOLE_ROWS : integer := HEIGHT / 8
);
port(
clk : in std_logic;
rst : in std_logic;
px : in integer range 0 to WIDTH - 1;
py : in integer range 0 to HEIGHT - 1;
hsync : in std_logic;
vsync : in std_logic;
col : in integer range 0 to CONSOLE_COLUMNS - 1;
row : in integer range 0 to CONSOLE_ROWS - 1;
char : out integer range 0 to 127 := 0;
foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
background_color : out std_logic_vector(23 downto 0) := (others => '1')
);
end my_code;

architecture rtl of my_code is
  alias bg_red   : std_logic_vector(7 downto 0) is background_color(23 downto 16);
  alias bg_green : std_logic_vector(7 downto 0) is background_color(15 downto 8);
  alias bg_blue  : std_logic_vector(7 downto 0) is background_color(7 downto 0);

  signal frame_counter : unsigned(31 downto 0) := (others => '0');

  -- Aquarium title
  constant title_text : string(1 to 28) := "~~ Tiny VHDL Aquarium! ~~ <3";
  constant title_row  : integer := 1;
  constant title_col  : integer := 26;

  -- Fish 1:  ><>
  constant fish1 : string(1 to 3) := "><>";
  constant fish1_row : integer := 10;

  -- Fish 2:  <>< (facing left)
  constant fish2 : string(1 to 3) := "<><";
  constant fish2_row : integer := 20;

  -- Fish 3:  ><))'>
  constant fish3 : string(1 to 6) := "><))'>";
  constant fish3_row : integer := 30;

  -- Fish 4:  <'((<>
  constant fish4 : string(1 to 6) := "<'((<>";
  constant fish4_row : integer := 40;

  -- Bubbles column
  constant bubble_col : integer := 5;

  -- Seaweed
  constant weed_row_start : integer := 50;

  -- Crab at bottom
  constant crab_text : string(1 to 5) := "V(..)";
  constant crab_row  : integer := 57;
  constant crab_col  : integer := 38;

  signal fish1_col : integer range 0 to CONSOLE_COLUMNS - 1 := 0;
  signal fish2_col : integer range 0 to CONSOLE_COLUMNS - 1 := 70;
  signal fish3_col : integer range 0 to CONSOLE_COLUMNS - 1 := 0;
  signal fish4_col : integer range 0 to CONSOLE_COLUMNS - 1 := 60;

  signal bubble_phase : unsigned(5 downto 0) := (others => '0');

  signal char_out : integer range 0 to 127 := 0;

  -- Helper function: modulo for column wrapping
  function wrap_col(val : integer; max_val : integer) return integer is
  begin
    return val mod max_val;
  end function;

begin

  -- Frame counter & animation
  process(clk)
    variable old_vsync : std_logic := '0';
    variable fc_local  : unsigned(31 downto 0) := (others => '0');
  begin
    if rising_edge(clk) then
      if rst = '1' then
        frame_counter <= (others => '0');
        fish1_col <= 0;
        fish2_col <= 70;
        fish3_col <= 0;
        fish4_col <= 60;
        bubble_phase <= (others => '0');
      elsif vsync = '0' and old_vsync = '1' then
        frame_counter <= frame_counter + 1;

        -- Move fish every 8 frames for a gentle swim
        if frame_counter(2 downto 0) = "000" then
          -- Fish 1 swims right
          if fish1_col < CONSOLE_COLUMNS - 1 then
            fish1_col <= fish1_col + 1;
          else
            fish1_col <= 0;
          end if;

          -- Fish 3 swims right (slower, updates every 16 frames via extra bit)
          if frame_counter(3) = '1' then
            if fish3_col < CONSOLE_COLUMNS - 1 then
              fish3_col <= fish3_col + 1;
            else
              fish3_col <= 0;
            end if;
          end if;

          -- Fish 2 swims left
          if fish2_col > 0 then
            fish2_col <= fish2_col - 1;
          else
            fish2_col <= CONSOLE_COLUMNS - 1;
          end if;

          -- Fish 4 swims left
          if fish4_col > 0 then
            fish4_col <= fish4_col - 1;
          else
            fish4_col <= CONSOLE_COLUMNS - 1;
          end if;

          bubble_phase <= bubble_phase + 1;
        end if;
      end if;
      old_vsync := vsync;
    end if;
  end process;

  -- Character output logic
  process(col, row, fish1_col, fish2_col, fish3_col, fish4_col, frame_counter, bubble_phase)
    variable c : integer range 0 to 127 := 0;
    variable rel : integer;
    variable bub_row : integer;
  begin
    c := 0; -- default: space

    -- Title
    if row = title_row and col >= title_col and col < title_col + title_text'length then
      rel := col - title_col + 1;
      if rel >= 1 and rel <= title_text'length then
        c := character'pos(title_text(rel));
      end if;

    -- Fish 1: ><>  swimming right
    elsif row = fish1_row and col >= fish1_col and col < fish1_col + fish1'length then
      rel := col - fish1_col + 1;
      if rel >= 1 and rel <= fish1'length then
        c := character'pos(fish1(rel));
      end if;

    -- Fish 2: <><  swimming left
    elsif row = fish2_row and col >= fish2_col and col < fish2_col + fish2'length then
      rel := col - fish2_col + 1;
      if rel >= 1 and rel <= fish2'length then
        c := character'pos(fish2(rel));
      end if;

    -- Fish 3: ><))'>  swimming right
    elsif row = fish3_row and col >= fish3_col and col < fish3_col + fish3'length then
      rel := col - fish3_col + 1;
      if rel >= 1 and rel <= fish3'length then
        c := character'pos(fish3(rel));
      end if;

    -- Fish 4: <'((<>  swimming left
    elsif row = fish4_row and col >= fish4_col and col < fish4_col + fish4'length then
      rel := col - fish4_col + 1;
      if rel >= 1 and rel <= fish4'length then
        c := character'pos(fish4(rel));
      end if;

    -- Crab at bottom
    elsif row = crab_row and col >= crab_col and col < crab_col + crab_text'length then
      rel := col - crab_col + 1;
      if rel >= 1 and rel <= crab_text'length then
        c := character'pos(crab_text(rel));
      end if;

    -- Bubbles: 'o' rising in a column, 3 bubbles spaced apart, shifting upward
    elsif col = bubble_col or col = bubble_col + 30 or col = bubble_col + 55 then
      bub_row := to_integer(bubble_phase);
      if row = (CONSOLE_ROWS - 5 - (bub_row mod (CONSOLE_ROWS - 6))) or
         row = (CONSOLE_ROWS - 5 - ((bub_row + 12) mod (CONSOLE_ROWS - 6))) or
         row = (CONSOLE_ROWS - 5 - ((bub_row + 24) mod (CONSOLE_ROWS - 6))) then
        c := character'pos('o');
      end if;

    -- Seaweed at the bottom: alternating | and ( depending on frame for sway
    elsif row >= weed_row_start and row <= CONSOLE_ROWS - 2 then
      if col = 10 or col = 20 or col = 35 or col = 50 or col = 65 or col = 75 then
        if frame_counter(4) = '0' then
          c := character'pos('(');
        else
          c := character'pos(')');
        end if;
      end if;

    -- Sandy bottom
    elsif row = CONSOLE_ROWS - 1 then
      if (col mod 3) = 0 then
        c := character'pos('.');
      elsif (col mod 3) = 1 then
        c := character'pos(',');
      else
        c := character'pos('_');
      end if;

    -- Water surface
    elsif row = 0 then
      if frame_counter(3) = '0' then
        c := character'pos('~');
      else
        c := character'pos('-');
      end if;
    end if;

    char_out <= c;
  end process;

  char <= char_out;

  -- Background: deep ocean gradient (dark blue, getting darker toward bottom)
  process(row, col, frame_counter, py)
    variable depth_blue  : unsigned(7 downto 0);
    variable depth_green : unsigned(7 downto 0);
    variable shimmer     : unsigned(7 downto 0);
  begin
    -- Deeper = darker blue
    depth_blue := to_unsigned(180 - (py / 4), 8);
    depth_green := to_unsigned(40 + (py / 16), 8);
    shimmer := resize(frame_counter(5 downto 0), 8);

    -- Sandy bottom row
    if row >= CONSOLE_ROWS - 2 then
      bg_red   <= x"C2";
      bg_green <= x"B2";
      bg_blue  <= x"6E";
    else
      bg_red   <= std_logic_vector(to_unsigned(5, 8));
      bg_green <= std_logic_vector(depth_green + shimmer(4 downto 2));
      bg_blue  <= std_logic_vector(depth_blue);
    end if;
  end process;

  -- Foreground colors per element
  process(row, col, fish1_col, fish2_col, fish3_col, fish4_col, frame_counter, bubble_phase)
  begin
    -- Default: white-ish
    foreground_color <= x"CCDDFF";

    -- Title: golden yellow
    if row = title_row and col >= title_col and col < title_col + title_text'length then
      foreground_color <= x"FFD700";

    -- Fish 1: orange
    elsif row = fish1_row and col >= fish1_col and col < fish1_col + fish1'length then
      foreground_color <= x"FF6633";

    -- Fish 2: cyan/teal
    elsif row = fish2_row and col >= fish2_col and col < fish2_col + fish2'length then
      foreground_color <= x"00CED1";

    -- Fish 3: magenta/pink
    elsif row = fish3_row and col >= fish3_col and col < fish3_col + fish3'length then
      foreground_color <= x"FF69B4";

    -- Fish 4: lime green
    elsif row = fish4_row and col >= fish4_col and col < fish4_col + fish4'length then
      foreground_color <= x"7FFF00";

    -- Crab: red
    elsif row = crab_row and col >= crab_col and col < crab_col + crab_text'length then
      foreground_color <= x"FF2222";

    -- Bubbles: light blue
    elsif col = bubble_col or col = bubble_col + 30 or col = bubble_col + 55 then
      foreground_color <= x"AAEEFF";

    -- Seaweed: green
    elsif row >= weed_row_start and row <= CONSOLE_ROWS - 2 then
      foreground_color <= x"228B22";

    -- Water surface: light blue
    elsif row = 0 then
      foreground_color <= x"87CEEB";

    -- Sandy bottom text
    elsif row = CONSOLE_ROWS - 1 then
      foreground_color <= x"A09060";
    end if;
  end process;

end architecture;

#FPGA #Icepi-Zero #HDL #VHDL

#fpga #icepizero #hdl #vhdl

Icepi Zero Bot @[email protected]

2026-02-18

@[email protected] asked

Sucess!

UtilizationCellUsedAvailableUsage DCCA2563.6% EHXPLLL1250% MULT18X18D2287.1% OSCG11100% TRELLIS_COMB1100242884.5% TRELLIS_FF196242880.8% TRELLIS_IO101975.1%
TimingClockAchievedConstraint $glbnet$clkp36.51 MHz25 MHz $glbnet$clkt261.37 MHz250 MHz
Code

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1')
    );
end my_code;

architecture rtl of my_code is
    constant IMAGE_WIDTH : integer := 32;
    constant IMAGE_HEIGHT : integer := 32;

    type image_type is array (0 to IMAGE_HEIGHT-1) of std_logic_vector(0 to IMAGE_WIDTH-1);
    constant image_open : image_type := (
        "00000000000000000000000000000000", 
        "00000000000000000000000000000000",
        "00000000000001111111000000000000",
        "00000000000111111111110000000000",
        "00000000011111111111111100000000",
        "00000000111111111110011110000000",
        "00000001111111111100001111000000",
        "00000011111111111110011111100000",
        "00000011111111111111111111100000",
        "00000111111111111111111111110000",
        "00000111111111111111111111110000",
        "00000111111111111111111111110000",
        "00000111111111111111111111000000",
        "00000111111111111111111000000000",
        "00000111111111111111000000000000",
        "00000111111111111110000000000000",
        "00000111111111111110000000000000",
        "00000111111111111110000000000000",
        "00000111111111111110000000000000",
        "00000111111111111111000000000000",
        "00000111111111111111111000000000",
        "00000111111111111111111111000000",
        "00000111111111111111111111110000",
        "00000111111111111111111111110000",
        "00000011111111111111111111100000",
        "00000011111111111111111111100000",
        "00000001111111111111111111000000",
        "00000000111111111111111110000000",
        "00000000011111111111111100000000",
        "00000000000111111111110000000000",
        "00000000000001111111000000000000",
        "00000000000000000000000000000000"
    );
    constant image_closed : image_type := (
        "00000000000000000000000000000000", 
        "00000000000000000000000000000000",
        "00000000000001111111000000000000",
        "00000000000111111111110000000000",
        "00000000011111111111111100000000",
        "00000000111111111110011110000000",
        "00000001111111111100001111000000",
        "00000011111111111110011111100000",
        "00000011111111111111111111100000",
        "00000111111111111111111111110000",
        "00000111111111111111111111110000",
        "00000111111111111111111111110000",
        "00000111111111111111111111110000",
        "00000111111111111111111111110000",
        "00000111111111111111111111110000",
        "00000111111111111111111111110000",
        "00000111111111111111111111110000",
        "00000111111111111111111111110000",
        "00000111111111111111111111110000",
        "00000111111111111111111111110000",
        "00000111111111111111111111110000",
        "00000111111111111111111111110000",
        "00000111111111111111111111110000",
        "00000111111111111111111111110000",
        "00000011111111111111111111100000",
        "00000011111111111111111111100000",
        "00000001111111111111111111000000",
        "00000000111111111111111110000000",
        "00000000011111111111111100000000",
        "00000000000111111111110000000000",
        "00000000000001111111000000000000",
        "00000000000000000000000000000000"
    );

    type grid_type is array (0 to HEIGHT/IMAGE_HEIGHT-1) of std_logic_vector(0 to WIDTH/IMAGE_WIDTH-1);    
    constant grid : grid_type := (
        "11111111111111111111",
        "10000000011000000001",
        "10111111011011111101",
        "10100000000000000101",
        "10101111011011110101",
        "10000000011000000001",
        "11111111011011111111",
        "10000000000000000001",
        "11111111011011111111",
        "10000000011000000001",
        "10101111011011110101",
        "10100000000000000101",
        "10111111011011111101",
        "10000000011000000001",
        "11111111111111111111"
    );

    constant SPEED : integer := 2;

    signal position_x : integer range -SPEED to WIDTH + SPEED := WIDTH/2;
    signal position_y : integer range -SPEED to HEIGHT + SPEED := WIDTH/2;
    signal direction : integer := 0;

    signal image_x : integer range 0 to IMAGE_WIDTH-1;
    signal image_y : integer range 0 to IMAGE_HEIGHT-1;

    signal directional_image_x : integer range 0 to IMAGE_WIDTH-1;
    signal directional_image_y : integer range 0 to IMAGE_HEIGHT-1;

    signal debug_next_tile_x : integer;
    signal debug_next_tile_y : integer;

    signal random_bit : std_logic := '0';
    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    component OSCG is
        generic (
            DIV : integer := 128
        );
        port (
            OSC : out std_logic            
        );
    end component;
begin
    char <= 0;
    foreground_color <= (others => '1');

    image_x <= px - position_x;
    image_y <= py - position_y;

    with direction select
        directional_image_x <= 
            image_x when 0,
            image_y when 1,
            (IMAGE_WIDTH - 1) - image_x when 2,
            (IMAGE_HEIGHT - 1) - image_y when 3,
            0 when others;

    with direction select
        directional_image_y <= 
            image_y when 0,
            (IMAGE_WIDTH - 1) - image_x when 1,
            image_y when 2,
            image_x when 3,
            0 when others;


    background_color <= 
        x"FFFFFF" when grid(py/IMAGE_HEIGHT)(px/IMAGE_WIDTH) = '1' else
        x"FFFF00" when frame_counter(4) = '0' and image_open(directional_image_y)(directional_image_x) = '1' and
                px >= position_x and px < position_x + IMAGE_WIDTH and
                py >= position_y and py < position_y + IMAGE_HEIGHT
            else
        x"FFFF00" when frame_counter(4) = '1' and image_closed(directional_image_y)(directional_image_x) = '1' and
                px >= position_x and px < position_x + IMAGE_WIDTH and
                py >= position_y and py < position_y + IMAGE_HEIGHT
            else
        --x"7F0000" when debug_next_tile_x = px/IMAGE_WIDTH and debug_next_tile_y = py/IMAGE_HEIGHT else
        x"000000";

    rng : OSCG port map (
        OSC => random_bit
    );

    process(clk)
        variable old_vsync : std_logic := '0';
        variable next_direction : integer := 0;

        variable next_x : integer range -SPEED to WIDTH + SPEED := 0;
        variable next_y : integer range -SPEED to HEIGHT + SPEED := 0;
        variable next_tile_x : integer := 0;
        variable next_tile_y : integer := 0;

        variable good : std_logic := '0';
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                frame_counter <= frame_counter + 1;
                good := '0';

                if position_x mod IMAGE_WIDTH = 0 and position_y mod IMAGE_HEIGHT = 0 then
                    if random_bit = '1' then
                        next_direction := (next_direction + 1) mod 4;
                    else
                        next_direction := (next_direction + 3) mod 4;
                    end if;
                end if;
            end if;
            old_vsync := vsync;

            if good = '0' then
                case next_direction is
                    when 0 =>
                        next_x := position_x + SPEED;
                        next_y := position_y;
                    when 1 =>
                        next_x := position_x;
                        next_y := position_y + SPEED;
                    when 2 =>
                        next_x := position_x - SPEED;
                        next_y := position_y;
                    when 3 =>
                        next_x := position_x;
                        next_y := position_y - SPEED;
                    when others =>
                        null;
                end case;

                next_tile_x := next_x / IMAGE_WIDTH;
                next_tile_y := next_y / IMAGE_HEIGHT;
                if next_direction = 0 and (next_x mod IMAGE_WIDTH) /= 0 then
                    next_tile_x := next_tile_x + 1;
                elsif next_direction = 1 and (next_y mod IMAGE_HEIGHT) /= 0 then
                    next_tile_y := next_tile_y + 1;
                end if;

                debug_next_tile_x <= next_tile_x;
                debug_next_tile_y <= next_tile_y;

                if next_tile_y = 7 and next_tile_x = 0 and direction = 2 then
                    good := '1';
                    position_x <= 18*IMAGE_WIDTH;
                    position_y <= position_y;
                    direction <= 0;
                elsif next_tile_y = 7 and next_tile_x = 19 and direction = 0 then
                    good := '1';
                    position_x <= 1*IMAGE_WIDTH;
                    position_y <= position_y;
                    direction <= 2;
                elsif grid(next_tile_y)(next_tile_x) = '0' and next_direction /= ((direction + 2) mod 4) then
                    good := '1';
                    position_x <= next_x;
                    position_y <= next_y;
                    direction <= next_direction mod 4;
                else
                    if random_bit = '1' then
                        next_direction := (next_direction + 1) mod 4;
                    else
                        next_direction := (next_direction + 3) mod 4;
                    end if;
                end if;
            end if;
        end if;
    end process;
end architecture;

#FPGA #Icepi-Zero #HDL #VHDL

#fpga #icepizero #hdl #vhdl

Icepi Zero Bot @[email protected]

2026-02-16

@[email protected] asked

Sucess!

UtilizationCellUsedAvailableUsage DCCA2563.6% EHXPLLL1250% TRELLIS_COMB1078242884.4% TRELLIS_FF149242880.6% TRELLIS_IO101975.1%
TimingClockAchievedConstraint $glbnet$clkp41.75 MHz25 MHz $glbnet$clkt294.29 MHz250 MHz
Code



library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;
entity my_code is

    generic(

        WIDTH : integer := 640;

        HEIGHT : integer := 480;

        CONSOLE_COLUMNS : integer := WIDTH / 8;

        CONSOLE_ROWS : integer := HEIGHT / 8

    );

    port(

        clk : in std_logic;

        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;

        py : in integer range 0 to HEIGHT - 1;

        hsync : in std_logic;

        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;

        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;

        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');

        background_color : out std_logic_vector(23 downto 0) := (others => '1')

    );

end my_code;
architecture rtl of my_code is

    -- Internal signals for color channels

    signal r_sig : std_logic_vector(7 downto 0);

    signal g_sig : std_logic_vector(7 downto 0);

    signal b_sig : std_logic_vector(7 downto 0);
-- Animation state signals
signal frame_counter : unsigned(31 downto 0) := (others => '0');
signal anim_speed    : integer range 0 to 3 := 0;

-- Bouncing text state
constant msg_text    : string := " <3 VHDL <3 ";
signal text_col      : integer range -10 to CONSOLE_COLUMNS + 10 := 5; -- widened range for safety
signal text_row      : integer range -10 to CONSOLE_ROWS + 10 := 5;
signal dir_col       : integer range -1 to 1 := 1;
signal dir_row       : integer range -1 to 1 := 1;

begin
-- Assemble background color from internal signals
background_color <= r_sig & g_sig & b_sig;

-- Foreground is always white
foreground_color <= (others => '1');

----------------------------------------------------------------------------
-- 1. Background Generation
-- Calculates Manhattan distance using IF/ELSE to avoid 'abs' synthesis error.
----------------------------------------------------------------------------
process(px, py, frame_counter)
    variable dx, dy : integer;
    variable dist   : integer;
    variable phase  : unsigned(7 downto 0);
begin
    -- Manual Absolute Value for X
    if px > (WIDTH / 2) then
        dx := px - (WIDTH / 2);
    else
        dx := (WIDTH / 2) - px;
    end if;

    -- Manual Absolute Value for Y
    if py > (HEIGHT / 2) then
        dy := py - (HEIGHT / 2);
    else
        dy := (HEIGHT / 2) - py;
    end if;

    dist := dx + dy;

    -- Create moving phase
    phase := to_unsigned((dist / 2) - to_integer(frame_counter(7 downto 0)), 8);

    -- Assign colors
    r_sig <= std_logic_vector(phase + 128);
    g_sig <= std_logic_vector(phase);
    b_sig <= std_logic_vector(phase - 128);
end process;

----------------------------------------------------------------------------
-- 2. Foreground Text Generation
----------------------------------------------------------------------------
process(col, row, text_col, text_row)
    variable char_index : integer;
begin
    char <= 0; 

    if (row = text_row) and 
       (col >= text_col) and 
       (col < text_col + msg_text'length) then

        char_index := col - text_col + 1;
        char <= character'pos(msg_text(char_index));
    end if;
end process;

----------------------------------------------------------------------------
-- 3. Animation Logic
----------------------------------------------------------------------------
process(clk)
    variable old_vsync : std_logic := '0';
begin
    if rising_edge(clk) then
        if vsync = '0' and old_vsync = '1' then
            frame_counter <= frame_counter + 1;

            -- Update position every few frames
            if anim_speed = 2 then
                anim_speed <= 0;

                -- Check Horizontal Bounds
                if (dir_col = 1 and (text_col + msg_text'length >= CONSOLE_COLUMNS - 1)) then
                    dir_col <= -1;
                elsif (dir_col = -1 and text_col <= 1) then
                    dir_col <= 1;
                else
                    text_col <= text_col + dir_col;
                end if;

                -- Check Vertical Bounds
                if (dir_row = 1 and (text_row >= CONSOLE_ROWS - 2)) then
                    dir_row <= -1;
                elsif (dir_row = -1 and text_row <= 1) then
                    dir_row <= 1;
                else
                    text_row <= text_row + dir_row;
                end if;

            else
                anim_speed <= anim_speed + 1;
            end if;
        end if;

        old_vsync := vsync;
    end if;
end process;

end architecture;

#FPGA #Icepi-Zero #HDL #VHDL

#fpga #icepizero #hdl #vhdl

Icepi Zero Bot @[email protected]

2026-02-15

@[email protected] asked

Sucess!

UtilizationCellUsedAvailableUsage DCCA2563.6% EHXPLLL1250% TRELLIS_COMB1543242886.4% TRELLIS_FF176242880.7% TRELLIS_IO101975.1%
TimingClockAchievedConstraint $glbnet$clkp39.8 MHz25 MHz $glbnet$clkt278.09 MHz250 MHz
Code



library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;
entity my_code is

    generic(

        WIDTH : integer := 640;

        HEIGHT : integer := 480;

        CONSOLE_COLUMNS : integer := WIDTH / 8;

        CONSOLE_ROWS : integer := HEIGHT / 8

    );

    port(

        clk : in std_logic;

        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;

        py : in integer range 0 to HEIGHT - 1;

        hsync : in std_logic;

        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;

        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;

        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');

        background_color : out std_logic_vector(23 downto 0) := (others => '1')

    );

end my_code;
architecture rtl of my_code is

    alias red   : std_logic_vector(7 downto 0) is background_color(23 downto 16);

    alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8);

    alias blue  : std_logic_vector(7 downto 0) is background_color(7 downto 0);
signal frame_counter : unsigned(31 downto 0) := (others => '0');

-- Aquarium title
constant title_text : string(1 to 19) := "~* FPGA AQUARIUM *~";
constant title_row : integer := 2;
constant title_col : integer := (CONSOLE_COLUMNS - title_text'length) / 2;

-- Fish swimming across the screen
signal fish1_col : integer range 0 to CONSOLE_COLUMNS := 10;
signal fish2_col : integer range 0 to CONSOLE_COLUMNS := 50;
signal fish3_col : integer range 0 to CONSOLE_COLUMNS := 30;
constant fish1_row : integer := 15;
constant fish2_row : integer := 25;
constant fish3_row : integer := 35;

-- Bubble positions
signal bubble1_row : integer range 0 to CONSOLE_ROWS := 50;
signal bubble2_row : integer range 0 to CONSOLE_ROWS := 40;
signal bubble3_row : integer range 0 to CONSOLE_ROWS := 45;
constant bubble1_col : integer := 20;
constant bubble2_col : integer := 50;
constant bubble3_col : integer := 70;

-- Seaweed decoration
constant seaweed_text : string(1 to 3) := "|||";

begin
-- Character display logic
process(col, row, fish1_col, fish2_col, fish3_col, bubble1_row, bubble2_row, bubble3_row)
begin
    char <= 0; -- default: space

    -- Title
    if row = title_row and col >= title_col and col < title_col + title_text'length then
        char <= character'pos(title_text(col + 1 - title_col));

    -- Fish 1 (swimming right) ><>
    elsif row = fish1_row and col = fish1_col then
        char <= character'pos('>');
    elsif row = fish1_row and col = fish1_col + 1 then
        char <= character'pos('<');
    elsif row = fish1_row and col = fish1_col + 2 then
        char <= character'pos('>');

    -- Fish 2 (swimming left) <>
    elsif row = fish2_row and col = fish2_col then
        char <= character'pos('<');
    elsif row = fish2_row and col = fish2_col + 1 then
        char <= character'pos('>');
    elsif row = fish2_row and col = fish2_col + 2 then
        char <= character'pos('<');

    -- Fish 3 (swimming right) ><(*)>
    elsif row = fish3_row and col = fish3_col then
        char <= character'pos('>');
    elsif row = fish3_row and col = fish3_col + 1 then
        char <= character'pos('<');
    elsif row = fish3_row and col = fish3_col + 2 then
        char <= character'pos('(');
    elsif row = fish3_row and col = fish3_col + 3 then
        char <= character'pos('*');
    elsif row = fish3_row and col = fish3_col + 4 then
        char <= character'pos(')');
    elsif row = fish3_row and col = fish3_col + 5 then
        char <= character'pos('>');

    -- Bubbles (rising 'o')
    elsif row = bubble1_row and col = bubble1_col then
        char <= character'pos('o');
    elsif row = bubble2_row and col = bubble2_col then
        char <= character'pos('o');
    elsif row = bubble3_row and col = bubble3_col then
        char <= character'pos('o');

    -- Seaweed at bottom
    elsif row >= CONSOLE_ROWS - 8 and (col = 10 or col = 15 or col = 60 or col = 75) then
        char <= character'pos('|');

    end if;
end process;

-- Ocean gradient background (darker at bottom, lighter at top)
red   <= std_logic_vector(to_unsigned(10 + row, 8));
green <= std_logic_vector(to_unsigned(80 + row * 2, 8));
blue  <= std_logic_vector(to_unsigned(180 + row, 8));

-- Bright cyan text for underwater effect
foreground_color <= x"00FFFF";

-- Animation update process
process(clk)
    variable old_vsync : std_logic := '0';
begin
    if rising_edge(clk) then
        if rst = '1' then
            frame_counter <= (others => '0');
            fish1_col <= 10;
            fish2_col <= 50;
            fish3_col <= 30;
            bubble1_row <= 50;
            bubble2_row <= 40;
            bubble3_row <= 45;
        elsif vsync = '0' and old_vsync = '1' then
            frame_counter <= frame_counter + 1;

            -- Animate fish (every 2 frames for smooth motion)
            if frame_counter(1 downto 0) = "00" then
                -- Fish 1: swim right
                if fish1_col < CONSOLE_COLUMNS - 3 then
                    fish1_col <= fish1_col + 1;
                else
                    fish1_col <= 0;
                end if;

                -- Fish 2: swim left
                if fish2_col > 0 then
                    fish2_col <= fish2_col - 1;
                else
                    fish2_col <= CONSOLE_COLUMNS - 3;
                end if;

                -- Fish 3: swim right (slower)
                if frame_counter(2) = '1' then
                    if fish3_col < CONSOLE_COLUMNS - 6 then
                        fish3_col <= fish3_col + 1;
                    else
                        fish3_col <= 0;
                    end if;
                end if;
            end if;

            -- Animate bubbles (rise slowly)
            if frame_counter(2 downto 0) = "000" then
                -- Bubble 1
                if bubble1_row > 5 then
                    bubble1_row <= bubble1_row - 1;
                else
                    bubble1_row <= CONSOLE_ROWS - 5;
                end if;

                -- Bubble 2
                if bubble2_row > 5 then
                    bubble2_row <= bubble2_row - 1;
                else
                    bubble2_row <= CONSOLE_ROWS - 5;
                end if;

                -- Bubble 3
                if bubble3_row > 5 then
                    bubble3_row <= bubble3_row - 1;
                else
                    bubble3_row <= CONSOLE_ROWS - 5;
                end if;
            end if;

        end if;
        old_vsync := vsync;
    end if;
end process;

end architecture;

#FPGA #Icepi-Zero #HDL #VHDL

#fpga #icepizero #hdl #vhdl

Icepi Zero Bot @[email protected]

2026-02-09

@[email protected] asked

Sucess!

UtilizationCellUsedAvailableUsage DCCA2563.6% EHXPLLL1250% TRELLIS_COMB589242882.4% TRELLIS_FF113242880.5% TRELLIS_IO101975.1%
TimingClockAchievedConstraint $glbnet$clkp94.4 MHz25 MHz $glbnet$clkt296.3 MHz250 MHz

#FPGA #Icepi-Zero #HDL #VHDL

#fpga #icepizero #hdl #vhdl

Icepi Zero Bot @[email protected]

2026-02-09

@[email protected] asked

Sucess!

UtilizationCellUsedAvailableUsage DCCA2563.6% EHXPLLL1250% TRELLIS_COMB542242882.2% TRELLIS_FF111242880.5% TRELLIS_IO101975.1%
TimingClockAchievedConstraint $glbnet$clkp88.9 MHz25 MHz $glbnet$clkt280.11 MHz250 MHz

#FPGA #Icepi-Zero #HDL #VHDL

#fpga #icepizero #hdl #vhdl

Icepi Zero Bot @[email protected]

2026-02-06

@[email protected] asked

Sucess!

UtilizationCellUsedAvailableUsage DCCA2563.6% EHXPLLL1250% TRELLIS_COMB1402242885.8% TRELLIS_FF162242880.7% TRELLIS_IO101975.1%
TimingClockAchievedConstraint $glbnet$clkp39.94 MHz25 MHz $glbnet$clkt303.67 MHz250 MHz

#FPGA #Icepi-Zero #HDL #VHDL

#fpga #icepizero #hdl #vhdl

Icepi Zero Bot @[email protected]

2026-02-05

@[email protected] asked

Sucess!

UtilizationCellUsedAvailableUsage DCCA2563.6% EHXPLLL1250% TRELLIS_COMB587242882.4% TRELLIS_FF114242880.5% TRELLIS_IO101975.1%
TimingClockAchievedConstraint $glbnet$clkp90.84 MHz25 MHz $glbnet$clkt307.69 MHz250 MHz

#HDL #FPGA #Icepi-Zero #VHDL

#hdl #fpga #icepizero #vhdl

Icepi Zero Bot @[email protected]

2026-02-04

@[email protected] asked

Sucess!

UtilizationCellUsedAvailableUsage DCCA2563.6% EHXPLLL1250% TRELLIS_COMB1304242885.4% TRELLIS_FF146242880.6% TRELLIS_IO101975.1%
TimingClockAchievedConstraint $glbnet$clkp38.25 MHz25 MHz $glbnet$clkt292.14 MHz250 MHz

#FPGA #Icepi-Zero #HDL #VHDL

#fpga #icepizero #hdl #vhdl

Icepi Zero Bot @[email protected]

2026-02-04

@[email protected] asked

Sucess!

UtilizationCellUsedAvailableUsage DCCA2563.6% EHXPLLL1250% MULT18X18D32810.7% TRELLIS_COMB127502428852.5% TRELLIS_FF144242880.6% TRELLIS_IO101975.1% TRELLIS_RAMW1200303639.5%
TimingClockAchievedConstraint $glbnet$clkp31.59 MHz25 MHz $glbnet$clkt344.47 MHz250 MHz

#FPGA #Icepi-Zero #HDL #SystemVerilog

#fpga #icepizero #hdl #systemverilog

Icepi Zero Bot @[email protected]

2026-02-04

@[email protected] asked

Sucess!

UtilizationCellUsedAvailableUsage DCCA2563.6% EHXPLLL1250% TRELLIS_COMB453242881.9% TRELLIS_FF106242880.4% TRELLIS_IO101975.1%
TimingClockAchievedConstraint $glbnet$clkp102.55 MHz25 MHz $glbnet$clkt293.43 MHz250 MHz

#FPGA #Icepi-Zero #HDL #VHDL

#fpga #icepizero #hdl #vhdl

Icepi Zero Bot @[email protected]

2026-02-01

@[email protected] asked

Sucess!

UtilizationCellUsedAvailableUsage DCCA2563.6% EHXPLLL1250% MULT18X18D2287.1% OSCG11100% TRELLIS_COMB102172428842.1% TRELLIS_FF139242880.6% TRELLIS_IO101975.1% TRELLIS_RAMW1200303639.5%
TimingClockAchievedConstraint $glbnet$clkp40.21 MHz25 MHz $glbnet$clkt278.01 MHz250 MHz

#FPGA #Icepi-Zero #HDL #VHDL

#fpga #icepizero #hdl #vhdl

Icepi Zero Bot @[email protected]

2026-01-31

@[email protected] asked

Sucess!

UtilizationCellUsedAvailableUsage DCCA2563.6% EHXPLLL1250% MULT18X18D1283.6% TRELLIS_COMB1039242884.3% TRELLIS_FF119242880.5% TRELLIS_IO101975.1%
TimingClockAchievedConstraint $glbnet$clkp41.01 MHz25 MHz $glbnet$clkt296.65 MHz250 MHz

#FPGA #Icepi-Zero #HDL #VHDL

#fpga #icepizero #hdl #vhdl

Icepi Zero Bot @[email protected]

2026-01-31

@[email protected] asked

Sucess!

UtilizationCellUsedAvailableUsage DCCA2563.6% EHXPLLL1250% MULT18X18D1283.6% TRELLIS_COMB1041242884.3% TRELLIS_FF119242880.5% TRELLIS_IO101975.1%
TimingClockAchievedConstraint $glbnet$clkp42.52 MHz25 MHz $glbnet$clkt290.7 MHz250 MHz

#FPGA #Icepi-Zero #HDL #VHDL

#fpga #icepizero #hdl #vhdl

JCM @[email protected]

2026-01-28

The @icepi-zero-bot supports Spade now as requested by @thezoq2 🎉
The keyword for detecting it is #[no_mangle.

Sadly I have no experience in Spade, so the current example in the bot's description is very minimal.
If anyone can create a more complex example and wants to contribute it, feel free to message me!

RE: https://wafrn.jcm.re/fediverse/post/c349a0ba-6667-4406-b11f-b95e860f2822
#FPGA #Icepi-Zero #Spade #Spade-HDL #bot #fedibot

#fpga #icepizero #spade #spadehdl #bot #fedibot

JCM @[email protected]

2026-01-27

Small update announcement for the @icepi-zero-bot (that you might have noticed already):

The bot now reports details about utilization and clock speeds together with the video in the success post.
You can split your code into multiple messages if your instance has a low character limit for direct messages (see the bot's description for more details).

For the future, I plan to:

Add support for more HDLs (tell me your favorite ones and I try to integrate them).
Support for outputting text via UART, that the host will capture and include in the success post.

If you have any other ideas/wishes, feel free to tell me :D

#FPGA #bot #fedibot #Icepi-Zero #VHDL #Verilog #SystemVerilog #Amaranth

#fpga #bot #fedibot #icepizero #vhdl #verilog

JCM @[email protected]

2026-01-23

Heyo Fediverse,

Did you ever want to run your VHDL code on someone else's FPGA and see the results as a video?

No?

With @icepi-zero-bot you can do it anyway!

Just send the account an ask containing your VHDL code (see the account's bio for an example) and the bot will synthesize your code, flash it onto my Icepi Zero FPGA board, and record a 30s video of its HDMI output!

I know this might not be the most useful bot, but I've mainly made it just for fun.
Feel free to play around a bit with it! :D

I'll add SystemVerilog support soon, once I figure out how to reliably differentiate it from VHDL based on only the code.

#FPGA #VHDL #bot #fedibot #Icepi-Zero

#fpga #vhdl #bot #fedibot #icepizero

Brad Linder @[email protected]

2025-06-02

Icepi Zero is an open source FPGA board in a Raspberry Pi Zero-sized form factor (crowdfunding)

Nearly a decade ago, Raspberry Pi showed that it’s possible to cram a fully functional computer into a tiny package that’s about the size of a stick of chewing gum or about the size of a USB flash drive. In time since the first Raspberry Pi Zero launched we’ve seen a bunch of updates as well as third-party boards with a similar design but different hardware.

But the Icepi Zero stands out for a […]

#crowdfunding #ecp5 #fpga #icepiZero #openHardware #openSource #raspberryPiZero #sbc

#crowdfunding #ecp5 #fpga #icepizero #openhardware #opensource

N-gated Hacker News @[email protected]

2025-05-30

🚀 Behold, the Icepi Zero: because what the world desperately needed was yet another Raspberry Pi knockoff to join the party. 🤖 It's like they took all the excitement of a Raspberry Pi and squeezed it into an #FPGA – for those who think coding should be as thrilling as watching paint dry. 🖌️
https://github.com/cheyao/icepi-zero #IcepiZero #RaspberryPi #TechInnovation #CodingHumor #GadgetNews #HackerNews #ngated

#fpga #icepizero #raspberrypi #techinnovation #codinghumor #gadgetnews