#sucrela — Public Fediverse posts

Good news!

I'll be at #FOSDEM this year again.

You can meet me at @xcpng stand , see you in building H :)

I'll also be presenting the SucréLA open source logic analyzer: https://fosdem.org/2026/schedule/event/WSKHHU-sucrela_open_source_usb_3_0_logic_analyzer_based_on_fpga/

See you around!

#oshw #opensource #fpga #SucreLA

And look at what I've just received ... 🎁

PCBs + stencil 😍 🍾

A few days after receiving the components from LCSC. 📦
It's still xmas! 🎄

#SucreLA #opensource #oshw #fpga

Ladies and gentlemen, let me present you...

The BOM!

#SucreLA #opensource #fpga #oshw

Manufacturing is done :)

#SucreLA #osh #openhw #fpga #opensource

Manufacturing is done :)

#SucreLA #osh #openhw #fpga #opensource

Manufacturing is done :)

#SucreLA #osh #openhw #fpga #opensource

Manufacturing is done :)

#SucreLA #osh #openhw #fpga #opensource

Look at what I've just received from Digikey :)

#FPGA #SucreLA #openhw #osh

It's already Xmas! 🎄

Look at what I've just received from Digikey :)

#FPGA #SucreLA #openhw #osh

It's already Xmas! 🎄

Look at what I've just received from Digikey :)

#FPGA #SucreLA #openhw #osh

It's already Xmas! 🎄

Look at what I've just received from Digikey :)

#FPGA #SucreLA #openhw #osh

It's already Xmas! 🎄

The taste of layout and routing a high speed 6 layers PCB at night while sipping a de-stressing infusion :)

#SucréLA #pcb #FPGA #hardware

It's hard to find time to post updates on all the progress I am making on the SucréLA #opensource #FPGA based Logic Analyzer 🥵

But it's going forward full steam! 🚂 🚄

Lots of fixes and robustification pushed. 🔧 ✅

It's now working pretty well in PulseView sampling as fast as 128 Msps which is pretty good for a first 2-boards-plugged-together-prototype. 😍

I'm even mostly using it to debug itself now! 🤳

#ecp5 #soc #oshw #SucreLA #fpga

So, to "conclude" yesterday's debug session, it seems that increasing the number of parallel libusb async bulk tranfers from 16 to 32 fixes the issue.

No more late USB reads from the host!
If someone has theories on how to "calibrate" this number of parallel transfers ... is there a formula somewhere?
I still don't understand yet why 32 was not enough and what makes those fail.

#usb #SucreLA #fpga #ecp5 #opensource #logicielslibres

I found the issue! 🥳

Can you see it? :) 🔬 🐛

#opensource #fpga #ecp5 #oshw #SucreLA #logicielslibres #electronics #soc

I'm dogfooding SucréLA! 🐶

I'm currently using it to .... debug itself!

This is showing HSPI packets and the timing of the MCU IRQ handlers for HSPI and USB.

So cool to use it for real and to debug itself :)

#opensource #fpga #ecp5 #oshw #SucreLA #logicielslibres #electronics #soc

SucréLA open-source sw/hw/gateware Logic Analyzer now supports a new exciting feature: x2 and x4 oversampling ! 🥳

Meaning that while the capture pipeline in the SoC runs @ X MHz on N probes, it can now also sample:
* N/2 probes @ 2*X MHz 😍
or
* N/4 probes @ 4*X MHz 🥵

While continuously streaming data to the host PC running sigrok/PulseView via USB 3.0 ⚡

Wanna see how this feature has been developed? 🫣

https://gitlab.com/yannsionneau/SucreLA/-/commit/fbba0ced39b5d9e3c3f4cf9f92c592914d8afee2 🤓

#opensource #fpga #ecp5 #logicielslibres #oshw #soc #SucreLA

If someone wants to help me debug my Lattice ECP5 SSPI programming issue: I uploaded the pulseview (logic analyzer) dumps of the SPI link: https://limewire.com/d/8Xdrk#iWBdBVyut2

You can open this with pulseview and add a SPI decoder.

#fpga #ecp5 #opensource #SucreLA

Pro tips when using Migen's SyncFIFO() module in your pipeline design...

I went from 70 MHz max frequency to 100+ MHz by just adding this parameter: `buffered=True`

It helped a lot for timing closure of the design :)

#FPGA #ECP5 #OpenSource #LiteX #Migen #SucréLA #HydraSucréLA

Pro tips when using Migen's SyncFIFO() module in your pipeline design...

I went from 70 MHz max frequency to 100+ MHz by just adding this parameter: `buffered=True`

It helped a lot for timing closure of the design :)

#FPGA #ECP5 #OpenSource #LiteX #Migen #SucréLA #HydraSucréLA

Pro tips when using Migen's SyncFIFO() module in your pipeline design...

I went from 70 MHz max frequency to 100+ MHz by just adding this parameter: `buffered=True`

It helped a lot for timing closure of the design :)

#FPGA #ECP5 #OpenSource #LiteX #Migen #SucréLA #HydraSucréLA

Pro tips when using Migen's SyncFIFO() module in your pipeline design...

I went from 70 MHz max frequency to 100+ MHz by just adding this parameter: `buffered=True`

It helped a lot for timing closure of the design :)

#FPGA #ECP5 #OpenSource #LiteX #Migen #SucréLA #HydraSucréLA

New PCB rework!

This time instead of soldering on the track I used a short coil wire so the job is cleaner!

Applying the rework-fix on board #2 proved that board #1 io expander was burnt!

All (SPI+io expander) is good now on board #2 :)

#HydraSucréLA #SucréLA #OpenSource #FPGA

The PCB rework of this sunday afternoon :)

It went well!

FYI I don't have binocular nor a good soldering iron.

Had to scratch the track, unsolder the very small resistor, re-solder it on the track (from parallel to series).

It's a bit dirty I agree but it's done and it works!

#HydraSucréLA #SucréLA #FPGA #OpenSource

Routing in progress!

#ECP5 #HydraUSB3 #SucreLA

Routing in progress!

#ECP5 #HydraUSB3 #SucreLA

Routing in progress!

#ECP5 #HydraUSB3 #SucreLA

Routing in progress!

#ECP5 #HydraUSB3 #SucreLA

Routing in progress!

#ECP5 #HydraUSB3 #SucreLA