#hydrasucrela — Public Fediverse posts
Live and recent posts from across the Fediverse tagged #hydrasucrela, aggregated by home.social.
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Pro tips when using Migen's SyncFIFO() module in your pipeline design...
I went from 70 MHz max frequency to 100+ MHz by just adding this parameter: `buffered=True`
It helped a lot for timing closure of the design :)
#FPGA #ECP5 #OpenSource #LiteX #Migen #SucréLA #HydraSucréLA
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Pro tips when using Migen's SyncFIFO() module in your pipeline design...
I went from 70 MHz max frequency to 100+ MHz by just adding this parameter: `buffered=True`
It helped a lot for timing closure of the design :)
#FPGA #ECP5 #OpenSource #LiteX #Migen #SucréLA #HydraSucréLA
-
Pro tips when using Migen's SyncFIFO() module in your pipeline design...
I went from 70 MHz max frequency to 100+ MHz by just adding this parameter: `buffered=True`
It helped a lot for timing closure of the design :)
#FPGA #ECP5 #OpenSource #LiteX #Migen #SucréLA #HydraSucréLA
-
Pro tips when using Migen's SyncFIFO() module in your pipeline design...
I went from 70 MHz max frequency to 100+ MHz by just adding this parameter: `buffered=True`
It helped a lot for timing closure of the design :)
#FPGA #ECP5 #OpenSource #LiteX #Migen #SucréLA #HydraSucréLA
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New PCB rework!
This time instead of soldering on the track I used a short coil wire so the job is cleaner!
Applying the rework-fix on board #2 proved that board #1 io expander was burnt!
All (SPI+io expander) is good now on board #2 :)
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The PCB rework of this sunday afternoon :)
It went well!
FYI I don't have binocular nor a good soldering iron.
Had to scratch the track, unsolder the very small resistor, re-solder it on the track (from parallel to series).
It's a bit dirty I agree but it's done and it works!