#litex — Public Fediverse posts

I've been playing around with #LiteX and #migen #HDL lately and I think it's finally starting to sink in that you can really just do almost arbitrary amounts of "stuff" per clock (limitations apply, objects in mirror may appear closer etc).

It's really very fun! And between trellis, #yosys and #nextpnr you can just... Do it without begging any vendor for a free copy of an EDA.

I highly recommend it! It's so much fun!

You can make your own SoC with deranged peripherals!

#electronics #fpga

I've been playing around with #LiteX and #migen #HDL lately and I think it's finally starting to sink in that you can really just do almost arbitrary amounts of "stuff" per clock (limitations apply, objects in mirror may appear closer etc).

It's really very fun! And between trellis, #yosys and #nextpnr you can just... Do it without begging any vendor for a free copy of an EDA.

I highly recommend it! It's so much fun!

You can make your own SoC with deranged peripherals!

#electronics #fpga

I've been playing around with #LiteX and #migen #HDL lately and I think it's finally starting to sink in that you can really just do almost arbitrary amounts of "stuff" per clock (limitations apply, objects in mirror may appear closer etc).

It's really very fun! And between trellis, #yosys and #nextpnr you can just... Do it without begging any vendor for a free copy of an EDA.

I highly recommend it! It's so much fun!

You can make your own SoC with deranged peripherals!

#electronics #fpga

I've been playing around with #LiteX and #migen #HDL lately and I think it's finally starting to sink in that you can really just do almost arbitrary amounts of "stuff" per clock (limitations apply, objects in mirror may appear closer etc).

It's really very fun! And between trellis, #yosys and #nextpnr you can just... Do it without begging any vendor for a free copy of an EDA.

I highly recommend it! It's so much fun!

You can make your own SoC with deranged peripherals!

#electronics #fpga

I've been playing around with #LiteX and #migen #HDL lately and I think it's finally starting to sink in that you can really just do almost arbitrary amounts of "stuff" per clock (limitations apply, objects in mirror may appear closer etc).

It's really very fun! And between trellis, #yosys and #nextpnr you can just... Do it without begging any vendor for a free copy of an EDA.

I highly recommend it! It's so much fun!

You can make your own SoC with deranged peripherals!

#electronics #fpga

#FOSDEM 2026 was awesome! 🧇

Very cool to meet lots of interesting people :) 🍻 🫂

Video & Slides of my talk about SucréLA are online! 🎉

SucréLA: open source usb 3.0 logic analyzer based on FPGA https://fosdem.org/2026/schedule/event/WSKHHU-sucrela_open_source_usb_3_0_logic_analyzer_based_on_fpga/

#FPGA #opensource #hardware #logiciellibre #sigrok #litex #soc #pcb #usb

#FOSDEM 2026 was awesome! 🧇

Very cool to meet lots of interesting people :) 🍻 🫂

Video & Slides of my talk about SucréLA are online! 🎉

SucréLA: open source usb 3.0 logic analyzer based on FPGA https://fosdem.org/2026/schedule/event/WSKHHU-sucrela_open_source_usb_3_0_logic_analyzer_based_on_fpga/

#FPGA #opensource #hardware #logiciellibre #sigrok #litex #soc #pcb #usb

#FOSDEM 2026 was awesome! 🧇

Very cool to meet lots of interesting people :) 🍻 🫂

Video & Slides of my talk about SucréLA are online! 🎉

SucréLA: open source usb 3.0 logic analyzer based on FPGA https://fosdem.org/2026/schedule/event/WSKHHU-sucrela_open_source_usb_3_0_logic_analyzer_based_on_fpga/

#FPGA #opensource #hardware #logiciellibre #sigrok #litex #soc #pcb #usb

#FOSDEM 2026 was awesome! 🧇

Very cool to meet lots of interesting people :) 🍻 🫂

Video & Slides of my talk about SucréLA are online! 🎉

SucréLA: open source usb 3.0 logic analyzer based on FPGA https://fosdem.org/2026/schedule/event/WSKHHU-sucrela_open_source_usb_3_0_logic_analyzer_based_on_fpga/

#FPGA #opensource #hardware #logiciellibre #sigrok #litex #soc #pcb #usb

#FOSDEM 2026 was awesome! 🧇

Very cool to meet lots of interesting people :) 🍻 🫂

Video & Slides of my talk about SucréLA are online! 🎉

SucréLA: open source usb 3.0 logic analyzer based on FPGA https://fosdem.org/2026/schedule/event/WSKHHU-sucrela_open_source_usb_3_0_logic_analyzer_based_on_fpga/

#FPGA #opensource #hardware #logiciellibre #sigrok #litex #soc #pcb #usb

Oh. Boy. A lot more init stuff is needed. Well that explains it.

https://github.com/enjoy-digital/litex/blob/70b6dc93f658824de4d43a5e0904f2c415ea3ef4/litex/soc/software/liblitedram/sdram.c#L1190

#fpga #litex

Anyone ever use the standalone generator?
I
#fpga #litex

Well that's kind of frustrating. This LiteDRAM DDR2 controller using sim mode (built-in DRAM model) eats the write transaction, eats the read transaction, and then never responds.

I followed the init_sequence from the generated C code, but I have a hunch more is required.

#fpga #litex

Litex: Because who needs years of study when you can cram a "formal language" in a lunch break? 🙄⚡ GitHub's version of "skip the content, learn nothing!" 🤖👨‍💻
https://github.com/litexlang/golitex #Litex #LunchBreak #Learning #SkipTheContent #GitHub #FormalLanguage #HackerNews #ngated

Litex: Because who needs years of study when you can cram a "formal language" in a lunch break? 🙄⚡ GitHub's version of "skip the content, learn nothing!" 🤖👨‍💻
https://github.com/litexlang/golitex #Litex #LunchBreak #Learning #SkipTheContent #GitHub #FormalLanguage #HackerNews #ngated

Litex: Because who needs years of study when you can cram a "formal language" in a lunch break? 🙄⚡ GitHub's version of "skip the content, learn nothing!" 🤖👨‍💻
https://github.com/litexlang/golitex #Litex #LunchBreak #Learning #SkipTheContent #GitHub #FormalLanguage #HackerNews #ngated

Litex: Because who needs years of study when you can cram a "formal language" in a lunch break? 🙄⚡ GitHub's version of "skip the content, learn nothing!" 🤖👨‍💻
https://github.com/litexlang/golitex #Litex #LunchBreak #Learning #SkipTheContent #GitHub #FormalLanguage #HackerNews #ngated

Litex: The First Formal Language Learnable in 1-2 Hours

https://github.com/litexlang/golitex

#HackerNews #Litex #Formal #Language #Learnable #Programming #Education

Woohoo! #SDRAM on #ULX5M is working with #LiteX #FemetoRV!!! #Cologne GateMateA1 that is #CM5 pin compatible... All done with #opensource toolchain!

Woohoo! #SDRAM on #ULX5M is working with #LiteX #FemetoRV!!! #Cologne GateMateA1 that is #CM5 pin compatible... All done with #opensource toolchain!

Woohoo! #SDRAM on #ULX5M is working with #LiteX #FemetoRV!!! #Cologne GateMateA1 that is #CM5 pin compatible... All done with #opensource toolchain!

Woohoo! #SDRAM on #ULX5M is working with #LiteX #FemetoRV!!! #Cologne GateMateA1 that is #CM5 pin compatible... All done with #opensource toolchain!

Woohoo! #SDRAM on #ULX5M is working with #LiteX #FemetoRV!!! #Cologne GateMateA1 that is #CM5 pin compatible... All done with #opensource toolchain!

I'm making lots of progress on the HydraSucréLA bringup! 🎺

Open source sw/hw/gateware logic analyzer incoming!

It's already capturing 🎉 🥳

#opensource #hardware #fpga #ecp5 #LiteX

Pro tips when using Migen's SyncFIFO() module in your pipeline design...

I went from 70 MHz max frequency to 100+ MHz by just adding this parameter: `buffered=True`

It helped a lot for timing closure of the design :)

#FPGA #ECP5 #OpenSource #LiteX #Migen #SucréLA #HydraSucréLA

Pro tips when using Migen's SyncFIFO() module in your pipeline design...

I went from 70 MHz max frequency to 100+ MHz by just adding this parameter: `buffered=True`

It helped a lot for timing closure of the design :)

#FPGA #ECP5 #OpenSource #LiteX #Migen #SucréLA #HydraSucréLA

Pro tips when using Migen's SyncFIFO() module in your pipeline design...

I went from 70 MHz max frequency to 100+ MHz by just adding this parameter: `buffered=True`

It helped a lot for timing closure of the design :)

#FPGA #ECP5 #OpenSource #LiteX #Migen #SucréLA #HydraSucréLA

Pro tips when using Migen's SyncFIFO() module in your pipeline design...

I went from 70 MHz max frequency to 100+ MHz by just adding this parameter: `buffered=True`

It helped a lot for timing closure of the design :)

#FPGA #ECP5 #OpenSource #LiteX #Migen #SucréLA #HydraSucréLA

Nice! nextpnr-xilinx in the #openxc7 #opensource #FPGA toolchain now can place and route a #LiTeX GTX transceiver test design.

Nice! nextpnr-xilinx in the #openxc7 #opensource #FPGA toolchain now can place and route a #LiTeX GTX transceiver test design.

Nice! nextpnr-xilinx in the #openxc7 #opensource #FPGA toolchain now can place and route a #LiTeX GTX transceiver test design.

Nice! nextpnr-xilinx in the #openxc7 #opensource #FPGA toolchain now can place and route a #LiTeX GTX transceiver test design.

Nice! nextpnr-xilinx in the #openxc7 #opensource #FPGA toolchain now can place and route a #LiTeX GTX transceiver test design.

I started a project page to document my first FPGA project on a long while, mainly so that I don't forget, but could possibly be useful to others... I'll plan to add subsequent projects and make more progress on this one in the next few weeks and months.

"I bought myself a Radiona ULX3S from CrowdSupply, which includes the 85k Lattice ECP5 FPGA, which can be programmed to simulate the open source 32-bit RISC-V CPU with a completely open source LiteX-yosys-nextpnr, toolchain."

https://blog.bomorgan.io/hobbies/hardware/fpgas/litex-riscv-ecp5-ulx3s/

#riscv #foss #fpga #litex #yosys #nextpnr #linux #crowdsupply #radiona #ulx3s #lattice #ecp5

I started a project page to document my first FPGA project on a long while, mainly so that I don't forget, but could possibly be useful to others... I'll plan to add subsequent projects and make more progress on this one in the next few weeks and months.

"I bought myself a Radiona ULX3S from CrowdSupply, which includes the 85k Lattice ECP5 FPGA, which can be programmed to simulate the open source 32-bit RISC-V CPU with a completely open source LiteX-yosys-nextpnr, toolchain."

https://blog.bomorgan.io/hobbies/hardware/fpgas/litex-riscv-ecp5-ulx3s/

#riscv #foss #fpga #litex #yosys #nextpnr #linux #crowdsupply #radiona #ulx3s #lattice #ecp5

I started a project page to document my first FPGA project on a long while, mainly so that I don't forget, but could possibly be useful to others... I'll plan to add subsequent projects and make more progress on this one in the next few weeks and months.

"I bought myself a Radiona ULX3S from CrowdSupply, which includes the 85k Lattice ECP5 FPGA, which can be programmed to simulate the open source 32-bit RISC-V CPU with a completely open source LiteX-yosys-nextpnr, toolchain."

https://blog.bomorgan.io/hobbies/hardware/fpgas/litex-riscv-ecp5-ulx3s/

#riscv #foss #fpga #litex #yosys #nextpnr #linux #crowdsupply #radiona #ulx3s #lattice #ecp5

I started a project page to document my first FPGA project on a long while, mainly so that I don't forget, but could possibly be useful to others... I'll plan to add subsequent projects and make more progress on this one in the next few weeks and months.

"I bought myself a Radiona ULX3S from CrowdSupply, which includes the 85k Lattice ECP5 FPGA, which can be programmed to simulate the open source 32-bit RISC-V CPU with a completely open source LiteX-yosys-nextpnr, toolchain."

https://blog.bomorgan.io/hobbies/hardware/fpgas/litex-riscv-ecp5-ulx3s/

#riscv #foss #fpga #litex #yosys #nextpnr #linux #crowdsupply #radiona #ulx3s #lattice #ecp5

I started a project page to document my first FPGA project on a long while, mainly so that I don't forget, but could possibly be useful to others... I'll plan to add subsequent projects and make more progress on this one in the next few weeks and months.

"I bought myself a Radiona ULX3S from CrowdSupply, which includes the 85k Lattice ECP5 FPGA, which can be programmed to simulate the open source 32-bit RISC-V CPU with a completely open source LiteX-yosys-nextpnr, toolchain."

https://blog.bomorgan.io/hobbies/hardware/fpgas/litex-riscv-ecp5-ulx3s/

#riscv #foss #fpga #litex #yosys #nextpnr #linux #crowdsupply #radiona #ulx3s #lattice #ecp5

Just got a 32-bit RISC-V SoC programmed into the Lattice ECP5 FPGA on Radiona's ULX3S using the completely open source LiteX toolchain, including yosys and nextpnr.

#fosh #foss #oshw #fpga #riscv #linux #litex #yosys #nextpnr

Just got a 32-bit RISC-V SoC programmed into the Lattice ECP5 FPGA on Radiona's ULX3S using the completely open source LiteX toolchain, including yosys and nextpnr.

#fosh #foss #oshw #fpga #riscv #linux #litex #yosys #nextpnr

Just got a 32-bit RISC-V SoC programmed into the Lattice ECP5 FPGA on Radiona's ULX3S using the completely open source LiteX toolchain, including yosys and nextpnr.

#fosh #foss #oshw #fpga #riscv #linux #litex #yosys #nextpnr

Just got a 32-bit RISC-V SoC programmed into the Lattice ECP5 FPGA on Radiona's ULX3S using the completely open source LiteX toolchain, including yosys and nextpnr.

#fosh #foss #oshw #fpga #riscv #linux #litex #yosys #nextpnr

Just got a 32-bit RISC-V SoC programmed into the Lattice ECP5 FPGA on Radiona's ULX3S using the completely open source LiteX toolchain, including yosys and nextpnr.

#fosh #foss #oshw #fpga #riscv #linux #litex #yosys #nextpnr

Partially assembled #ULX4M #PCIe baseboard. With onboard resistor jumpers I can set 1x PCIe + 2xSTP or 4x PCIe. I can now check simple stuff, but for PCIe I will need to use #Litex

@whitequark maybe @aleksorsist could use some help with ThunderScope? The ThunderScope folks are #LiteX heretics though. :P I probably shouldn’t cast stones since I’m in a LiteX/Amaranth mixed-mode purgatory.

The Alientek DaVinci Pro #FPGA board now has
#LiTeX support!
https://github.com/litex-hub/litex-boards/pull/582

Wrote up a bunch of automation scripts to set up a #Vivado AMS instance and automated build of cores. Due to the genius of @enjoy_digital #LiTeX tech, all working cores were built for a different FPGA (K325T 3x MiSTer) in a day (5h build time, $5 AWS).

https://youtu.be/hXLaA0ITzy8

Playing with #litex #litescope FPGA logic analyzer. That stuff works super well. What the #FOSS #fpga people (#litex #migen #oss-cad #yosys #openocd and all the others hidden in the toolchain) have done is amazing. The board is a colorlight 5a-75b with an ECP5.
https://kraut.zone/w/k2qy5PXbBuHhozcDf9QgbP

Code: https://github.com/bjonnh/alscope

Playing with #litex #litescope FPGA logic analyzer. That stuff works super well. What the #FOSS #fpga people (#litex #migen #oss-cad #yosys #openocd and all the others hidden in the toolchain) have done is amazing. The board is a colorlight 5a-75b with an ECP5.
https://kraut.zone/w/k2qy5PXbBuHhozcDf9QgbP

Code: https://github.com/bjonnh/alscope

Playing with #litex #litescope FPGA logic analyzer. That stuff works super well. What the #FOSS #fpga people (#litex #migen #oss-cad #yosys #openocd and all the others hidden in the toolchain) have done is amazing. The board is a colorlight 5a-75b with an ECP5.
https://kraut.zone/w/k2qy5PXbBuHhozcDf9QgbP

Code: https://github.com/bjonnh/alscope