#litex — Public Fediverse posts

I've been playing around with #LiteX and #migen #HDL lately and I think it's finally starting to sink in that you can really just do almost arbitrary amounts of "stuff" per clock (limitations apply, objects in mirror may appear closer etc).

It's really very fun! And between trellis, #yosys and #nextpnr you can just... Do it without begging any vendor for a free copy of an EDA.

I highly recommend it! It's so much fun!

You can make your own SoC with deranged peripherals!

#electronics #fpga

Pro tips when using Migen's SyncFIFO() module in your pipeline design...

I went from 70 MHz max frequency to 100+ MHz by just adding this parameter: `buffered=True`

It helped a lot for timing closure of the design :)

#FPGA #ECP5 #OpenSource #LiteX #Migen #SucréLA #HydraSucréLA

I started a project page to document my first FPGA project on a long while, mainly so that I don't forget, but could possibly be useful to others... I'll plan to add subsequent projects and make more progress on this one in the next few weeks and months.

"I bought myself a Radiona ULX3S from CrowdSupply, which includes the 85k Lattice ECP5 FPGA, which can be programmed to simulate the open source 32-bit RISC-V CPU with a completely open source LiteX-yosys-nextpnr, toolchain."

https://blog.bomorgan.io/hobbies/hardware/fpgas/litex-riscv-ecp5-ulx3s/

#riscv #foss #fpga #litex #yosys #nextpnr #linux #crowdsupply #radiona #ulx3s #lattice #ecp5

Just got a 32-bit RISC-V SoC programmed into the Lattice ECP5 FPGA on Radiona's ULX3S using the completely open source LiteX toolchain, including yosys and nextpnr.

#fosh #foss #oshw #fpga #riscv #linux #litex #yosys #nextpnr

Wrote up a bunch of automation scripts to set up a #Vivado AMS instance and automated build of cores. Due to the genius of @enjoy_digital #LiTeX tech, all working cores were built for a different FPGA (K325T 3x MiSTer) in a day (5h build time, $5 AWS).

https://youtu.be/hXLaA0ITzy8

Playing with #litex #litescope FPGA logic analyzer. That stuff works super well. What the #FOSS #fpga people (#litex #migen #oss-cad #yosys #openocd and all the others hidden in the toolchain) have done is amazing. The board is a colorlight 5a-75b with an ECP5.
https://kraut.zone/w/k2qy5PXbBuHhozcDf9QgbP

Code: https://github.com/bjonnh/alscope

Should anyone have any use for an Ethernet PHY PMOD, I've pushed my design files and related materials along with a readme, under a permissive open hardware license to a github repository. Enjoy!
https://github.com/swetland/ethernet-pmod
#fpga #pmod #oshw #litex