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A year's worth of work and headache. Being stuck 95% of the time. Finally the first square wave coming out of the Kintex7 GTX transceiver, using #openXC7 the full open source FPGA toolchain.
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Yay!
Several months of work on the #openXC7 #opensource #FPGA toolchain, and the first tangible result:
This LED means, that the GTX PLL has lock! -
Nice! nextpnr-xilinx in the #openxc7 #opensource #FPGA toolchain now can place and route a #LiTeX GTX transceiver test design.
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Placing GTX bels already seems to work.
Nice. #openXC7 #opensource #FPGA toolchain. -
Thanks Chandler Klüser for contributing an MSX port for the #MiSTeX retrogaming system!
https://youtu.be/xek4TRzTf9M -
I am deactivating my patreon for the #MiSTeX #FPGA #retrogaming project
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Good news for #openXC7 #opensource #fpga toolchain: The GTXE2_CHANNEL fuzzer now works perfectly, finds all the features the GTP fuzzer finds, and even a couple more:
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GTP and GTX fuzzers give very similar results. Good, adds more plausibility to the GTX results.
#openxc7 #opensource #fpga #toolchain -
Cool! I think I solved most of the GTX_CHANNEL bits. #openxc7 #OpenSource #FPGA #prjxray
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Yay, looks like I have my first solutions for the GTX_COMMON primitive! #openXC7 #opensource #FPGA
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I created a 3D printed diopter insert for #walksnail goggles L. Works perfectly, I can see everything clearly now.
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New important bugfix release of the #openXC7 #opensource #FPGA toolchain
https://github.com/openXC7/nextpnr-xilinx/releases/tag/0.8.2 -
New important bugfix release for the #openXC7 #opensource #FPGA toolchain:
https://github.com/openXC7/nextpnr-xilinx/releases/tag/0.8.1 -
Version 0.8.0 of the #openXC7 #opensource #FPGA toolchain has been released!
Now featuring GTP-Transceiver support for Artix7,
the BUFH/BUFHCE primitive and MMCM-fixes.
https://github.com/openXC7/nextpnr-xilinx/releases/tag/0.8.0 -
GTP receiver also seems to be working with internal loopback with the #openXC7 #opensource #FPGA toolchain. LED patterns shows receiver data (a counter), and it is qualitatively the same as the vivado version.
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GTP Transceivers are now also working with internal refclk on Xilinx Artix FPGAs with the #openXC7 #opensource #FPGA #toolchain
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Ported Minimig-AGA to the Xilinx-#MiSTeX #FPGA #retrogaming platform today.
Basically works (Kickstart 1.3 boots), but has lots of bugs (graphical glitches, floppy hangs on load). -
First signs of life from the GTP Multi-Gigabit Transceivers using the #openXC7 #opensource #FPGA toolchain on an Artix7 FPGA. This was several months of work.
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Building 11 @topapate #retrogaming #MiSTeX cores simultaneously on an AWS 32 core 128GB RAM machine, for Kintex 325T.
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There is now a binary repository with ready made bitstreams for the #MiSTeX #retrogaming #FPGA project.
https://github.com/MiSTeX-devel/MiSTeX-bin -
Three more #retrogaming #arcade #FPGA cores from @topapate working on #MiSTeX on Xilinx!
We now have a total of 47 working JOTEGO cores!
https://github.com/MiSTeX-devel/MiSTeX-ports/tree/main/cores -
The Bubble Bobble arcade core is now working on #Xilinx #FPGA s on the #MiSTeX #retrogaming platform.
Thanks to the great work of @somhi (on GitHub) , this port only took 10 minutes. -
The 1943 core is now working on #Xilinx #FPGA s on the #MiSTeX #retrogaming platform.
Thanks to the great work of @somhi (on GitHub) , this port only took 30 minutes. -
The 1942 core is now working on #Xilinx #FPGAs on the #MiSTeX #retrogaming platform.
Thanks to the fantastic work of @somhi (on GitHub),
I could write a shell script which automates most of the gruntwork of the porting process.
This is the first one ported with that script.
I did the script and this port in a couple of hours. -
The first core using the JOTEGO's (@topapate) framework is working on Xilinx FPGAs on the #MiSTeX #retrogaming #FPGA platform!
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First blinky greetings from the GTPE2_COMMON PLL using the #openXC7 #opensource #FPGA toolchain.
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Nice!
The #openxc7 #opensource #FPGA toolchain already seems to be able to place GTP transceivers.
I only still have to figure out how to use an internal refclk, something even Vivado only does under protest (DRC rule downgrade). -
The #MiSTeX #fpga #retrogaming baseboard rev2 has arrived!
It has the MiSTeX logo and an additional trace from the
HPS to the RP2040, to allow updating the RP2040 firmware from the HPS linux system. And latching switches. -
Thanks @lu_source
for covering the #MiSTeX #retrogaming #FPGA project -
NES now works on the #MiSTeX #FPGA #retrogaming console! (With limitations, no savestates, no PAL/NTSC)
Also: Now the full 256 MB of DDR3 memory are useable on the QMTech Xilinx boards (previously 128MB) and the bandwidth is double too (16 bit access instead of 8 bit) -
Thanks Chandler Klüser for covering the #MiSTeX project
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That is how revision 2 of the #MiSTeX #FPGA #retrogaming baseboard looks like now.
Details on my patreon:
https://t.co/y7JZfGUDnU -
rev2 of the #MiSTeX #retrogaming #FPGA baseboard is upcoming, fixing the (minor) issues of rev1, moving to KiCAD8 and using @baxysquare ' s cute MiSTeX-Kun mascot.
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This week's work. Implement dynamic reconfiguration core for #Xilinx #FPGAs. Integrate into #MiSTeX #opensource #retrogames #console. Now changing video modes and #HDMI works with Xilinx FPGAs for the first time. Up to 1366x768@60. FullHD not yet. Hope for the new board revision.
VGA works with 1080p. -
The #MiSTeX #FPGA retro game console for #QMTech core boards is almost ready to be sent to the fab @JLCPCB
You can look into the design files here:
https://kicanvas.org/?github=https%3A%2F%2Fgithub.com%2FMiSTeX-devel%2FMiSTeX-hardware%2Ftree%2Fmain%2FQMTech-MiSTeX -
Just got a dynamic reconfiguration core working for the MMCME2_ADV using the #openXC7 #opensource #FPGA toolchain. Should also work with minor modifications for the PLLE2_ADV (upcoming).
This took 10 seconds to compile and 5 seconds to upload to the FPGA, using 100% open source tools. Compare that with Vivado!
My first nontrivial piece of #Verilog !
Here is the source:
https://github.com/openXC7/primitive-tests/blob/main/mmcm-reconfig/xilinx7_reconfig.v -
There is now a docker container version available for the #openXC7 #opensource #FPGA toolchain:
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The #openXC7 #opensource #FPGA toolchain now uses Yosys 0.36, upgrading from Yosys 0.17, since the problems it had with Xilinx series 7 FPGAs have been resolved.
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New release of the #openxc7 #opensource #FPGA toolchain.
https://github.com/openXC7/openXC7-snap/releases/tag/0.7.0 -
Yay! MMCME2_ADV on the #openxc7 #OpenSource #FPGA toolchain now supports fractional scaling! This is 100MHz * 10.625 / 20.875
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First blinky driven by an MMCME2_ADV PLL, using the #openxc7 #opensource #FPGA toolchain.
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Many thanks to Milosch Meriac, for contributing a podman containerized version of the Nix toolchain packaging of the #opensource #openXC7 #FPGA toolchain
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Good news for the #openXC7 #opensource #FPGA toolchain. It might be just time to move from yosys 0.17 to yosys 0.34.
Not only seem the abc9 crashes and the BRAM problems seem to have gone away, 0.17 seemed to generate broken hardware DSPs in some cases where 0.34 does not. -
Thanks @splinedrive
for testing countless bitstreams from the #openXC7 #opensource #FPGA toolchain on the Artix7 with your SoC, which, interestingly enough triggered some bugs which the much more complex @enjoy_digital
LiteX SoC did not. The toolchain became so much better! -
New important bugfix release of the #openXC7 #opensource #FPGA toolchain for Xilinx 7series devices. I backported the latest features to the old stable codebase, to give you back router2 performance and stability.