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#fpgas — Public Fediverse posts

Live and recent posts from across the Fediverse tagged #fpgas, aggregated by home.social.

  1. "The FPGA earned the Milestone designation because it introduced iteration to semiconductor design. Engineers could redesign hardware repeatedly without fabricating a new chip, dramatically reducing development risk and enabling faster innovation at a time when semiconductor costs were rising rapidly."

    spectrum.ieee.org/fpga-chip-ie

    #IEEE #Milestones #History #Technology #Engineering #FPGAs

  2. "The FPGA earned the Milestone designation because it introduced iteration to semiconductor design. Engineers could redesign hardware repeatedly without fabricating a new chip, dramatically reducing development risk and enabling faster innovation at a time when semiconductor costs were rising rapidly."

    spectrum.ieee.org/fpga-chip-ie

    #IEEE #Milestones #History #Technology #Engineering #FPGAs

  3. "The FPGA earned the Milestone designation because it introduced iteration to semiconductor design. Engineers could redesign hardware repeatedly without fabricating a new chip, dramatically reducing development risk and enabling faster innovation at a time when semiconductor costs were rising rapidly."

    spectrum.ieee.org/fpga-chip-ie

    #IEEE #Milestones #History #Technology #Engineering #FPGAs

  4. "The FPGA earned the Milestone designation because it introduced iteration to semiconductor design. Engineers could redesign hardware repeatedly without fabricating a new chip, dramatically reducing development risk and enabling faster innovation at a time when semiconductor costs were rising rapidly."

    spectrum.ieee.org/fpga-chip-ie

    #IEEE #Milestones #History #Technology #Engineering #FPGAs

  5. "The FPGA earned the Milestone designation because it introduced iteration to semiconductor design. Engineers could redesign hardware repeatedly without fabricating a new chip, dramatically reducing development risk and enabling faster innovation at a time when semiconductor costs were rising rapidly."

    spectrum.ieee.org/fpga-chip-ie

    #IEEE #Milestones #History #Technology #Engineering #FPGAs

  6. Unveiling the Architectural Advantage: FPGAs as AI’s Secret Inference Powerhouse The race to dominate the artificial intelligence (AI) field predominantly focuses on raw computing power—most of...

    #AI #Hardware #AI #hardware #AI #inference #amd #Apple #FPGA #FPGAs #M1Ultra

    Origin | Interest | Match
  7. 🚀 In a groundbreaking revelation, we discover that #FPGAs can fit in USB ports! 🙄 Apparently, playing with decades-old tech is "interesting" if you add enough jargon. 🦖 Who knew routing signals in a thumb drive was the pinnacle of innovation? 😅
    danielmangum.com/posts/spi-rou #USBInnovation #TechTrends #SignalRouting #NerdHumor #HackerNews #ngated

  8. Discover how GPUs accelerate the power of Generative AI, enabling groundbreaking creativity and innovation. Explore the tradeoffs, challenges, and alternatives to GPUs, and learn how to make informed decisions for your AI projects. #GenerativeAI #GPU #DeepLearning #AIInnovation #Technology #FPGAs #TPUs #AIHardware #ArtificialIntelligence #AIOptimization
    medium.com/@sanjay.mohindroo66

  9. Fearlessly generate your own clocks with Lattice ECP5 #FPGAs and Yosys. Includes worked examples for #ULX3S and easy to adapt to any dev board. Happy #FPGAFriday! @yosyshq projectf.io/posts/ecp5-fpga-cl

  10. Hello everyone. On this account, I want to share my experience with and digital circuit development in general. My colleagues and I have also started a blog fpgahero.com where we will occasionally write posts on this topic. Stay tuned.

  11. The new Pro 24.1 will be released soon.The new feature will support from 5 series by and will probably not require a paid license. It was mentioned on Reddit: reddit.com/r/FPGA/comments/1bn

  12. @jgkoomey @geerlingguy @film_girl
    This is a subject super near and dear to me. I now basically work on and to a much lesser degree but in the time around when the M1 came out was a string of R&D programs I started on that got cancelled in succession for "limited business viability" reasons.

  13. :fox_3c:

    Anyone here knowledgeable about #FPGAs that I could chat to if i have questions? 🥺

  14. The 1942 core is now working on on the platform.
    Thanks to the fantastic work of @somhi (on GitHub),
    I could write a shell script which automates most of the gruntwork of the porting process.
    This is the first one ported with that script.
    I did the script and this port in a couple of hours.

  15. Which vendor do you prefer? Feel free to explain why in the comments. Thanks for every boost!

  16. My project spi-fpga is available on Github for many years and is gradually collecting stars. It is just a simple controller for written in , so I didn't expect 156 stars. github.com/jakubcabal/spi-fpga

  17. This week's work. Implement dynamic reconfiguration core for . Integrate into . Now changing video modes and works with Xilinx FPGAs for the first time. Up to 1366x768@60. FullHD not yet. Hope for the new board revision.
    VGA works with 1080p.

  18. It turns out that it is reasonable to build a #uxn cpu on the lattice ICE40 family of #fpgas. They have 64K words of 16 bit memory, but one can access just he first 8 bits of each word.. One could use just half the memory, and access just one byte at each address.

  19. The #IWOMP best paper award 🥇 was awarded to Julian Brandner, Dr. Florian L. Mayer and Michael Philippsen for their paper entitled:

    "Multipurpose Cacheing to accelerate #OpenMP Target Regions on #FPGAs"

    Congratulations to all three! 👏 🤩

  20. @ariadne Eeyuppp!

    There's a reason literally did design their chips to emulate & with an architecture that isn't an a OS can even directly utilize.

    That being said, I'm confident that / will be a stepping stone till is mature enough to become mainstream (i.e. 20 Years) and cheap $10 allow running one at a performance that is on-par to then current SoCs and faster than any current-day can be.

  21. @ariadne Eeyuppp!

    There's a reason #Transmeta literally did design their chips to emulate #amd64 & #ix86 with an architecture that isn't an #ISA a OS can even directly utilize.

    That being said, I'm confident that #ARM / #ARM64 will be a stepping stone till #RISCV is mature enough to become mainstream (i.e. 20 Years) and cheap $10 #FPGAs allow running one at a performance that is on-par to then current #AppleSilicon SoCs and faster than any current-day #AMD64 can be.

  22. @ariadne Eeyuppp!

    There's a reason #Transmeta literally did design their chips to emulate #amd64 & #ix86 with an architecture that isn't an #ISA a OS can even directly utilize.

    That being said, I'm confident that #ARM / #ARM64 will be a stepping stone till #RISCV is mature enough to become mainstream (i.e. 20 Years) and cheap $10 #FPGAs allow running one at a performance that is on-par to then current #AppleSilicon SoCs and faster than any current-day #AMD64 can be.