#fpgafriday — Public Fediverse posts

I've just updated 🏝️Isle chapter 6 software. It's exciting to work on big designs and graphics engines, but building a usable computer is about the small things too. #FPGAFriday

https://github.com/projf/isle/tree/main/software/book/ch06

Board testing in advance of #FPGAFriday. The answer was 42. #ULX3S

Happy #FPGAFriday. I'm starting work on the next part of 🏝️Isle #FPGA Computer. I'm looking at input and the early system library. UTF-8 is surprisingly easy to decode in assembler; that's not some sort of humble brag, it's a testament to the design of UTF-8.

Happy #FPGAFriday. The hardware for the next installment of 🏝️ Isle #FPGA Computer is ready; now I'm working on docs, a new blog post, and an update for my sponsors. I'm aiming for a public update next Friday.

It can be difficult to let your imperfect creations feel the light of public scrutiny, but a project like this only thrives with the thoughts and contributions of many different people. 🙏

No FPGA for me today 😢, so I'd appreciate hearing about your hardware projects. #FPGAFriday

Hello hardware friends, it's a hot #FPGAFriday on the south coast. I'm writing tests and docs today, which is surprisingly satisfying if it's for a project you care about.

What are you working on today?

Got time to add more letters on the train yesterday. Happy #FPGAFriday.

It's about time I updated my recommended #FPGA links. Send me a suggestion this #FPGAFriday. 😊 https://projectf.io/recommended-fpga-sites/

Fearlessly generate your own clocks with Lattice ECP5 #FPGAs and Yosys. Includes worked examples for #ULX3S and easy to adapt to any dev board. Happy #FPGAFriday! @yosyshq https://projectf.io/posts/ecp5-fpga-clock/

It's the little differences... that drive you mad when supporting multiple #FPGA dev boards. 😢

Supporting #SPI flash on Arty S7 requires the STARTUPE2 primitive, while the A7 lets you access it via pin L16. #FPGAFriday

It's #FPGAFriday! Here's another peek at my current #FPGA project. This video shows Isle textmode, which supports coloured text (and backgrounds) and automatic scrolling. This capture is from Verilator/SDL, but it also runs on ECP5 and Xilinx 7 series FPGAs.

Sneak peek at the latest build of my new project for #FPGAFriday. I am currently testing it with my sponsors and will release it to everyone later this year. #FPGA #RISCV

My town has no water this weekend due to a burst pipe. I could use some #FPGAFriday inspiration right now. Show me your #FPGA projects, however big or small.

To get the ball rolling, here's a little video of a design I've been simulating.

Including a great typo. It is #FPGAFriday after all 😅

Again 😄 #FPGAFriday

Which #FPGA vendor do you prefer? Feel free to explain why in the comments. Thanks for every boost! #FPGAs #fpgafriday #fpgawars

Well, it is #FPGAFriday 😅

Where's our #FPGAFriday goodness, I hear you cry? You'll have to settle for a little bit of my forthcoming #riscv branch post. You want to be able to program all those RISC-V CPUs people keep developing, don't you?

I hope some of our wonderful #FPGA friends share their work too.

It's never too late to join the #FPGAFriday party! 100% homegrown graphics hardware and #riscv assembler. #FPGA dev board is Digilent Arty S7-25.

I'm going fixed-point for #FPGAFriday.
I'm experimenting with fixed-point multiplication on 32-bit RISC-V running on #fpga. This is my first attempt, but it seems to work for the few values I've tested. #riscv

I'm having "fun" with BRAM today. I hope you're doing something more exciting for #FPGAFriday.

It's #FPGAFriday already! This week, I've got some 1280x720 ULX3S graphics designs for you. Please give them a try and let me know how you get on. This is my first attempt at graphics on ECP5. #FPGA #RadionaOrg

Find the Verilog source & Makefile in git: https://github.com/projf/projf-explore/tree/main/graphics/fpga-graphics

Verilog has melted my brain a bit this week. This #FPGAFriday, I'm doing a bit of blog writing and looking for signs of spring. Are you doing anything different this week? #FPGA

I bet you have an #FPGA board in a drawer somewhere. Why not show it some love for #FPGAFriday? I'm dusting off my #RadionaOrg ULX3S and porting a graphics design with the @yosyshq open-source toolchain.

It's #FPGAFriday time! I'm working on bitmap graphics again this week. I also have a user patch for Project F Graphics to test and a new edition of RISC-V assembler to write. Are you doing any hardware design today? #FPGA

Why if it isn’t #FPGAFriday! Are you doing anything nice?

I’m getting back to bitmap graphics in Verilog. I have no exciting captures to share this week, just a video ram module.

A quick video update for #FPGAFriday.

I'm adding videos to my FPGA Graphics tutorials. You can find the first in Beginning FPGA Graphics: https://projectf.io/posts/fpga-graphics/

The video is 1280x720p60 DVI captured from a Nexys Video #FPGA dev board. Stay tuned for more videos soon. 📹

Here's a sneak peek of what I've been working on at Project F over the summer. HDMI capture from Nexys Video. #FPGAFriday #FPGA

Thank you to my sponsors for supporting this project 🙏 https://github.com/sponsors/WillGreen

More peeking soon. 😄

The #mch2022 badge is out for some good old #FPGAFriday fun!

Hello friends, COVID is slowly releasing its grip on me. For #FPGAFriday this week, I've given Project F a facelift.

Overly-thin body text is out, chunkier design is in. Plus, there's better mobile scaling and dark mode for those late-night design sessions. Have a nosey: https://projectf.io/tutorials/