#asynclogic — Public Fediverse posts

This is so much fun
https://tommythorn.github.io/tt08-maxbw/
#ASIC #tinytapeout #AsyncLogic #VLSI #tokenflow

Managed to push my first (barely) nontrivial async circuit through #TinyTapeout (bundled data 4-phase). Alas, I totally failed delay matching so I’m just using ridiculously large delays. I still have a couple of hours to improve it. #asic #asynclogic

Anyone here has an interest in or experience with #async #logic, like #mousetrap or Click?

#VLSI #AsynchrousLogic #AsyncLogic #ASIC

AHHHH! I finally got a ring oscillator working on #ECP5 with the #Yosys / #Nextpnr tool chain (I’m not complaining, I’m happy they exist and I’m doing something unorthodox)

You have to instantiate the inverters as LUTs directly *AND* you have to build the latest tools yourself (I had two different binaries segfault on the design).

https://github.com/YosysHQ/nextpnr/issues/1194#issuecomment-1684724413
#verilog #fpga #ncl #asynclogic

@reduz Alas “technical” covers cosmic areas, but I miss the usenet communities of yore, like comp.arch and comp.arch.fpga.

Always ready to discuss anything related to #microprocessorarchitecture, #microprocessorimplementation, #digitallogic, and especially “paths not followed”, like #asynclogic, #blockstructureISAs, etc

All the conference papers I want to read are pay-walled at $33 per article (thanks IEEE). That actually gets expensive quickly. Frustrating.
#AsyncLogic #VLSI #ASIC #Circuits

Watching a slightly older talk on #AsyncLogic. Delightful and had a few things I hadn't heard before:
https://youtu.be/Di-H333l1rQ

Fun! I wonder if Valve's Portal took inspiration from the Real World Potato computer (300 kHz @ 0.75 V) described in https://www.researchgate.net/publication/280493949_25_Years_Ago_The_First_Asynchronous_Microprocessor
KW: #AsyncLogic #VLSI

Reading "The Design of an Asynchronous MIPS R3000 Microprocessor" (https://www.researchgate.net/publication/2448388_The_Design_of_an_Asynchronous_MIPS_R3000_Microprocessor), a very different way to implement the classsic #RISC #pipeline
KW: #AsyncLogic #Architecture #processor

@matthewvenn "Efabless want all the submissions to run a top level timing check" So does this mean that anything that's not synchronous logic is out? Clearly async or domino say will not pass any of the timing tool they have. That's a pretty unfortunate restriction. #tinytapeout #asic #skywater #asynclogic #dominologic #digitaldesign #efabless

For #tinytapeout I want to produce some #asynclogic designs, the challenge being the limited size and IO of course. My initial thought would be something as trivial a ripple-carry adder loop, to meassure the avg. add/s, Interfacing with #synchronouslogic to get data on and off the scan chain. I can do #NCL easily enough but the higher performance alternatives all require custom cell and/or tricky delays for the #QDI #bundleddata. Anyone else working on something like this?

Shoot, I should probably have decorated with #asynclogic #tinytapeout #vlsi #verilog etc. Oh well, I'm new here. (I wonder if @mrg have made progress on async support in OpenRAM)