home.social
Sign in Create account

#asynclogic — Public Fediverse posts

Live and recent posts from across the Fediverse tagged #asynclogic, aggregated by home.social.

  1. Tommy Þ @[email protected] ·

    This is so much fun
    tommythorn.github.io/tt08-maxb
    #ASIC #tinytapeout #AsyncLogic #VLSI #tokenflow

    #asic #tinytapeout #asynclogic #vlsi #tokenflow
  2. Tommy Þ @[email protected] ·

    AHHHH! I finally got a ring oscillator working on #ECP5 with the #Yosys / #Nextpnr tool chain (I’m not complaining, I’m happy they exist and I’m doing something unorthodox)

    You have to instantiate the inverters as LUTs directly *AND* you have to build the latest tools yourself (I had two different binaries segfault on the design).

    github.com/YosysHQ/nextpnr/iss
    #verilog #fpga #ncl #asynclogic

    #ecp5 #yosys #nextpnr #verilog #fpga #ncl
  3. Tommy Þ @[email protected] ·

    @reduz Alas “technical” covers cosmic areas, but I miss the usenet communities of yore, like comp.arch and comp.arch.fpga.

    Always ready to discuss anything related to #microprocessorarchitecture, #microprocessorimplementation, #digitallogic, and especially “paths not followed”, like #asynclogic, #blockstructureISAs, etc

    #microprocessorarchitecture #microprocessorimplementation #digitallogic #asynclogic #blockstructureisas
  4. Tommy Þ @[email protected] ·

    @matthewvenn "Efabless want all the submissions to run a top level timing check" So does this mean that anything that's not synchronous logic is out? Clearly async or domino say will not pass any of the timing tool they have. That's a pretty unfortunate restriction. #tinytapeout #asic #skywater #asynclogic #dominologic #digitaldesign #efabless

    #tinytapeout #asic #skywater #asynclogic #dominologic #digitaldesign