mole99

wafer.space bare dies and CoB have arrived! 🎉

These are from my open-source FABulous FPGA, which was part of the first shuttle run.
It's a small FPGA with 480x LC, 6x MAC, 12x register files and 6x SRAM. The source files are available in the repository: https://github.com/mole99/gf180mcu-fabulous-fpga

#OpenSource #ASIC #FPGA

Greyhound is alive! 🐶

Last week, I posted about soldering my custom chips onto breakout boards. Now, I can finally say that Greyhound is working 🎉
If the video below doesn't work, you can also view it on Peertube: https://makertube.net/w/3rQ8a7WxTYcr1BQY9nCUat

I'm incredibly happy that Greyhound is no longer just theoretical, but that it can run examples on its FPGA in the real world 🤩

Greyhound repository: https://github.com/mole99/greyhound-ihp

#FPGA #ASIC

The next step is testing the chips. However, I need more time to setup the development environment. Stay tuned!

Thanks to @tnt for his soldering advice and for sharing his Tiny Tapeout IHP Breakout board, which I forked for the Greyhound Breakout PCB.

You can watch his bringup of the IHP 25A Tiny Tapeout chip here: https://www.youtube.com/watch?v=l0BNbLQ6u8g

#ASIC #OpenSource #Chip

And another chip submitted for tapeout - HeiChips 🎉

This one has been in the works for some time, but since the shuttle was canceled last fall, it was postponed to a later one.

It's an open-source chip featuring user projects created by participants of the HeiChips Summer School 2025 (https://heichips.github.io/). How cool is that?
The chip uses 9mm² of silicon on SG13CMOS and has been submitted to IHP's Low-Cost MPW shuttle (https://dk.ihp-microelectronics.com/OpenSourceRequest.php).

More below ⬇️

#FPGA #ASIC #OpenSource

LibreLane 3.0 has officially been released! 🎉

With this release, LibreLane finally has a logo! What's more, we now have a website showcasing LibreLane's capabilities, as well as a blog featuring development updates and announcements.

Read the full blog post here: http://www.librelane.org/blog/2026-03-25-website_release_3-0
LibreLane website: https://librelane.org/
Install LibreLane today: http://docs.librelane.org/

#FOSSi #LibreLane #OpenSource

A Tiny FABulous FPGA on Tiny Tapeout? It's more likely than you think!

Yesterday the TTIHP26a shuttle (https://app.tinytapeout.com/shuttles/ttihp26a) from #TinyTapeout has closed. In it, hundreds of incredible projects.
You can view the full shuttle and its designs here: https://app.tinytapeout.com/projects/3744

I had the opportunity to submit an FPGA, which I created using my FABulous LibreLane plugin. For this fabric, I developed a "tiny" tile library that better fits the constraints of Tiny Tapeout.

#FPGA #ASIC #TinyTapeout

I'm super happy that my PR for pad ring generation has been finally merged into LibreLane!
This allows you to implement a full chip, including the pad ring - who would have thought?

It is currently part of the LibreLane dev branch. Check out LibreLane here: https://github.com/librelane/librelane

#OpenSource #ASIC #LibreLane

Look what arrived on my doorstep today! 👏

A limited 1st edition collectible from the silicon vault.

#opensource #chips #tinytapeout

And this is an artistic PCB with the #TinyTapeout logo. However, what you may not realize at first glance - the pattern represents standard cells from a real chip. Coincidentally, my design from TT06 was picked for the background! You can find it here: https://github.com/mole99/tt06-tiny-shader

The files for generating the PCB from a GDS can be found here: https://github.com/htfab/tt-coaster

Thanks, Tamas!

Tiny Shader running on the GateMateA1-EVB with an open source toolchain 🎉

Originally this design was created for Tiny Tapeout, more information can be found here: https://github.com/mole99/tt06-tiny-shader

And if you want to see the TT06 chip in action, take a look at this thread: https://fosstodon.org/@mole99/113730908871370284

#FPGA #OpenSource #GateMate

I've got myself a new toy 🙌

This is the GateMateA1-EVB from Olimex, an FPGA dev board containing the GateMate CCGM1A1 with 20480 CPEs.

Now that initial nextpnr support for the chip has been merged, it is possible to program it with a fully open source toolchain 🎉
Synthesis with Yosys, place and route with nextpnr, bitstream packing with gmpack and finally upload to the board with openFPGALoader!

That meant I just had to get one, and two days later it arrived!

#FPGA #OpenSource #GateMate

If you are an advocate, supporter or just want to be a part of the Free and Open Source Silicon community, please join our new FOSSi Chat: https://fossi-chat.org

FOSSi Chat uses Matrix, an open protocol for decentralised, secure communications that is already the platform of choice for a large number of open source communities.

Let's make sure the community as a whole finds a new place where we can exchange ideas and work on great things!

#OpenSource #ChipDesign #FOSSi

They're finally here 🎉️ My very own chips from the Google-sponsored MPW-8 shuttle!
Open source chip design is real and here to stay.

The entire delivery includes bare dies, QFN packaged parts, daughter card assemblies, and a development board.
Many thanks to Efabless for managing the chip fabrication and delivery!

What's inside it? A simple RISC-V SoC with various peripherals, you can find my submission repository here: https://github.com/mole99/leosoc-sky130

#SKY130 #OpenMPW #ASIC

Today I submitted my final work report for Google Summer of Code 2023 🥳️

It's been an exciting three months, and I now have a much better understanding of what it means to contribute to an open source project. In the end, not only did I achieve the original goals of the project, but even a bit more.

Read on for more information about the project!

#GSoC #SKY130 #Verilog

Today is a good time to announce that I'm working on a GSoC project this summer! 🎉️

Google Summer of Code is a program from Google that sponsors students to work on open source projects during the summer months.

My project is called "Improving SDF support in Icarus Verilog" and I will explain what it is about in the following posts. But just as a heads up: it has to do with chip design.

#SKY130 #ASIC #OpenSource

And another project ACCEPTED for tapeout! I can't even comprehend how fast this is all happening.

This time I submitted a simple SoC: LeoSoC. https://platform.efabless.com/projects/1797

It contains a LeoRV32 core, 8 kB of Work RAM, another 8 kB of Video RAM and circuitry to output SVGA timings to a monitor.

I didn't really expect the project to be selected, since I submitted it the week before the deadline and the lottery is based on submission date. But it's a welcome surprise for sure 😃️

#ASIC #Verilog #SKY130

Waveform Generator ACCEPTED for MPW-7! 🎉

I finally got the news that one of my projects, a digital waveform generator, was accepted into the 7th Google-sponsored shuttle run for SKY130.

I will get the actual chips back in a couple of months and can't wait to test them!

Here is the list of projects on this run, you can find the Waveform Generator under Location E7, Slot 33:

https://foss-eda-tools.googlesource.com/third_party/shuttle/sky130/mpw-007/foundry/+/refs/heads/main/manifest-mpw-7.csv

#ASIC #Verilog #SKY130

Hi everyone! This is my very first toot :)

I would like to take the opportunity to present one of my latest projects:

A generic waveform generator implemented as an ASIC using the open source SKY130 PDK. With a bit of luck, this will be fabricated in the MPW-7 Shuttle through the Open MPW Program.

Development repository: https://codeberg.org/mole99/waveform-generator
ASIC implementation: https://codeberg.org/mole99/caravel_wfg
Project submission: https://platform.efabless.com/projects/1202

#ASIC #Verilog #SKY130

@yrabbit
Very exciting! But please take your time with everything, I will be happy to try it out once it's ready 😃️

By the way, I would be very interested in your thought process and the steps involved in implementing a new primitive like ELVDS in #apicula + #yosys + #nextpnr .
Maybe someday you could toot about this in detail?