#veryl — Public Fediverse posts

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module my_code #( param WIDTH: u32 = 640, param HEIGHT: u32 = 480, param CONSOLE_COLUMNS: u32 = WIDTH / 8, param CONSOLE_ROWS: u32 = HEIGHT / 8 ) ( clk: input clock, rst: input reset, px: input u32, py: input u32, hsync: input logic, vsync: input logic, col: input u32, row: input u32, char: output u32, foreground_color: output logic<24>, background_color: output logic<24>, uart_data: output logic<8>, uart_ready: input logic, uart_valid: output logic ) { var frame_counter: u32; var old_vsync: logic; var red: logic<8>; var green: logic<8>; var blue: logic<8>; always_comb { red = (col * 4) as u8; green = py as u8; blue = frame_counter as u8; background_color = {red, green, blue}; foreground_color = 24'hff_ff_ff; char = 0; if(row == 10) { if(col == 5) { char = 8'h56; } if(col == 6) { char = 8'h65; } if(col == 7) { char = 8'h72; } if(col == 8) { char = 8'h79; } if(col == 9) { char = 8'h6c; } } uart_data = 0; uart_valid = 0; } always_ff (clk, rst) { if_reset { frame_counter = 0; old_vsync = 0; } else { if(!vsync && old_vsync) { frame_counter = frame_counter + 1; } old_vsync = vsync; } } }

Success!

UART Output

UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1024242884.2%TRELLIS_FF157242880.6%TRELLIS_IO111975.6%
TimingClockAchievedConstraint$glbnet$clkp39.77 MHz25 MHz$glbnet$clkt321.34 MHz250 MHz
Code

module my_code #(
    param WIDTH: u32 = 640,
    param HEIGHT: u32 = 480,
    param CONSOLE_COLUMNS: u32 = WIDTH / 8,
    param CONSOLE_ROWS: u32 = HEIGHT / 8
) (
    clk: input clock,
    rst: input reset,

    px: input u32,
    py: input u32,
    hsync: input logic,
    vsync: input logic,

    col: input u32,
    row: input u32,

    char: output u32,
    foreground_color: output logic<24>,
    background_color: output logic<24>,

    uart_data: output logic<8>,
    uart_ready: input logic,
    uart_valid: output logic
) {
    var frame_counter: u32;
    var old_vsync: logic;

    var red: logic<8>;
    var green: logic<8>;
    var blue: logic<8>;

    always_comb {
        red   = (col * 4) as u8;
        green = py as u8;
        blue  = frame_counter as u8;

        background_color = {red, green, blue};
        foreground_color = 24'hff_ff_ff;

        char = 0;
        if(row == 10) {
            if(col == 5) { char = 8'h56; }
            if(col == 6) { char = 8'h65; }
            if(col == 7) { char = 8'h72; }
            if(col == 8) { char = 8'h79; }
            if(col == 9) { char = 8'h6c; }
        }

        uart_data = 0;
        uart_valid = 0;
    }

    always_ff (clk, rst) {
        if_reset {
            frame_counter = 0;
            old_vsync = 0;
        } else {
            if(!vsync && old_vsync) {
                frame_counter = frame_counter + 1;
            }
            old_vsync = vsync;
        }
    }
}

#FPGA #Icepi-Zero #HDL #Veryl

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module my_code #( param WIDTH: u32 = 640, param HEIGHT: u32 = 480, param CONSOLE_COLUMNS: u32 = WIDTH / 8, param CONSOLE_ROWS: u32 = HEIGHT / 8 ) ( clk: input clock, rst: input reset, px: input u32, py: input u32, hsync: input logic, vsync: input logic, col: input u32, row: input u32, char: output u32, foreground_color: output logic<24>, background_color: output logic<24>, uart_data: output logic<8>, uart_ready: input logic, uart_valid: output logic ) { var frame_counter: u32; var old_vsync: logic; var red: logic<8>; var green: logic<8>; var blue: logic<8>; always_comb { red = (col * 4) as u8; green = py as u8; blue = frame_counter as u8; background_color = {red, green, blue}; foreground_color = 24'hff_ff_ff; char = 0; if(row == 10) { if(col == 5) { char = 8'h56; } if(col == 6) { char = 8'h65; } if(col == 7) { char = 8'h72; } if(col == 8) { char = 8'h79; } if(col == 9) { char = 8'h6c; } } uart_data = 0; uart_valid = 0; } always_ff (clk, rst) { if_reset { frame_counter = 0; old_vsync = 0; } else { if(!vsync && old_vsync) { frame_counter = frame_counter + 1; } old_vsync = vsync; } } }

Success!

UART Output

UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1024242884.2%TRELLIS_FF157242880.6%TRELLIS_IO111975.6%
TimingClockAchievedConstraint$glbnet$clkp39.77 MHz25 MHz$glbnet$clkt321.34 MHz250 MHz
Code

module my_code #(
    param WIDTH: u32 = 640,
    param HEIGHT: u32 = 480,
    param CONSOLE_COLUMNS: u32 = WIDTH / 8,
    param CONSOLE_ROWS: u32 = HEIGHT / 8
) (
    clk: input clock,
    rst: input reset,

    px: input u32,
    py: input u32,
    hsync: input logic,
    vsync: input logic,

    col: input u32,
    row: input u32,

    char: output u32,
    foreground_color: output logic<24>,
    background_color: output logic<24>,

    uart_data: output logic<8>,
    uart_ready: input logic,
    uart_valid: output logic
) {
    var frame_counter: u32;
    var old_vsync: logic;

    var red: logic<8>;
    var green: logic<8>;
    var blue: logic<8>;

    always_comb {
        red   = (col * 4) as u8;
        green = py as u8;
        blue  = frame_counter as u8;

        background_color = {red, green, blue};
        foreground_color = 24'hff_ff_ff;

        char = 0;
        if(row == 10) {
            if(col == 5) { char = 8'h56; }
            if(col == 6) { char = 8'h65; }
            if(col == 7) { char = 8'h72; }
            if(col == 8) { char = 8'h79; }
            if(col == 9) { char = 8'h6c; }
        }

        uart_data = 0;
        uart_valid = 0;
    }

    always_ff (clk, rst) {
        if_reset {
            frame_counter = 0;
            old_vsync = 0;
        } else {
            if(!vsync && old_vsync) {
                frame_counter = frame_counter + 1;
            }
            old_vsync = vsync;
        }
    }
}

#FPGA #Icepi-Zero #HDL #Veryl