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1000 results for “sparse_array”

  1. Habr @[email protected] ·

    SAE: введение, пояснение и код

    Привет, друзья! В прошлой статье мы разобрали идею применения автоэнкодеров к трансоформерам. Там весь наш pipeline проходил на идее сжатия признакового пространства так, чтобы поделить кошек и собак. Но что делать, если у нас не задача классификации, а задача next token prediction? Да и признаки не соответствуют "собакам" и "кошкам", а охватывают все богатство естественного языка... Ответ сообщества сейчас такой — давайте использовать SAE. Как? Разбираем основы в статье.

    habr.com/ru/articles/983474/

    #Sparse_Autoencoders #explainable_ai

    #explainable_ai #sparse_autoencoders
  2. Habr @[email protected] ·

    SAE: введение, пояснение и код

    Привет, друзья! В прошлой статье мы разобрали идею применения автоэнкодеров к трансоформерам. Там весь наш pipeline проходил на идее сжатия признакового пространства так, чтобы поделить кошек и собак. Но что делать, если у нас не задача классификации, а задача next token prediction? Да и признаки не соответствуют "собакам" и "кошкам", а охватывают все богатство естественного языка... Ответ сообщества сейчас такой — давайте использовать SAE. Как? Разбираем основы в статье.

    habr.com/ru/articles/983474/

    #Sparse_Autoencoders #explainable_ai

    #sparse_autoencoders #explainable_ai
  3. :awesome:🐦‍🔥nemo™🐦‍⬛ 🇺🇦🍉 @[email protected] ·

    #signal To add post‑quantum security, Signal introduced the Sparse Post‑Quantum Ratchet #SPQR , which runs alongside the existing #DoubleRatchet

    signal.org/blog/spqr/

    The protocol now effectively combines three components: the symmetric ratchet, the classical DH ratchet, and the new post‑quantum ratchet (SPQR).

    pqshield.com/diving-into-signa

    #TrippleRatchet

    blog.quarkslab.com/triple-thre

    #doubleratchet #spqr #signal #trippleratchet
  4. Charnock @[email protected] ·

    Some weird joint called Minehead circa 1934. What I like about the Ward Lock maps of this era is their sparse nature and clean lines really lends them to being base maps for scenarios. They aren't in any sense cluttered.

    @vortiwife and I work from different ends of the spectrum on this sort of thing and I find that rather fascinating. This is obviously an aesthetic choice thing and not because I am dog-awful with GIS systems.

    😇

    #ttrpgmap

    #ttrpgmap
  5. Eugene @[email protected] ·

    🌳 I am finalizing a tool that allows for a rapid and accurate assessment of the green infrastructure in any Calgary community. This isn't just "green color" on a map—my algorithm recognizes the differences in the quality and structure of the urban environment.

    What we can quantify right now:
    🔹 Lawn (Grasses, low shrubs): Open spaces that tend to dry out and heat up quickly during summer.
    🔹 Park (Sparse Canopy): Scattered groups of trees in parks and private yards.
    🔹 Forest (Dense Canopy): The "lungs" of a neighborhood, characterized by closed canopies and thick undergrowth. These areas provide vital protection against urban heat.

    ❗ Why does this matter?
    Using Inglewood as an example (see the chart), we can see that "dense forest" covers only about 5% of the area. This is a critical indicator of the territory's climate resilience.

    #Calgary #UrbanForestry #CityPlanning #DataScience #Inglewood #CalgaryEnvironment #GIS #RemoteSensing #MachineLearning #Inglewood #Rstats #GreennesOfCalgary #YYC #yycPlanning

    #datascience #rstats #yyc #calgary #machinelearning #gis
  6. neddyo @[email protected] ·

    Tonight: wildly dark, almost sinister Irish folk drones from Lankum side project One Leg One Eye. Sparse vocals, traditional instruments, and deep electronics and synth. Littlefield is literally trembling. It's a mood, for sure. Heavy.

    #nycfreaks #livemusic #brooklyn #irish #folk #lankum

    #nycfreaks #livemusic #brooklyn #irish #folk #lankum
  7. Propel a Cure 4 Crohn’s @[email protected] ·

    Many studies have explored the role of bacteria in #IBD, but research has been more sparse on viruses, which may hold valuable clues to disease triggers and development.

    #crohnsdisease #crohns #CrohnsColitis #crohnsandcolitis #inflammatoryboweldisease #virome #viruses

    #ibd #crohnsdisease #crohns #crohnscolitis #crohnsandcolitis #inflammatoryboweldisease
  8. Propel a Cure 4 Crohn’s @[email protected] ·

    Many studies have explored the role of bacteria in #IBD, but research has been more sparse on viruses, which may hold valuable clues to disease triggers and development.

    #crohnsdisease #crohns #CrohnsColitis #crohnsandcolitis #inflammatoryboweldisease #virome #viruses

    #ibd #crohnsdisease #crohns #crohnscolitis #crohnsandcolitis #inflammatoryboweldisease
  9. Bigarella @[email protected] ·

    Il terreno della lotta armata è perfettamente sconosciuto alla maggioranza degli operai

    La nascita dei Gruppi d’Azione Patriottica riflette un’oculata strategia politico-militare del Partito Comunista mirante alla polarizzazione su un doppio binario della lotta contro il fascista ed il tedesco: da un lato la guerriglia e la lotta armata in mano ad un’ardita avanguardia operaia, dall’altro lo scontro economico-rivendicativo nelle fabbriche. E’ una scelta di per sé obbligata, che diverrà inevitabile sulla scia del massiccio sciopero dei sette giorni del dicembre ’43 e di quello insurrezionale del marzo ’44. In quest’ultimi due casi, l’assenza del contributo e del supporto gappista attenuerà consistentemente la forza e la portata delle agitazioni operaie. Già dal settembre, Francesco Scotti ed Egisto Rubini assistiti da Giordano Cipriani ed insieme ad alcuni operai milanesi e sestesi ricevono l’incarico di costituire i primi gruppi d’azione patriottica. Il compito si rivelerà arduo già dai primi mesi per una serie di ragioni. Innanzitutto il terreno della lotta armata è perfettamente sconosciuto alla maggioranza degli operai. Pur ricompattata negli scioperi di marzo ed attestata una ferma e decisa volontà d’azione, la classe operaia è politicamente ed ideologicamente impreparata. Il ricordo del Rinascimento, dell’Unità d’Italia e del biennio rosso 1919-’20 è sì vivo, ma la congiuntura è radicalmente differente e sfavorevole. Quella che si troverà a combattere non sarà una guerra popolana di stampo risorgimentale, ma una guerriglia pianificata scientificamente con bersagli ed obiettivi politici predefiniti. Seppur la presenza comunista nelle fabbriche milanesi sia preminente (soprattutto alla Magnaghi, Breda e alla Falck di Sesto San Giovanni), le difficoltà per l’arruolamento e l’inquadramento si presenteranno ardue fin da primissimi giorni. Alle prese con i bisogni e le necessità più impellenti e con le sopracitate condizioni lavorative a cui si aggiunge il rischio della deportazione o del lavoro alla Todt <12, l’operaio già da subito si dimostra reticente. Gravano i pesanti interrogativi riguardo la soluzione della guerra, che pur sfavorevole all’Asse, non presenta sicure certezze e conclusioni. Pesano inoltre gli indiscriminati arresti e le deportazioni, le feroci repressioni delle SS e la rinascita del fascismo che si nutre d’acredine e vendetta nei confronti di chi l’ha tradito e delle « cricche privatistiche collegate alla mentalità giudaico – massonica – borghese del capitalismo, dell’intellettualismo e del comunismo». La fabbrica garantisce, nella migliore delle ipotesi, a stento un piatto di minestra al giorno, un lavoro precario (seppur scarsamente remunerato) e l’ausweis, il lasciapassare tedesco per i lavoratori addetti alla produzione bellica, esonerati dalla chiamata alle armi, dalle deportazioni e dalle retate.
    Da qui la decisione del Partito Comunista di indirizzare la lotta attraverso una chiara separazione dei compiti: l’operaio e il gappista. Il primo, in fabbrica, a capo delle lotte prettamente economico-rivendicative con duplici obiettivi da perseguire: strappare all’industriale e al tedesco aumenti salariali e contemporaneamente far luce univocamente sul ruolo e sulle responsabilità degli stessi, smascherando gli interessi coincidenti. Altro obiettivo di non minore importanza è quello di riuscire a spezzare il blocco moderato-conservatore, attirando a sé la piccola e media borghesia ed isolando gli imprenditori collaborazionisti. Così facendo si impedisce al neo costituito fascismo, di presentarsi agli occhi della gente come unico garante dell’ordine e della riappacificazione come invocato dal filosofo Giovanni Gentile.
    Sulla sponda opposta c’è il gappista. Facente parte di nuclei ristrettissimi, comunisti, provenienti dalle fabbriche e, pertanto, prevalentemente operai, rappresenta la punta avanzata della lotta armata. Con alle spalle un drammatico passato, ha un percorso comune a tutti i militanti comunisti dell’epoca. L’esperienza della guerra di Spagna, la resistenza francese nei Francs-Tireurs et Partisans, la scuola politica a Mosca, l’esilio a Ventotene, la militanza nel neonato Partito Comunista del ’21, le condanne del Tribunale Speciale e gli anni di prigione, le persecuzioni. Vive nella clandestinità e nella vigilanza più assoluta, praticando una lotta armata di stampo terroristico.
    Occorre precisare che il gappismo e il gappista non hanno nulla a che vedere con la concezione moderna di largo senso comune del “terrorismo” e del “terrorista”. L’accezione moderna del termine “terrorista” si è caricata di particolari connotazioni negative e sinistre, rifacendosi soprattutto ai sanguinosi anni ’70 italiani. Attraverso i cosiddetti anni di piombo e la galassia delle formazioni antagoniste extraparlamentari che hanno abbracciato la lotta armata quali le Brigate Rosse, i Proletari Armati per il Comunismo, Prima Linea, il terrorismo nero di Ordine Nuovo e Terza Posizione ed accanto a fenomeni di portata europea quali le RAF in Germania, con il termine terrorista si è definito colui che fa della violenza il principale strumento di lotta politica. Quest’ultimo colpisce con determinate e mirate azioni più che l’uomo o l’istituzione in sé, ciò che essi incarnano e rappresentano politicamente, mirando alla destabilizzazione dello Stato attraverso l’instaurazione di una fantomatica rivoluzione per mano di pochi eletti.
    Giorgio Bocca dà una spiegazione illuminante e chiarificatrice riguardo le ragioni e gli indirizzi delle azioni gappistiche, una delucidazione essenziale che ci aiuta a riflettere e a praticare i dovuti distinguo: “Il terrorismo nelle città mira a effetti militari e politici ed è un atto di moralità rivoluzionaria. Se si accetta il principio morale e rivoluzionario della ribellione armata contro la legalità iniqua, bisogna arrivare al terrorismo cittadino. La resistenza è indivisibile, la guerra popolare, guerra di tutti, e non può tollerare isole di privilegio e di ingiusto rispetto, che si uccida, si torturi, si incendi nei villaggi di montagna e nei quartieri operai mentre le enclaves della borghesia cittadina restano tranquille e, dentro, tranquilli gli oppressori.” <13 Nel momento in cui gli spazi di agibilità politica e l’esercizio del dissenso sono preclusi e criminalizzati, la democrazia soppressa, alla presenza di un oppressore che dispone della vita e della morte di ciascuno con le città in stato d’assedio, l’ultima tappa obbligata è quella della lotta armata. Unico strumento di difesa disponibile, unico baluardo contro la totale depravazione umana, morale e sociale. Percorso tra l’altro comune ai movimenti di liberazione algerino, vietnamita, cubano e alla resistenza francese.
    Genesi: come, dove e in quanti
    La prima squadra di quella che poi diverrà la 3^ GAP è formata da quattro operai rappresentanti le più importanti fabbriche sestesi: Validio Mantovani (Nino, Ninetto, Barbisìn) dalla Saspa Pirelli, Carlo Camesasca (Barbisùn) dalla Ercole Marelli, Vito Antonio La Fratta (Totò) dalla Falck, Renato Sgobaro (Giulio, Lupo Mannaro) dalla Breda. Sono diretti da Egisto Rubini e Cesare Roda. Tutti alle prime armi con scarsissima dimestichezza dell’attività che andranno ad intraprendere, tutti provenienti dalla fabbrica e non più giovanissimi. Bisogna rompere il ghiaccio, arrischiare le prime azioni e i primi colpi, sperimentare tattiche e strategie, temprare lo spirito, razionalizzare l’istinto, controllare le reazioni emotive. Detto – fatto, il 4 ottobre del 1943, avendo incrociato per strada, in bicicletta, il sergente maggiore squadrista Visentin, individuo molto odiato per aver fatto “assaggiare” lo staffile a molti operai, lo attendono sulla via del ritorno e lo giustiziano. C’è esitazione, non ci si decide su chi dovrà sparare per primo, quindi si opta per il capo, Ninetto, che aprirà il fuoco. Azione riuscita e fuga veloce in bicicletta.
    Dopo aver eliminato un tenente della milizia a Casatenovo, i sestesi ricevono l’ordine di giustiziare il capitano (poi maggiore) della XXV legione della Guarda Nazionale Repubblicana, Gino Gatti, un torturatore di partigiani. Il compito si presenta sin dal principio non facile: il soggetto non è abitudinario e i suoi spostamenti ed i suoi orari sono tutt’altro che ripetitivi. Pur di portare a termine la loro missione, i gappisti decidono di affidarsi all’improvvisazione sfruttando l’occasione propizia e confidando nella buona sorte. Ma tutto ciò mal si concilia col rigore ed il militarismo scientifico della guerriglia armata in città. Gatti, attaccato di fronte alla Villa Reale di Monza, riuscirà a sopravvivere all’agguato riportando gravissime ferite. Pur nell’azzardata azione dei sestesi, l’operazione è tutt’altro che un insuccesso.
    Dimostrando di poter colpire il nemico nelle sue principali roccaforti, si spezza la sicurezza psicologica dei fascisti infondendo fiducia in quelle sacche della popolazione che, seppur antifasciste, non concretizzano la loro opposizione al risorto regime. Queste primissime esitazioni, queste improvvisate gesta temprano il gappista autodidatta e ne maturano l’addestramento.
    In ottobre il quadro organizzativo si perfeziona ulteriormente con l’arrivo di Vittorio Bardini, studente politico a Mosca ed ex combattente nella guerra di Spagna. Ilio Barontini, livornese, artificiere, raro caso di volontario e combattente in azioni d’aiuto agli abissini durante l’aggressione fascista all’Etiopia, comandante delle Brigate Garibaldi in Spagna, lo mette subito in contatto con Rubini, Roda e Francesco Scotti ispettore generale delle neonate brigate Garibaldi. Al momento è alquanto prematuro parlare di una brigata Garibaldi de facto; al contrario delle inesatte ricostruzioni, si presentano, sparse per le diverse zone della città, delle squadre al cui comando non v’è un comandante ed un commissario politico. E’ il comitato militare del PCI Lombardia, quindi Bardini, Scotti e Roda a capitanare e dirigere le neo costituite cellule. Tutte comunque raggruppate nel 17° distaccamento GAP Gramsci. Un triunvirato, i cosiddetti “triangoli militari di partito”: un responsabile generale (Bardini), un responsabile dei servizi tecnici (Roda) e in ultima istanza un responsabile militare delle azioni (Rubini).
    [NOTE]
    12 Organizzazione Todt: grande impresa di costruzioni che operò in Germania ed in tutti i paesi occupati della Wehrmacht, dedita al reclutamento di mano d’opera da utilizzare nella costruzione di strade, ponti e lavori di fortificazione militare (Linea Sigfrido, Linea Gustav, Linea Gotica). Contava all’incirca 1.500.000 lavoratori, di cui la maggior parte prigionieri di guerra. Sfruttata più volte da renitenti alla leva e partigiani per sfuggire alla deportazione o ai bandi di chiamata alle armi.
    13 G. Bocca, Storia dell’Italia partigiana, 1966, p. 145
    Giorgio Vitale, L’altra Resistenza. I GAP a Milano, Tesi di laurea, Università degli Studi di Milano, Anno Accademico 2008-2009

    #1943 #1944 #armata #azione #CesareRoda #comunisti #EgistoRubini #fabbriche #fascisti #GAP #GiorgioVitale #gruppi #IlioBarontini #lotta #Milano #operai #ottobre #partigiani #Patriottica #scioperi #SestoSanGiovanniMI #tedeschi
    #tedeschi #sestosangiovannimi #scioperi #patriottica #partigiani #ottobre
  10. AIagent.at 🤖 AI News @[email protected] ·

    Liquid AI releases LFM2-24B-A2B, a hybrid architecture that blends attention with convolutions to solve modern LLM scaling bottlenecks: Using a 1:3 ratio of attention to gated convolutions with sparse MoE, the model achieves 24B parameters while only activating 2.3B, fitting in 32GB RAM for local deployment. marktechpost.com/2026/02/25/li #AIagent #AI #LLM #GenAI #LiquidAI

    #aiagent #ai #llm #genai #liquidai
  11. Casey Primozic / ameo @[email protected] ·

    I've been making more progress on the sparse RNN training and visualization

    Working on the blog post now. Lots of cool stuff went into this from custom activation functions, custom regularizers, the new machine learning library #tinygrad, #graphviz, #webgl, and more

    Here, it learned a gated 3-state state machine coupled with other neurons that perform a different boolean operation depending on the current state

    #rnn #machinelearning

    #tinygrad #graphviz #webgl #rnn #machinelearning
  12. Martin Schäfer @[email protected] ·

    Sorting through my notes again, and hands-down the most interesting and thought-provoking talk I heard at the recent #DGKL conference in Osnabrück was @mhuening "Zur Morphologisierung sozialer Bedeutung". Unfortunately my notes are rather sparse: crazy examples of #German "-isierung" #derivation with completely different contextual meanings, and pointers to work by Alastair Pennycook (After words and Language assemblages, both 2024) and the Penelope Eckert paper on the Limits of meanings (doi.org/10.1353/lan.2019.0072) which I have wanted to read for a while now ... :)

    #dgkl #german #derivation
  13. Drop Bear @[email protected] ·

    The #Lehrmann family is reportedly prominent in the Southern US @martintheg
    In Australia, I've seen reference to the #Tapscott family, who are influential in northern NSW and southern Qld. Evidence of that connection is increasingly hard to find, but the record hasn't been completely scrubbed. Bruce's own online presence is remarkably sparse.
    independentaustralia.net/polit
    It does seem that there were big plans for Bruce.
    @Bot4Sale

    #AusPol

    #lehrmann #tapscott #auspol
  14. JMLR @[email protected] ·

    'Distributed Sparse Regression via Penalization', by Yao Ji, Gesualdo Scutari, Ying Sun, Harsha Honnappa.

    jmlr.org/papers/v24/21-1333.ht

    #lasso #sparse #penalized

    #lasso #sparse #penalized
  15. JMLR @[email protected] ·

    'MARS: A Second-Order Reduction Algorithm for High-Dimensional Sparse Precision Matrices Estimation', by Qian Li, Binyan Jiang, Defeng Sun.

    jmlr.org/papers/v24/21-0699.ht

    #sparse #matrix #penalized

    #sparse #matrix #penalized
  16. Kevin's Blog @[email protected] ·

    TD4 4-bit DIY CPU

    I was looking for DIY CPU projects, as I like kits that help me think at the lowest level of processing. It helps keep me grounded in how far technology has come over the years.

    • Part 1 – Introduction, Discussion and Analysis
    • Part 2 – Building and Hardware
    • Part 3 – Programming and Simple Programs
    • Part 4 – Some hardware enhancements
    • Part 5 – My own PCB version
    • Part 6 – Replacing the ROM with a microcontroller
    • Part 7 – Creating an Arduino “assembler” for the TD4
    • Part 8 – Extending the address space to 5-bits and an Arduino ROM PCB

    Some of the options that I know about, that actually come as kits you can buy and are interesting for me for DIY computers are:

    But I wanted to go further down and actually find something that lets me build a simple CPU from gates. Here there are several options too:

    Whilst I’d love to build Ben Eater’s 8-bit CPU, the kit as provided is too much of an outlay for me. It is ~$300 – I mean, good for what you get and all the knowledge, but it is a solderless breadboard kit and that isn’t really what I’m after. The Gigatron is a distinct possibility that I’ll come back to at some point I think.

    NAND to Tetris is excellent, and I have their book, but it is all emulated or virtualised, which does allow for all the scaling required for an (arguably) actually useful device, but isn’t designed to be built in actual hardware.

    But the TD4 is really interesting. It is available as a PCB and components for approx £25 on Aliexpress and based on an open source design that shows the basic operation of a 4-bit CPU.

    The “deluxe” kit mentioned above is a lot more expensive ~£120 but has all signals broken out to LEDs which, whilst is an awful lot of soldering, does looks incredibly impressive! The MiniMax is an evolution of the TD4 and kits for that are around £120. In fact, searching on Tindie and Hackaday.io for “TD4” will surface a few other DIY projects and even kits to purchase.

    The TD4 does seem to fit the bill for me as an inexpensive kit to try. The downside is that documentation for it (in English) is pretty sparse.

    The TD4 project itself is by “wuxx” an embedded engineer from HangZhou and much of the documentation is in Chinese. It is based on a Japenese book by Kaoru Tonami called “how to build a CPU” which can be found for ~£50 online, but as I don’t know Japanese either is unlikely to help me very much.

    There are some sources of information that others have put together though, so I’m going to be using those as a starting point along with whatever I can figure out myself:

    This post is my own “thinking out loud” as I work through the various parts to see how they work.

    Basic Architecture

    This is a 4-bit computer, with a 4-bit data bus, 4-bit commands, and a 4-bit address bus.

    There is a block diagram on GitHub:

    The fundamental process is as follows. For each “tick” of the computer:

    • An OpCode is read from the ROM using the current 4-bit address (0 to 15) from the program counter.
    • Each ROM entry is an 8-bit word with 4-bits as a command and 4-bits as data for the command.
    • The data selector determines a 4-bit INPUT value. This can come from one of the two registers (A or B); or a set of four switches for the IN register; or be set to zero.
    • This goes to the adder which adds it with the immediate data from the ROM (which could of course be zero).
    • The OUTPUT of the adder can go to either of the two registers (A or B), an OUT register which is hooked up to four LEDS, or the program counter register to create a “jump”.

    I’ll pull apart the different parts of the CPU in the following sections.

    ROM Format

    Each 8-bit word in the 16-byte ROM has the following format:

    • 4 command bits
    • 4 immediate data bits

    Instruction Decoding

    The 4 command bits from each ROM instruction have to be turned into the various selection signals to activate different parts of the CPU.

    There is a table from GitHub again:

    The explanation in Japanese translates (apparently) to:

    “Explanation: The SEL_B and SEL_A signals select the ALU data source, while #LOAD0-#LOAD3 select the ALU data destination. More formally, they control the source and destination operands of instructions, respectively.”

    From this we can note the following:

    • There is no instruction for 1000,1010,1100 or 1101.
    • Instruction 1110 appears twice, and the selectors set are dependent on the state of the C (carry) flag.
    • Some instructions act on immediate data, others assume it will be 0.

    The LOAD# have the following meanings in the system:

    • LOAD#0 – Register A (A)
    • LOAD#1 – Register B (B)
    • LOAD#2 – OUTPUT (OUT)
    • LOAD#3 – Program counter (PC)

    The actual decoding happens in two parts: input selection; and output selection.

    Registers

    The system has four registers, each formed from a 74HC161 “presettable, synchronous, 4-bit binary counter”. There are two general purpose registers: A and B. There is one output register, whose contents drive the state of four LEDs. And there is a program counter. Here is the schematic for register A:

    P0-P3 come from the output of the adder directly. RST and CLK are hopefully self-explanatory. For the A and B registers, Q0-Q3 go into the INPUT selection section (see later). For the OUTPUT register, these go directly to LEDs. For the program counter, these go into the ROM address logic (again more on that later).

    The relevant operation of the 161 is described in the datasheet:

    “The outputs (Q0 to Q3) of the counters may be preset HIGH or LOW. A LOW at the parallel enable input (PE) disables the counting action and causes the data at the data inputs (D0 to D3) to be loaded into the counter on the positive-going edge of the clock… A LOW at the master reset input (MR) sets Q0 to Q3 LOW…”

    So on reset the outputs are all 0. When PE goes LOW, on the next clock pulse, the value on the inputs (P0-P3) is loaded into the counter and reflected on Q0-Q3. However, because CET and CEP are LOW the counter won’t actually count any further.

    The program counter is a bit special, in that it is actually allowed the count by having CET and CEP set HIGH. This allows it to step through the instructions on a clock pulse.

    In this case Q0-Q3 go off to the ROM address decoding, which I’ll come to in a moment.

    INPUT Selection

    There are two SELECT lines select the INPUT data as follows:

    SEL_BSEL_ASOURCE00Register A (A)01Register B (B)10INPUT (IN)11Zero value (0)

    Input selection is handled by two 74HC153 dual 4-input multiplexers. Two are required as there are four data lines to be switched, and they all have one of four options to switch between based on the SELECT lines above.

    Here is the relevant part of the schematic.

    On the left are the three sets of four data signals that come from the A, B and IN inputs. D0 from each of the inputs goes to U7/1Cn; D1 goes to U7/2Cn; D2 to U8/1Cn; and D3 to U8/2Cn. Notice that the fourth set of data signals (U7/1C3, 2C3 and U8 1C3, 2C3) are connected directly to GND for the “zero” INPUT state (SEL_A=1, SEL_B=1).

    On the right, the two pairs of outputs make up the four data lines to feed into the adder section.

    So where does the SEL_A and SEL_B signals come from? From the schematic, we can see:

    • SEL_A = D4 OR D7 (via U10B – one of the 74HC32 2-input OR gates)
    • SEL_B = D5

    We can start to explain why some of the instruction combinations don’t exist (or at least, aren’t distinct) as we can see that SEL_A depends on either D4 or D7.

    OUTPUT Selection

    The OUTPUT selection is a little more complicated. As previously mentioned, there are four destinations: the two registers, the OUTPUT register, and the program counter.

    Each register has a /PE (“parallel enable input”) signal which is active low. These are individually fed by the output of the LOAD# logic.

    The three signals at the bottom are D6, D7 and D4. The lone signal top left is the carry (/C) flag, and the four outputs top right are the four LOAD# signals which feed directly into the /PE pins of the four registers.

    So from this we deduce the following relationships:

    • Reg A LOAD0 HIGH = D6 OR D7 – so LOAD0 is only active (LOW) when both D6 and D7 are LOW.
    • Reg B LOAD1 HIGH = NOT D6 OR D7 – so LOAD1 is only active (LOW) when D6 is HIGH and D7 is LOW.
    • OUT LOAD2 LOW = NOT D6 AND D7 – so LOAD2 is only active (LOW) when D6 is LOW and D7 is HIGH.
    • PC LOAD3 LOW = D6 AND D7 AND (D4 OR /C) – so LOAD3 is only active (LOW) when both D6 and D7 are HIGH and either D4 is HIGH or the carry signal (/C) is LOW.

    This effectively means that D6 is used to select between registers A and B when D7 is LOW; and between OUT and PC when D7 is HIGH (subject to either D4 or the /C signal too in the case of PC).

    Once again, we can see that there is some redundancy in the system for certain combinations of D4 to D7.

    ROM Address Decoding

    The 4-bit output from the program counter is effectively a 4-bit address bus. This gets turned into a set of selection signals to select which “byte” of the ROM should be active.

    This simply uses a 74HC154, 4 to 16 line decoder, meaning that a 4-bit number goes in and one of 16 corresponding outputs goes LOW whilst the rest remain HIGH. There is no memory address or matrix handling – there is literally one control line per “memory” location.

    The ROM itself is a set of 16 8-way DIP switches and diodes, so once its control signal is active (LOW) then those DIP switches become relevant on the data bus. Here is the last location and data bus logic. Note that all data signals are pulled HIGH by default, so will only be read as LOW if the DIP switch connects it to LOW via the diode, and that is only possible if that DIP block is selected from the 4 to 16 line decoder.

    The 74HC540 is an inverting line buffer, turning any active LOW DIP switch settings into HIGH signals on the command/data bus. Recall that D0-D3 represent immediate data and D4-D7 represent command logic.

    The Adder (ALU)

    The arithmetic logic unit (ALU) for this CPU is a simple adder. A 74HC283 is a 4-bit binary full adder. “full” in that it supports 4-bit add-with-carry functionality, although in this design, carry is only used on the output stage – it doesn’t form part of the input addition.

    A0-A3 comes from the INPUT selection circuitry, so can represent either register A or B, the state of the IN switches, or a fixed zero (0) value. B0-B3 comes directly from D0-D3 from the ROM contents as selected by the ROM addressing logic.

    The COUT (carry) flag goes into a flip-flop and the active LOW version of the output is used as the carry flag in the LOAD# decoding logic to support the “JUMP IF NOT CARRY” instruction. So returning to the logic of #LOAD3, we have:

      COUT    /C    D4   D6   D7    LOAD3
        0      1     X    1    1      0    -> Dst = PC
        X      X     1    1    1      0    -> Dst = PC

    Hence a jump will only happen (i.e. the PC get loaded) either if D4, D6, D7 are all 1 (unconditional) or if D4 =0, D6, D7 are 1 (conditional) if the CARRY flag is NOT set by the adder, resulting in /C = 1.

    Some of the ROM instructions require D0-D3 to be zero in which case the adder is effectively taking the input (A, B, IN, 0) and loading it into the destination register (A, B, OUT, PC).

    Notice that the adder does not use the carry in (CIN). This is tied to zero. Apparently this was left floating on an earlier revision of the board, which caused spurious results!

    Putting it all Together

    The complete truth table for the SEL, D4-7 and LOAD signals is as follows.

    SEL_BSEL_AD4D5D6D7LD0/ALD1/BLD2/OPLD3/PCADD A,i0000LL00000111MOV AB0001LH10000111IN A0010HL01000111MOV A,i0011HH11000111MOV BA0100LL00101011ADD B,i0101LH10101011IN B0110HL01101011MOV B,i0111HH111010111000LH00011101OUT B1001LH100111011010HH01011101OUT i1011HH110111011100LH0011111=C1101LH10111110JNC1110HH0111111=CJMP1111HH11111110

    Returning to our instruction table, we can see how the decoding of the D4-D7 lines leads to enacting the various commands. In particular, we can now expand the table to show how the SEL and LOAD logic results in selecting the source and destination registers as follows:

    D7-D4D3-D0INPUTOUTPUTADD A, data0000dataAAMOV A, B00010000BAIN A00100000INAMOV A, data0011data0AMOV B, A01000000ABADD B, data0101dataBBIN B01100000INBMOV B, data0111data0BOUT B *10000000BOUTOUT B10010000BOUTOUT data *1010data0OUTOUT data1011data0OUTJNC B *1100dataB/CPC/noneJMP B *1101dataBPCJNC1110data0/CPC/noneJMP1111data0PC

    As per the table, we can also now infer the missing, or duplicate, instructions (marked * above).

    In this table, the output will always be the addition of the INPUT and D3-D0, so everywhere 0 is specified for D3-D0 then in reality a value could be placed here instead. But then the instruction would take on a different meaning.

    For example, MOV A, B is really MOV A, B+data, which really only makes sense when data is set to 0 otherwise overflows are very likely to occur.

    It is also worth noting that SEL_A depends on either D4 or D7, and when SEL_A is set to 1 the input can only be either register B or zero. However, to output to OUT or PC, D7 has to be set. This means that instructions that act on OUT or PC can only take an input from register B or zero.

    The two JMP B instructions are going to be of limited use too. They are essentially JMP to B+data instructions. There are probably some creative uses of such instructions, but for simplicity, keeping to the “0” versions that just depend on the immediate data is probably best.

    Utility Blocks

    There is one section of the circuit that hasn’t been considered yet. There is a block that provides the clock and reset circuitry.

    The clock is based on a Schmidt trigger oscillator and can run on automatic or on manual trigger. There are two selectable speeds: 1Hz or 10Hz.

    Both the clock and reset signals feed into the four registers and the carry flip-flop.

    The remaining block is the power. It has a micro-USB socket and has to be powered from 5V directly either via the USB socket or directly into a 2-pin jumper header.

    Conclusion

    I have one on order. I’m looking forward to building it and giving it a go!

    I really like the LEDs on the deluxe version, but that is a bit too much for me just for some messing around, but I am wondering how difficult it would be to attempt my own version with a few extra LEDs.

    Assuming I manage to get one built and working, I’ll have a poke about at some signals and see what the art of the possible might be.

    Kevin

    #4bit #cpu #load0 #load3 #td4

    #cpu #td4 #load0 #load3 #4bit
  17. Kevin's Blog @[email protected] ·

    TD4 4-bit DIY CPU

    I was looking for DIY CPU projects, as I like kits that help me think at the lowest level of processing. It helps keep me grounded in how far technology has come over the years.

    Some of the options that I know about, that actually come as kits you can buy and are interesting for me for DIY computers are:

    But I wanted to go further down and actually find something that lets me build a simple CPU from gates. Here there are several options too:

    Whilst I’d love to build Ben Eater’s 8-bit CPU, the kit as provided is too much of an outlay for me. It is ~$300 – I mean, good for what you get and all the knowledge, but it is a solderless breadboard kit and that isn’t really what I’m after. The Gigatron is a distinct possibility that I’ll come back to at some point I think.

    NAND to Tetris is excellent, and I have their book, but it is all emulated or virtualised, which does allow for all the scaling required for an (arguably) actually useful device, but isn’t designed to be built in actual hardware.

    But the TD4 is really interesting. It is available as a PCB and components for approx £25 on Aliexpress and based on an open source design that shows the basic operation of a 4-bit CPU.

    The “deluxe” kit mentioned above is a lot more expensive ~£120 but has all signals broken out to LEDs which, whilst is an awful lot of soldering, does looks incredibly impressive! The MiniMax is an evolution of the TD4 and kits for that are around £120. In fact, searching on Tindie and Hackaday.io for “TD4” will surface a few other DIY projects and even kits to purchase.

    The TD4 does seem to fit the bill for me as an inexpensive kit to try. The downside is that documentation for it (in English) is pretty sparse.

    The TD4 project itself is by “wuxx” an embedded engineer from HangZhou and much of the documentation is in Chinese. It is based on a Japenese book by Kaoru Tonami called “how to build a CPU” which can be found for ~£50 online, but as I don’t know Japanese either is unlikely to help me very much.

    There are some sources of information that others have put together though, so I’m going to be using those as a starting point along with whatever I can figure out myself:

    This post is my own “thinking out loud” as I work through the various parts to see how they work.

    Basic Architecture

    This is a 4-bit computer, with a 4-bit data bus, 4-bit commands, and a 4-bit address bus.

    There is a block diagram on GitHub:

    The fundamental process is as follows. For each “tick” of the computer:

    • An OpCode is read from the ROM using the current 4-bit address (0 to 15) from the program counter.
    • Each ROM entry is an 8-bit word with 4-bits as a command and 4-bits as data for the command.
    • The data selector determines a 4-bit INPUT value. This can come from one of the two registers (A or B); or a set of four switches for the IN register; or be set to zero.
    • This goes to the adder which adds it with the immediate data from the ROM (which could of course be zero).
    • The OUTPUT of the adder can go to either of the two registers (A or B), an OUT register which is hooked up to four LEDS, or the program counter register to create a “jump”.

    I’ll pull apart the different parts of the CPU in the following sections.

    ROM Format

    Each 8-bit word in the 16-byte ROM has the following format:

    • 4 command bits
    • 4 immediate data bits

    Instruction Decoding

    The 4 command bits from each ROM instruction have to be turned into the various selection signals to activate different parts of the CPU.

    There is a table from GitHub again:

    The explanation in Japanese translates (apparently) to:

    “Explanation: The SEL_B and SEL_A signals select the ALU data source, while #LOAD0-#LOAD3 select the ALU data destination. More formally, they control the source and destination operands of instructions, respectively.”

    From this we can note the following:

    • There is no instruction for 1000,1010,1100 or 1101.
    • Instruction 1110 appears twice, and the selectors set are dependent on the state of the C (carry) flag.
    • Some instructions act on immediate data, others assume it will be 0.

    The LOAD# have the following meanings in the system:

    • LOAD#0 – Register A (A)
    • LOAD#1 – Register B (B)
    • LOAD#2 – OUTPUT (OUT)
    • LOAD#3 – Program counter (PC)

    The actual decoding happens in two parts: input selection; and output selection.

    Registers

    The system has four registers, each formed from a 74HC161 “presettable, synchronous, 4-bit binary counter”. There are two general purpose registers: A and B. There is one output register, whose contents drive the state of four LEDs. And there is a program counter. Here is the schematic for register A:

    P0-P3 come from the output of the adder directly. RST and CLK are hopefully self-explanatory. For the A and B registers, Q0-Q3 go into the INPUT selection section (see later). For the OUTPUT register, these go directly to LEDs. For the program counter, these go into the ROM address logic (again more on that later).

    The relevant operation of the 161 is described in the datasheet:

    “The outputs (Q0 to Q3) of the counters may be preset HIGH or LOW. A LOW at the parallel enable input (PE) disables the counting action and causes the data at the data inputs (D0 to D3) to be loaded into the counter on the positive-going edge of the clock… A LOW at the master reset input (MR) sets Q0 to Q3 LOW…”

    So on reset the outputs are all 0. When PE goes LOW, on the next clock pulse, the value on the inputs (P0-P3) is loaded into the counter and reflected on Q0-Q3. However, because CET and CEP are LOW the counter won’t actually count any further.

    The program counter is a bit special, in that it is actually allowed the count by having CET and CEP set HIGH. This allows it to step through the instructions on a clock pulse.

    In this case Q0-Q3 go off to the ROM address decoding, which I’ll come to in a moment.

    INPUT Selection

    There are two SELECT lines select the INPUT data as follows:

    SEL_BSEL_ASOURCE00Register A (A)01Register B (B)10INPUT (IN)11Zero value (0)

    Input selection is handled by two 74HC153 dual 4-input multiplexers. Two are required as there are four data lines to be switched, and they all have one of four options to switch between based on the SELECT lines above.

    Here is the relevant part of the schematic.

    On the left are the three sets of four data signals that come from the A, B and IN inputs. D0 from each of the inputs goes to U7/1Cn; D1 goes to U7/2Cn; D2 to U8/1Cn; and D3 to U8/2Cn. Notice that the fourth set of data signals (U7/1C3, 2C3 and U8 1C3, 2C3) are connected directly to GND for the “zero” INPUT state (SEL_A=1, SEL_B=1).

    On the right, the two pairs of outputs make up the four data lines to feed into the adder section.

    So where does the SEL_A and SEL_B signals come from? From the schematic, we can see:

    • SEL_A = D4 OR D7 (via U10B – one of the 74HC32 2-input OR gates)
    • SEL_B = D5

    We can start to explain why some of the instruction combinations don’t exist (or at least, aren’t distinct) as we can see that SEL_A depends on either D4 or D7.

    OUTPUT Selection

    The OUTPUT selection is a little more complicated. As previously mentioned, there are four destinations: the two registers, the OUTPUT register, and the program counter.

    Each register has a /PE (“parallel enable input”) signal which is active low. These are individually fed by the output of the LOAD# logic.

    The three signals at the bottom are D6, D7 and D4. The lone signal top left is the carry (/C) flag, and the four outputs top right are the four LOAD# signals which feed directly into the /PE pins of the four registers.

    So from this we deduce the following relationships:

    • Reg A LOAD0 HIGH = D6 OR D7 – so LOAD0 is only active (LOW) when both D6 and D7 are LOW.
    • Reg B LOAD1 HIGH = NOT D6 OR D7 – so LOAD1 is only active (LOW) when D6 is HIGH and D7 is LOW.
    • OUT LOAD2 LOW = NOT D6 AND D7 – so LOAD2 is only active (LOW) when D6 is LOW and D7 is HIGH.
    • PC LOAD3 LOW = D6 AND D7 AND (D4 OR /C) – so LOAD3 is only active (LOW) when both D6 and D7 are HIGH and either D4 is HIGH or the carry flag (C) is LOW.

    This effectively means that D6 is used to select between registers A and B when D7 is LOW; and between OUT and PC when D7 is HIGH (subject to either D4 or the CARRY too in the case of PC).

    Once again, we can see that there is some redundancy in the system for certain combinations of D4 to D7.

    ROM Address Decoding

    The 4-bit output from the program counter is effectively a 4-bit address bus. This gets turned into a set of selection signals to select which “byte” of the ROM should be active.

    This simply uses a 74HC154, 4 to 16 line decoder, meaning that a 4-bit number goes in and one of 16 corresponding outputs goes LOW whilst the rest remain HIGH. There is no memory address or matrix handling – there is literally one control line per “memory” location.

    The ROM itself is a set of 16 8-way DIP switches and diodes, so once its control signal is active (LOW) then those DIP switches become relevant on the data bus. Here is the last location and data bus logic. Note that all data signals are pulled HIGH by default, so will only be read as LOW if the DIP switch connects it to LOW via the diode, and that is only possible if that DIP block is selected from the 4 to 16 line decoder.

    The 74HC540 is an inverting line buffer, turning any active LOW DIP switch settings into HIGH signals on the command/data bus. Recall that D0-D3 represent immediate data and D4-D7 represent command logic.

    The Adder (ALU)

    The arithmetic logic unit (ALU) for this CPU is a simple adder. A 74HC283 is a 4-bit binary full adder. “full” in that it supports 4-bit add-with-carry functionality, although in this design, carry is only used on the output stage – it doesn’t form part of the input addition.

    A0-A3 comes from the INPUT selection circuitry, so can represent either register A or B, the state of the IN switches, or a fixed zero (0) value. B0-B3 comes directly from D0-D3 from the ROM contents as selected by the ROM addressing logic.

    The COUT (carry) flag goes into a flip-flop and the active LOW version of the output is used as the carry flag in the LOAD# decoding logic to support the “JUMP IF CARRY” and “JUMP IF NOT CARRY” instructions.

    Some of the ROM instructions require D0-D3 to be zero in which case the adder is effectively taking the input (A, B, IN, 0) and loading it into the destination register (A, B, OUT, PC).

    Notice that the adder does not use the carry in (CIN). This is tied to zero. Apparently this was left floating on an earlier revision of the board, which caused spurious results!

    Putting it all Together

    Returning to our instruction table, we can see how the decoding of the D4-D7 lines leads to enacting the various commands. In particular, we can now expand the table to show how the SEL and LOAD logic results in selecting he source and destination registers as follows:

    D7-D4D3-D0INPUTOUTPUTADD A, data0000dataAAMOV A, B00010000BAIN A00100000INAMOV A, data0011data0AMOV B, A01000000ABADD B, data0101dataBBIN B01100000INBMOV B, data0111data0BOUT B10000000BOUTOUT B10010000BOUTOUT data1010data0OUTOUT data1011data0OUTJMPC B1100dataB/CPC/noneJMP B1101dataBPCJMPC1110data0/CPC/noneJMP1111data0PC

    As per the table, we can also now infer the missing, or duplicate, instructions.

    In this table, the output will always be the addition of the INPUT and D3-D0, so everywhere 0 is specified for D3-D0 then in reality a value could be placed here instead. But then the instruction would take on a different meaning.

    For example, MOV A, B is really MOV A, B+data, which really only makes sense when data is set to 0 otherwise overflows are very likely to occur.

    It is also worth noting that SEL_A depends on either D4 or D7, and when SEL_A is set to 1 the input can only be either register B or zero. However, to output to OUT or PC, D7 has to be set. This means that instructions that act on OUT or PC can only take an input from register B or zero.

    The two JMP B instructions are going to be of limited use too. They are essentially JMP to B+data instructions. There are probably some creative uses of such instructions, but for simplicity, keeping to the “0” versions that just depend on the immediate data is probably best.

    Utility Blocks

    There is one section of the circuit that hasn’t been considered yet. There is a block that provides the clock and reset circuitry.

    The clock is based on a Schmidt trigger oscillator and can run on automatic or on manual trigger. There are two selectable speeds: 1Hz or 10Hz.

    Both the clock and reset signals feed into the four registers and the carry flip-flop.

    The remaining block is the power. It has a micro-USB socket and has to be powered from 5V directly either via the USB socket or directly into a 2-pin jumper header.

    Conclusion

    I have one on order. I’m looking forward to building it and giving it a go!

    I really like the LEDs on the deluxe version, but that is a bit too much for me just for some messing around, but I am wondering how difficult it would be to attempt my own version with a few extra LEDs.

    Assuming I manage to get one built and working, I’ll have a poke about at some signals and see what the art of the possible might be.

    Kevin

    #cpu #LOAD0 #TD4

    #td4 #load0 #cpu
  18. Kevin's Blog @[email protected] ·

    TD4 4-bit DIY CPU

    I was looking for DIY CPU projects, as I like kits that help me think at the lowest level of processing. It helps keep me grounded in how far technology has come over the years.

    • Part 1 – Introduction, Discussion and Analysis
    • Part 2 – Building and Hardware
    • Part 3 – Programming and Simple Programs
    • Part 4 – Some hardware enhancements
    • Part 5 – My own PCB version
    • Part 6 – Replacing the ROM with a microcontroller
    • Part 7 – Creating an Arduino “assembler” for the TD4

    Some of the options that I know about, that actually come as kits you can buy and are interesting for me for DIY computers are:

    But I wanted to go further down and actually find something that lets me build a simple CPU from gates. Here there are several options too:

    Whilst I’d love to build Ben Eater’s 8-bit CPU, the kit as provided is too much of an outlay for me. It is ~$300 – I mean, good for what you get and all the knowledge, but it is a solderless breadboard kit and that isn’t really what I’m after. The Gigatron is a distinct possibility that I’ll come back to at some point I think.

    NAND to Tetris is excellent, and I have their book, but it is all emulated or virtualised, which does allow for all the scaling required for an (arguably) actually useful device, but isn’t designed to be built in actual hardware.

    But the TD4 is really interesting. It is available as a PCB and components for approx £25 on Aliexpress and based on an open source design that shows the basic operation of a 4-bit CPU.

    The “deluxe” kit mentioned above is a lot more expensive ~£120 but has all signals broken out to LEDs which, whilst is an awful lot of soldering, does looks incredibly impressive! The MiniMax is an evolution of the TD4 and kits for that are around £120. In fact, searching on Tindie and Hackaday.io for “TD4” will surface a few other DIY projects and even kits to purchase.

    The TD4 does seem to fit the bill for me as an inexpensive kit to try. The downside is that documentation for it (in English) is pretty sparse.

    The TD4 project itself is by “wuxx” an embedded engineer from HangZhou and much of the documentation is in Chinese. It is based on a Japenese book by Kaoru Tonami called “how to build a CPU” which can be found for ~£50 online, but as I don’t know Japanese either is unlikely to help me very much.

    There are some sources of information that others have put together though, so I’m going to be using those as a starting point along with whatever I can figure out myself:

    This post is my own “thinking out loud” as I work through the various parts to see how they work.

    Basic Architecture

    This is a 4-bit computer, with a 4-bit data bus, 4-bit commands, and a 4-bit address bus.

    There is a block diagram on GitHub:

    The fundamental process is as follows. For each “tick” of the computer:

    • An OpCode is read from the ROM using the current 4-bit address (0 to 15) from the program counter.
    • Each ROM entry is an 8-bit word with 4-bits as a command and 4-bits as data for the command.
    • The data selector determines a 4-bit INPUT value. This can come from one of the two registers (A or B); or a set of four switches for the IN register; or be set to zero.
    • This goes to the adder which adds it with the immediate data from the ROM (which could of course be zero).
    • The OUTPUT of the adder can go to either of the two registers (A or B), an OUT register which is hooked up to four LEDS, or the program counter register to create a “jump”.

    I’ll pull apart the different parts of the CPU in the following sections.

    ROM Format

    Each 8-bit word in the 16-byte ROM has the following format:

    • 4 command bits
    • 4 immediate data bits

    Instruction Decoding

    The 4 command bits from each ROM instruction have to be turned into the various selection signals to activate different parts of the CPU.

    There is a table from GitHub again:

    The explanation in Japanese translates (apparently) to:

    “Explanation: The SEL_B and SEL_A signals select the ALU data source, while #LOAD0-#LOAD3 select the ALU data destination. More formally, they control the source and destination operands of instructions, respectively.”

    From this we can note the following:

    • There is no instruction for 1000,1010,1100 or 1101.
    • Instruction 1110 appears twice, and the selectors set are dependent on the state of the C (carry) flag.
    • Some instructions act on immediate data, others assume it will be 0.

    The LOAD# have the following meanings in the system:

    • LOAD#0 – Register A (A)
    • LOAD#1 – Register B (B)
    • LOAD#2 – OUTPUT (OUT)
    • LOAD#3 – Program counter (PC)

    The actual decoding happens in two parts: input selection; and output selection.

    Registers

    The system has four registers, each formed from a 74HC161 “presettable, synchronous, 4-bit binary counter”. There are two general purpose registers: A and B. There is one output register, whose contents drive the state of four LEDs. And there is a program counter. Here is the schematic for register A:

    P0-P3 come from the output of the adder directly. RST and CLK are hopefully self-explanatory. For the A and B registers, Q0-Q3 go into the INPUT selection section (see later). For the OUTPUT register, these go directly to LEDs. For the program counter, these go into the ROM address logic (again more on that later).

    The relevant operation of the 161 is described in the datasheet:

    “The outputs (Q0 to Q3) of the counters may be preset HIGH or LOW. A LOW at the parallel enable input (PE) disables the counting action and causes the data at the data inputs (D0 to D3) to be loaded into the counter on the positive-going edge of the clock… A LOW at the master reset input (MR) sets Q0 to Q3 LOW…”

    So on reset the outputs are all 0. When PE goes LOW, on the next clock pulse, the value on the inputs (P0-P3) is loaded into the counter and reflected on Q0-Q3. However, because CET and CEP are LOW the counter won’t actually count any further.

    The program counter is a bit special, in that it is actually allowed the count by having CET and CEP set HIGH. This allows it to step through the instructions on a clock pulse.

    In this case Q0-Q3 go off to the ROM address decoding, which I’ll come to in a moment.

    INPUT Selection

    There are two SELECT lines select the INPUT data as follows:

    SEL_BSEL_ASOURCE00Register A (A)01Register B (B)10INPUT (IN)11Zero value (0)

    Input selection is handled by two 74HC153 dual 4-input multiplexers. Two are required as there are four data lines to be switched, and they all have one of four options to switch between based on the SELECT lines above.

    Here is the relevant part of the schematic.

    On the left are the three sets of four data signals that come from the A, B and IN inputs. D0 from each of the inputs goes to U7/1Cn; D1 goes to U7/2Cn; D2 to U8/1Cn; and D3 to U8/2Cn. Notice that the fourth set of data signals (U7/1C3, 2C3 and U8 1C3, 2C3) are connected directly to GND for the “zero” INPUT state (SEL_A=1, SEL_B=1).

    On the right, the two pairs of outputs make up the four data lines to feed into the adder section.

    So where does the SEL_A and SEL_B signals come from? From the schematic, we can see:

    • SEL_A = D4 OR D7 (via U10B – one of the 74HC32 2-input OR gates)
    • SEL_B = D5

    We can start to explain why some of the instruction combinations don’t exist (or at least, aren’t distinct) as we can see that SEL_A depends on either D4 or D7.

    OUTPUT Selection

    The OUTPUT selection is a little more complicated. As previously mentioned, there are four destinations: the two registers, the OUTPUT register, and the program counter.

    Each register has a /PE (“parallel enable input”) signal which is active low. These are individually fed by the output of the LOAD# logic.

    The three signals at the bottom are D6, D7 and D4. The lone signal top left is the carry (/C) flag, and the four outputs top right are the four LOAD# signals which feed directly into the /PE pins of the four registers.

    So from this we deduce the following relationships:

    • Reg A LOAD0 HIGH = D6 OR D7 – so LOAD0 is only active (LOW) when both D6 and D7 are LOW.
    • Reg B LOAD1 HIGH = NOT D6 OR D7 – so LOAD1 is only active (LOW) when D6 is HIGH and D7 is LOW.
    • OUT LOAD2 LOW = NOT D6 AND D7 – so LOAD2 is only active (LOW) when D6 is LOW and D7 is HIGH.
    • PC LOAD3 LOW = D6 AND D7 AND (D4 OR /C) – so LOAD3 is only active (LOW) when both D6 and D7 are HIGH and either D4 is HIGH or the carry signal (/C) is LOW.

    This effectively means that D6 is used to select between registers A and B when D7 is LOW; and between OUT and PC when D7 is HIGH (subject to either D4 or the /C signal too in the case of PC).

    Once again, we can see that there is some redundancy in the system for certain combinations of D4 to D7.

    ROM Address Decoding

    The 4-bit output from the program counter is effectively a 4-bit address bus. This gets turned into a set of selection signals to select which “byte” of the ROM should be active.

    This simply uses a 74HC154, 4 to 16 line decoder, meaning that a 4-bit number goes in and one of 16 corresponding outputs goes LOW whilst the rest remain HIGH. There is no memory address or matrix handling – there is literally one control line per “memory” location.

    The ROM itself is a set of 16 8-way DIP switches and diodes, so once its control signal is active (LOW) then those DIP switches become relevant on the data bus. Here is the last location and data bus logic. Note that all data signals are pulled HIGH by default, so will only be read as LOW if the DIP switch connects it to LOW via the diode, and that is only possible if that DIP block is selected from the 4 to 16 line decoder.

    The 74HC540 is an inverting line buffer, turning any active LOW DIP switch settings into HIGH signals on the command/data bus. Recall that D0-D3 represent immediate data and D4-D7 represent command logic.

    The Adder (ALU)

    The arithmetic logic unit (ALU) for this CPU is a simple adder. A 74HC283 is a 4-bit binary full adder. “full” in that it supports 4-bit add-with-carry functionality, although in this design, carry is only used on the output stage – it doesn’t form part of the input addition.

    A0-A3 comes from the INPUT selection circuitry, so can represent either register A or B, the state of the IN switches, or a fixed zero (0) value. B0-B3 comes directly from D0-D3 from the ROM contents as selected by the ROM addressing logic.

    The COUT (carry) flag goes into a flip-flop and the active LOW version of the output is used as the carry flag in the LOAD# decoding logic to support the “JUMP IF NOT CARRY” instruction. So returning to the logic of #LOAD3, we have:

      COUT    /C    D4   D6   D7    LOAD3
        0      1     X    1    1      0    -> Dst = PC
        X      X     1    1    1      0    -> Dst = PC

    Hence a jump will only happen (i.e. the PC get loaded) either if D4, D6, D7 are all 1 (unconditional) or if D4 =0, D6, D7 are 1 (conditional) if the CARRY flag is NOT set by the adder, resulting in /C = 1.

    Some of the ROM instructions require D0-D3 to be zero in which case the adder is effectively taking the input (A, B, IN, 0) and loading it into the destination register (A, B, OUT, PC).

    Notice that the adder does not use the carry in (CIN). This is tied to zero. Apparently this was left floating on an earlier revision of the board, which caused spurious results!

    Putting it all Together

    The complete truth table for the SEL, D4-7 and LOAD signals is as follows.

    SEL_BSEL_AD4D5D6D7LD0/ALD1/BLD2/OPLD3/PCADD A,i0000LL00000111MOV AB0001LH10000111IN A0010HL01000111MOV A,i0011HH11000111MOV BA0100LL00101011ADD B,i0101LH10101011IN B0110HL01101011MOV B,i0111HH111010111000LH00011101OUT B1001LH100111011010HH01011101OUT i1011HH110111011100LH0011111=C1101LH10111110JNC1110HH0111111=CJMP1111HH11111110

    Returning to our instruction table, we can see how the decoding of the D4-D7 lines leads to enacting the various commands. In particular, we can now expand the table to show how the SEL and LOAD logic results in selecting the source and destination registers as follows:

    D7-D4D3-D0INPUTOUTPUTADD A, data0000dataAAMOV A, B00010000BAIN A00100000INAMOV A, data0011data0AMOV B, A01000000ABADD B, data0101dataBBIN B01100000INBMOV B, data0111data0BOUT B *10000000BOUTOUT B10010000BOUTOUT data *1010data0OUTOUT data1011data0OUTJNC B *1100dataB/CPC/noneJMP B *1101dataBPCJNC1110data0/CPC/noneJMP1111data0PC

    As per the table, we can also now infer the missing, or duplicate, instructions (marked * above).

    In this table, the output will always be the addition of the INPUT and D3-D0, so everywhere 0 is specified for D3-D0 then in reality a value could be placed here instead. But then the instruction would take on a different meaning.

    For example, MOV A, B is really MOV A, B+data, which really only makes sense when data is set to 0 otherwise overflows are very likely to occur.

    It is also worth noting that SEL_A depends on either D4 or D7, and when SEL_A is set to 1 the input can only be either register B or zero. However, to output to OUT or PC, D7 has to be set. This means that instructions that act on OUT or PC can only take an input from register B or zero.

    The two JMP B instructions are going to be of limited use too. They are essentially JMP to B+data instructions. There are probably some creative uses of such instructions, but for simplicity, keeping to the “0” versions that just depend on the immediate data is probably best.

    Utility Blocks

    There is one section of the circuit that hasn’t been considered yet. There is a block that provides the clock and reset circuitry.

    The clock is based on a Schmidt trigger oscillator and can run on automatic or on manual trigger. There are two selectable speeds: 1Hz or 10Hz.

    Both the clock and reset signals feed into the four registers and the carry flip-flop.

    The remaining block is the power. It has a micro-USB socket and has to be powered from 5V directly either via the USB socket or directly into a 2-pin jumper header.

    Conclusion

    I have one on order. I’m looking forward to building it and giving it a go!

    I really like the LEDs on the deluxe version, but that is a bit too much for me just for some messing around, but I am wondering how difficult it would be to attempt my own version with a few extra LEDs.

    Assuming I manage to get one built and working, I’ll have a poke about at some signals and see what the art of the possible might be.

    Kevin

    #4bit #cpu #load0 #load3 #td4

    #cpu #td4 #load0 #load3 #4bit
  19. Habr @[email protected] ·

    [Перевод] Macroni: рецепт поступательного улучшения языка программирования

    Хотя, Clang и используется в качестве инструмента для рефакторинга и статического анализа, у него есть серьёзный недостаток: в абстрактном синтаксическом дереве не предоставляется информации о происхождении конкретных расширений-макросов на CPP , за счёт которых может надстраиваться конкретный узел AST. Кроме того, Clang не понижает расширения-макросы на уровень LLVM, то есть, до кода в формате промежуточного представления (IR). Из-за этого оказывается запредельно сложно конструировать такие схемы статического анализа, при которых учитывались бы макросы. Сейчас эта тема активно исследуется. Но ситуация налаживается, поскольку прошлым летом был создан инструмент Macroni , упрощающий статический анализ именно такого рода. В Macroni разработчики могут определять синтаксис новых языковых конструкций на C с применением макросов, а также предоставлять семантику для этих конструкций при помощи MLIR (многоуровневого промежуточного представления). В Macroni используется инструмент VAST , понижающий код C до MLIR. В свою очередь, инструмент PASTA позволяет выяснить, откуда те или иные макросы попали в AST, и на основании этой информации макросы также удаётся понизить до MLIR. После этого разработчики могут определять с обственные MLIR-конвертеры для преобразования вывода Macroni в предметно-ориентированные диалекты MLIR, чтобы анализировать предмет с учётом многочисленных нюансов. В этой статье будет на нескольких примерах показано, как Macroni позволяет дополнять C более безопасными языковыми конструкциями и организовать анализ безопасности C.

    habr.com/ru/companies/timeweb/

    #timeweb_статьи_перевод #Macroni #программирование #c #c++ #LLVM #AST #Clang #MLIR #ABI #API #Линус_Торвальдс #Sparse #Objective_C

    #objective_c #sparse #линус_торвальдс #api #abi #mlir
  20. Ruth Salter @[email protected] ·

    A few months ago someone on Wikipedia suggested merging the (very sparse) Sandy Bell's page with Hamish Henderson's - which I thought was a terrible idea since Henderson was neither A Pub or The Revival.

    Onyway, I finally got round to adding a few edits to expand the Bell's page but it's still in need of much overhaul if anybody's a Bells enthusiast.

    en.wikipedia.org/wiki/Sandy_Be

    #FolkMusic #ScottishMusic #TradMusic #ScottishFolk #ScottishTrad #ScottishFolkRevival #FolkRevival #Edinburgh #Wikipedia

    #wikipedia #edinburgh #folkrevival #scottishfolkrevival #scottishtrad #scottishfolk
  21. In the Dark @[email protected] ·

    Weekly Update from the Open Journal of Astrophysics – 25/04/2026

    So here we are again, on a Saturday morning, with another update of activity at the Open Journal of Astrophysics. Since the last update we have published a further five papers, bringing the number in Volume 9 (2026) to 87 and the total so far published by OJAp up to 535.

    I will continue to include the posts made on our Mastodon account (on Fediscience) to encourage you to visit it. Mastodon is a really excellent service, and a more than adequate replacement for X/Twitter (which nobody should be using); these announcements also show the DOI for each paper.

    The first paper to report this week is “Bayesian Cosmic Void Finding with Graph Flows” by Leander Thiele (U. Tokyo, Japan). This was published on Monday 20th April in the folder Cosmology and Nongalactic Astrophysics. The paper presents a method using a deep graph neural network to identify cosmic voids in sparse galaxy surveys, improving upon traditional deterministic algorithms by considering the problem’s probabilistic nature. The overlay is here:

    You can find the officially accepted version on arXiv here and the announcement on Fediverse here:

    https://fediscience.org/@OJ_Astro/116435864086025246

    The second paper for this week, published on Wednesday 22nd April in the folder Astrophysics of Galaxies, is “Sifting for a Stream: The Morphology of the 300S Stellar Stream” by Benjamin Cohen (U. Chicago, USA) and 20 others distributed around the world. This study analyzes the morphology of the $300S$ stellar stream, revealing three density peaks, a possible gap, and a kink, suggesting significant influence from the Large Magellanic Cloud on its structure.

    The overlay for this one is here:

    The official version of the paper can be found on arXiv here and the Fediverse announcement here:

    https://fediscience.org/@OJ_Astro/116447005556180402

    Next one up, the third paper of the week, is “IRMaGiC: Extending Luminous Red Galaxy Selection into the Infrared with Joint Rubin Observatory’s Large Survey of Space Time and Roman’s High Latitude Imaging Survey” by Zhiyuan Guo & Chris. W. Walter (Duke U., USA) and Eli S. Rykoff (Stanford U., USA) on behalf of the LSST Dark Energy Science Collaboration. This was published on Wednesday April 22nd in the folder Cosmology and Nongalactic Astrophysics. The paper introduces IRMaGiC, an algorithm that improves the selection and redshift estimation of Luminous Red Galaxies (LRGs) by incorporating infrared data, enhancing future cosmological surveys.

    The overlay for this one is here:

    The final, accepted version can be found on arXiv here and the Mastodon announcement is here:

    https://fediscience.org/@OJ_Astro/116447067337351283

    The fourth paper this week, published on Thursday April 23rd, is “The Diagnostic Temperature Discrepancy as Evidence for Non-Maxwellian Coronal Electrons” by Victor Edmonds (Final Stop Consulting, USA). This paper, in the folder Solar and Stellar Astrophysics, presents two methods of measuring electron temperature in the quiet solar corona yielding different results, suggesting non-Maxwellian electron velocity distributions may be responsible for the discrepancy.

    The overlay is here:

    The finally accepted version of this paper can be found here and the Mastodon announcement follows:

    https://fediscience.org/@OJ_Astro/116452775389963618

    The fifth and final paper for this week was published on Friday 24th April in the folder Astrophysics of Galaxies. The title is “Galaxy evolution in the post-merger regime. IV – The long-term effect of mergers on galactic stellar mass growth and distribution” by Sara L. Ellison (U. Victoria, Canada) and Leonardo Ferreira (Universidade Federal do Rio Grande, Brazil). This study uses a large sample of post-merger galaxies to demonstrate that galaxy mergers trigger significant and extended stellar mass growth in their central regions, independent of stellar population modelling.

    The overlay is here:

    You can find the authorized version of this paper on arXiv here and the Fediverse announcement is here:

    https://fediscience.org/@OJ_Astro/116458316824739014

    The overlay for this one is here:

    You can find the officially-accepted version on arXiv here and the Mastodon announcement here:

    https://fediscience.org/@OJ_Astro/116458316824739014

    And that concludes this week’s update. I’ll do another one at the end of next week.

    P.S. Thanks to the efforts of a member of our Editorial Board, the Open Journal of Astrophysics now has a Wikipedia page.

    #300SStellarStream #arXiv250621410v2 #arXiv251121512v2 #arXiv260114554v2 #arXiv260214630v2 #arXiv260310040v3 #AstrophysicsOfGalaxies #BayesianMethods #CosmicVoids #CosmologyAndNonGalacticAstrophysics #DiamondOpenAccess #DiamondOpenAccessPublishing #EarthAndPlanetaryAstrophysics #GAIA #galaxyEvolution #galaxyFormation #galaxyMergers #InstrumentationAndMethodsForAstrophysics #IntergalacticMedium #IRMaGiC #LargeMagellanicCloud #LSST #LSSTDarkEnergyScienceCollaboration #MilkyWay #OpenAccess #OpenAccessPublishing #SolarAndStellarAstrophysics #SolarCorona #VeraCRubinObservatory #wikipedia
    #300sstellarstream #arxiv250621410v2 #arxiv251121512v2 #arxiv260114554v2 #arxiv260214630v2 #arxiv260310040v3
  22. In the Dark @[email protected] ·

    Weekly Update from the Open Journal of Astrophysics – 25/04/2026

    So here we are again, on a Saturday morning, with another update of activity at the Open Journal of Astrophysics. Since the last update we have published a further five papers, bringing the number in Volume 9 (2026) to 87 and the total so far published by OJAp up to 535.

    I will continue to include the posts made on our Mastodon account (on Fediscience) to encourage you to visit it. Mastodon is a really excellent service, and a more than adequate replacement for X/Twitter (which nobody should be using); these announcements also show the DOI for each paper.

    The first paper to report this week is “Bayesian Cosmic Void Finding with Graph Flows” by Leander Thiele (U. Tokyo, Japan). This was published on Monday 20th April in the folder Cosmology and Nongalactic Astrophysics. The paper presents a method using a deep graph neural network to identify cosmic voids in sparse galaxy surveys, improving upon traditional deterministic algorithms by considering the problem’s probabilistic nature. The overlay is here:

    You can find the officially accepted version on arXiv here and the announcement on Fediverse here:

    https://fediscience.org/@OJ_Astro/116435864086025246

    The second paper for this week, published on Wednesday 22nd April in the folder Astrophysics of Galaxies, is “Sifting for a Stream: The Morphology of the 300S Stellar Stream” by Benjamin Cohen (U. Chicago, USA) and 20 others distributed around the world. This study analyzes the morphology of the $300S$ stellar stream, revealing three density peaks, a possible gap, and a kink, suggesting significant influence from the Large Magellanic Cloud on its structure.

    The overlay for this one is here:

    The official version of the paper can be found on arXiv here and the Fediverse announcement here:

    https://fediscience.org/@OJ_Astro/116447005556180402

    Next one up, the third paper of the week, is “IRMaGiC: Extending Luminous Red Galaxy Selection into the Infrared with Joint Rubin Observatory’s Large Survey of Space Time and Roman’s High Latitude Imaging Survey” by Zhiyuan Guo & Chris. W. Walter (Duke U., USA) and Eli S. Rykoff (Stanford U., USA) on behalf of the LSST Dark Energy Science Collaboration. This was published on Wednesday April 22nd in the folder Cosmology and Nongalactic Astrophysics. The paper introduces IRMaGiC, an algorithm that improves the selection and redshift estimation of Luminous Red Galaxies (LRGs) by incorporating infrared data, enhancing future cosmological surveys.

    The overlay for this one is here:

    The final, accepted version can be found on arXiv here and the Mastodon announcement is here:

    https://fediscience.org/@OJ_Astro/116447067337351283

    The fourth paper this week, published on Thursday April 23rd, is “The Diagnostic Temperature Discrepancy as Evidence for Non-Maxwellian Coronal Electrons” by Victor Edmonds (Final Stop Consulting, USA). This paper, in the folder Solar and Stellar Astrophysics, presents two methods of measuring electron temperature in the quiet solar corona yielding different results, suggesting non-Maxwellian electron velocity distributions may be responsible for the discrepancy.

    The overlay is here:

    The finally accepted version of this paper can be found here and the Mastodon announcement follows:

    https://fediscience.org/@OJ_Astro/116452775389963618

    The fifth and final paper for this week was published on Friday 24th April in the folder Astrophysics of Galaxies. The title is “Galaxy evolution in the post-merger regime. IV – The long-term effect of mergers on galactic stellar mass growth and distribution” by Sara L. Ellison (U. Victoria, Canada) and Leonardo Ferreira (Universidade Federal do Rio Grande, Brazil). This study uses a large sample of post-merger galaxies to demonstrate that galaxy mergers trigger significant and extended stellar mass growth in their central regions, independent of stellar population modelling.

    The overlay is here:

    You can find the authorized version of this paper on arXiv here and the Fediverse announcement is here:

    https://fediscience.org/@OJ_Astro/116458316824739014

    The overlay for this one is here:

    You can find the officially-accepted version on arXiv here and the Mastodon announcement here:

    https://fediscience.org/@OJ_Astro/116458316824739014

    And that concludes this week’s update. I’ll do another one at the end of next week.

    P.S. Thanks to the efforts of a member of our Editorial Board, the Open Journal of Astrophysics now has a Wikipedia page.

    #300SStellarStream #arXiv250621410v2 #arXiv251121512v2 #arXiv260114554v2 #arXiv260214630v2 #arXiv260310040v3 #AstrophysicsOfGalaxies #BayesianMethods #CosmicVoids #CosmologyAndNonGalacticAstrophysics #DiamondOpenAccess #DiamondOpenAccessPublishing #EarthAndPlanetaryAstrophysics #GAIA #galaxyEvolution #galaxyFormation #galaxyMergers #InstrumentationAndMethodsForAstrophysics #IntergalacticMedium #IRMaGiC #LargeMagellanicCloud #LSST #LSSTDarkEnergyScienceCollaboration #MilkyWay #OpenAccess #OpenAccessPublishing #SolarAndStellarAstrophysics #SolarCorona #VeraCRubinObservatory #wikipedia
    #wikipedia #veracrubinobservatory #solarcorona #solarandstellarastrophysics #openaccesspublishing #openaccess
  23. 잘생긴 남자 @[email protected] ·

    Update on my #os (tentatively codenamed #tyros) that I'm building in my spare time.

    My first task is booting, and it's really made me appreciate how terrible everyone says the PC (x86) architecture is. I'd done a bit of 386 assembly before, so I knew it was a little goofy, but I was unprepared for the horrors of the actual architecture.

    I actually got my first kernel booting after just a few hours. But, it was 16-bit real mode and relied on BIOS, so that was obviously a dead duck.

    I got my second kernel booting after another couple days, which was transitioned (manually) into 32-bit protected mode. But the documentation for "long" mode (64-bit) was more sparse and more daunting, so I looked for another approach....

    #os #tyros
  24. 잘생긴 남자 @[email protected] ·

    Update on my #os (tentatively codenamed #tyros) that I'm building in my spare time.

    My first task is booting, and it's really made me appreciate how terrible everyone says the PC (x86) architecture is. I'd done a bit of 386 assembly before, so I knew it was a little goofy, but I was unprepared for the horrors of the actual architecture.

    I actually got my first kernel booting after just a few hours. But, it was 16-bit real mode and relied on BIOS, so that was obviously a dead duck.

    I got my second kernel booting after another couple days, which was transitioned (manually) into 32-bit protected mode. But the documentation for "long" mode (64-bit) was more sparse and more daunting, so I looked for another approach....

    #os #tyros
  25. Spencer Callaghan @[email protected] ·

    I feel like the only community I’m really missing on #mastodon is sports.

    #tech and #cdnpoli seem pretty well covered here but the #sens #redblacks #patriots and #hotspur communities feel pretty sparse.

    #hotspur #mastodon #tech #cdnpoli #sens #redblacks
  26. 50+ Music @[email protected] ·

    "Try to Remember" is a song about nostalgia from the #musicalComedy play #TheFantasticks (1960). It is the first song performed in the show, encouraging the audience to imagine what the sparse set suggests. The words were written by the American lyricist #TomJones while #HarveySchmidt composed the music.
    youtube.com/watch?v=chXuhNeBhjM

    #musicalcomedy #thefantasticks #tomjones #harveyschmidt
  27. slowforward @[email protected] ·

    bongiani art museum: “universi possibili / carte, documenti e pagine sparse” @ archivio di stato di salerno

    cliccare per ingrandire

    Dopo la mostra “Carte, cartapecore, scartoffie e pinzillacchere” del 2017 presentata all’Archivio di Stato di Salerno con l’esposizione di antiche pergamene, scritture e documenti  originali in un insolito viaggio dentro il passato e il ventre dell’Archivio, a distanza di 7 anni viene presentato nel Salone dell’Archivio di Stato di Salerno un secondo evento dal titolo: “UNIVERSI POSSIBILI, carte, documenti e pagine sparse” a  cura di Sandro Bongiani che comprende l’utilizzo di undici documenti già presentati nella precedente mostra per essere ora utilizzati come base di lavoro da 43 importanti artisti  italiani e stranieri, diversi per età e linguaggio espressivo, invitati a intervenire, ognuno con il proprio vissuto e visione poetica a realizzare l’opera “unica” per questo evento collettivo a Salerno.

    Gli artisti invitati:  Alessandra Angelini I Francesco Aprile I Antonio Baglivo I John M. Bennett I Raffaele Boemio I Andrea Bonanno I Sandro Bongiani I Anna Boschi I Ryosuke Cohen I Carmela Corsitto I Rosa Cuccurullo I Nicolò D’Alessandro I Marcello Diotallevi I Pablo  Echaurren I Cinzia Farina I Luc Fierens I Giovanni Fontana I Marco Giovenale I Coco Gordon I Paolo Gubinelli I Carlo Iacomucci I Ugo la Pietra I Giovanni Leto I Pietro Lista I Oronzo Liuzzi I Maya Lopez I Serse Luigetti  I  Ruggero Maggi I Mauro Magni I Elena Marini I Gabi Minedi I Giorgio Moio  I Mauro Molinari I Franco Panella I Filippo Panseca I Enzo Patti I Lamberto Pignotti I RCBz  I  Gian Paolo Roffi I Paolo Scirpa I Ernesto Terlizzi I Reid Wood I Rolando Zucchini

    #AlessandraAngelini #AndreaBonanno #AnnaBoschi #antichePergamene #AntonioBaglivo #ArchivioDiStatoDiSalerno #art #arte #BongianiArtMuseum #CappellaDiSanLudovico #CarloIacomucci #CarmelaCorsitto #carte #CinziaFarina #CocoGordon #CollezioneBongianiArtMuseum #documenti #ElenaMarini #EnzoPatti #ErnestoTerlizzi #FilippoPanseca #FrancescoAprile #FrancoPanella #GabiMinedi #GianPaoloRoffi #GiorgioMoio #GiovanniFontana #GiovanniLeto #JohnMBennett #LambertoPignotti #LucFierens #MarcelloDiotallevi #MarcoGiovenale #materialiVerbovisivi #MauroMagni #MauroMolinari #MayaLopez #NicolòDAlessandro #OronzoLiuzzi #PabloEchaurren #pagineSparse #PaoloGubinelli #PaoloScirpa #PietroLista #RaffaeleBoemio #RCBz #ReidWood #RolandoZucchini #RosaCuccurullo #RuggeroMaggi #RyosukeCohen #SandroBongiani #SandroBongianiArteContemporanea #scritture #SerseLuigetti #UgoLaPietra #UniversiPossibili

    #alessandraangelini #andreabonanno #annaboschi #antichepergamene #antoniobaglivo #archiviodistatodisalerno
  28. slowforward @[email protected] ·

    bongiani art museum: “universi possibili / carte, documenti e pagine sparse” @ archivio di stato di salerno

    cliccare per ingrandire

    Dopo la mostra “Carte, cartapecore, scartoffie e pinzillacchere” del 2017 presentata all’Archivio di Stato di Salerno con l’esposizione di antiche pergamene, scritture e documenti  originali in un insolito viaggio dentro il passato e il ventre dell’Archivio, a distanza di 7 anni viene presentato nel Salone dell’Archivio di Stato di Salerno un secondo evento dal titolo: “UNIVERSI POSSIBILI, carte, documenti e pagine sparse” a  cura di Sandro Bongiani che comprende l’utilizzo di undici documenti già presentati nella precedente mostra per essere ora utilizzati come base di lavoro da 43 importanti artisti  italiani e stranieri, diversi per età e linguaggio espressivo, invitati a intervenire, ognuno con il proprio vissuto e visione poetica a realizzare l’opera “unica” per questo evento collettivo a Salerno.

    Gli artisti invitati:  Alessandra Angelini I Francesco Aprile I Antonio Baglivo I John M. Bennett I Raffaele Boemio I Andrea Bonanno I Sandro Bongiani I Anna Boschi I Ryosuke Cohen I Carmela Corsitto I Rosa Cuccurullo I Nicolò D’Alessandro I Marcello Diotallevi I Pablo  Echaurren I Cinzia Farina I Luc Fierens I Giovanni Fontana I Marco Giovenale I Coco Gordon I Paolo Gubinelli I Carlo Iacomucci I Ugo la Pietra I Giovanni Leto I Pietro Lista I Oronzo Liuzzi I Maya Lopez I Serse Luigetti  I  Ruggero Maggi I Mauro Magni I Elena Marini I Gabi Minedi I Giorgio Moio  I Mauro Molinari I Franco Panella I Filippo Panseca I Enzo Patti I Lamberto Pignotti I RCBz  I  Gian Paolo Roffi I Paolo Scirpa I Ernesto Terlizzi I Reid Wood I Rolando Zucchini

    #AlessandraAngelini #AndreaBonanno #AnnaBoschi #antichePergamene #AntonioBaglivo #ArchivioDiStatoDiSalerno #art #arte #BongianiArtMuseum #CappellaDiSanLudovico #CarloIacomucci #CarmelaCorsitto #carte #CinziaFarina #CocoGordon #CollezioneBongianiArtMuseum #documenti #ElenaMarini #EnzoPatti #ErnestoTerlizzi #FilippoPanseca #FrancescoAprile #FrancoPanella #GabiMinedi #GianPaoloRoffi #GiorgioMoio #GiovanniFontana #GiovanniLeto #JohnMBennett #LambertoPignotti #LucFierens #MarcelloDiotallevi #MarcoGiovenale #materialiVerbovisivi #MauroMagni #MauroMolinari #MayaLopez #NicolòDAlessandro #OronzoLiuzzi #PabloEchaurren #pagineSparse #PaoloGubinelli #PaoloScirpa #PietroLista #RaffaeleBoemio #RCBz #ReidWood #RolandoZucchini #RosaCuccurullo #RuggeroMaggi #RyosukeCohen #SandroBongiani #SandroBongianiArteContemporanea #scritture #SerseLuigetti #UgoLaPietra #UniversiPossibili

    #alessandraangelini #andreabonanno #annaboschi #antichepergamene #antoniobaglivo #archiviodistatodisalerno
  29. slowforward @[email protected] ·

    bongiani art museum: “universi possibili / carte, documenti e pagine sparse” @ archivio di stato di salerno

    cliccare per ingrandire

    Dopo la mostra “Carte, cartapecore, scartoffie e pinzillacchere” del 2017 presentata all’Archivio di Stato di Salerno con l’esposizione di antiche pergamene, scritture e documenti  originali in un insolito viaggio dentro il passato e il ventre dell’Archivio, a distanza di 7 anni viene presentato nel Salone dell’Archivio di Stato di Salerno un secondo evento dal titolo: “UNIVERSI POSSIBILI, carte, documenti e pagine sparse” a  cura di Sandro Bongiani che comprende l’utilizzo di undici documenti già presentati nella precedente mostra per essere ora utilizzati come base di lavoro da 43 importanti artisti  italiani e stranieri, diversi per età e linguaggio espressivo, invitati a intervenire, ognuno con il proprio vissuto e visione poetica a realizzare l’opera “unica” per questo evento collettivo a Salerno.

    Gli artisti invitati:  Alessandra Angelini I Francesco Aprile I Antonio Baglivo I John M. Bennett I Raffaele Boemio I Andrea Bonanno I Sandro Bongiani I Anna Boschi I Ryosuke Cohen I Carmela Corsitto I Rosa Cuccurullo I Nicolò D’Alessandro I Marcello Diotallevi I Pablo  Echaurren I Cinzia Farina I Luc Fierens I Giovanni Fontana I Marco Giovenale I Coco Gordon I Paolo Gubinelli I Carlo Iacomucci I Ugo la Pietra I Giovanni Leto I Pietro Lista I Oronzo Liuzzi I Maya Lopez I Serse Luigetti  I  Ruggero Maggi I Mauro Magni I Elena Marini I Gabi Minedi I Giorgio Moio  I Mauro Molinari I Franco Panella I Filippo Panseca I Enzo Patti I Lamberto Pignotti I RCBz  I  Gian Paolo Roffi I Paolo Scirpa I Ernesto Terlizzi I Reid Wood I Rolando Zucchini

    #AlessandraAngelini #AndreaBonanno #AnnaBoschi #antichePergamene #AntonioBaglivo #ArchivioDiStatoDiSalerno #art #arte #BongianiArtMuseum #CappellaDiSanLudovico #CarloIacomucci #CarmelaCorsitto #carte #CinziaFarina #CocoGordon #CollezioneBongianiArtMuseum #documenti #ElenaMarini #EnzoPatti #ErnestoTerlizzi #FilippoPanseca #FrancescoAprile #FrancoPanella #GabiMinedi #GianPaoloRoffi #GiorgioMoio #GiovanniFontana #GiovanniLeto #JohnMBennett #LambertoPignotti #LucFierens #MarcelloDiotallevi #MarcoGiovenale #materialiVerbovisivi #MauroMagni #MauroMolinari #MayaLopez #NicolòDAlessandro #OronzoLiuzzi #PabloEchaurren #pagineSparse #PaoloGubinelli #PaoloScirpa #PietroLista #RaffaeleBoemio #RCBz #ReidWood #RolandoZucchini #RosaCuccurullo #RuggeroMaggi #RyosukeCohen #SandroBongiani #SandroBongianiArteContemporanea #scritture #SerseLuigetti #UgoLaPietra #UniversiPossibili

    #alessandraangelini #andreabonanno #annaboschi #antichepergamene #antoniobaglivo #archiviodistatodisalerno
  30. slowforward @[email protected] ·

    dal 13 dicembre, a salerno: “universi possibili. carte, documenti e pagine sparse”, mostra collettiva a cura di sandro bongiani

    Universi Possibili, carte, documenti e pagine sparse

    L’Archivio di Stato di Salerno ha il piacere di presentare, venerdì 13 dicembre 2024 alle ore 19:00, la mostra collettiva dal titolo “Universi Possibili, carte, documenti e pagine sparse”, a cura di Sandro Bongiani. La mostra è organizzata dalla Collezione Bongiani Art Museum di Salerno.

    Archivio di Stato di Salerno – Ministero della cultura
    Piazza Abate Conforti,7 84121 Salerno (SA)

    “UNIVERSI POSSIBILI, carte, documenti e pagine sparse” Progetto collettivo “add to & Return”, un viaggio a ritroso nel passato per poi connettersi con il presente. Una contaminazione totale di diversi modi espressivi in cui la condivisione diventa presupposto essenziale di sedimentazione, stratificazione e dialogo tra momenti diversi divenuti opera contemporanea.

    La mostra è costituita dalle opere di 43 artisti italiani e stranieri appositamente invitati a questo importante evento collettivo.

    Gli artisti invitati: Alessandra Angelini I Francesco Aprile I Antonio Baglivo I John M. Bennett I Raffaele Boemio I Andrea Bonanno I Sandro Bongiani I Anna Boschi I Ryosuke Cohen I Carmela Corsitto I Rosa Cuccurullo I Nicolò D’Alessandro I Marcello Diotallevi I Pablo Echaurren I Cinzia Farina I Luc Fierens I Giovanni Fontana I Marco Giovenale I Coco Gordon I Paolo Gubinelli I Carlo Iacomucci I Ugo La Pietra I Giovanni Leto I Pietro Lista I Oronzo Liuzzi I Maya Lopez I Serse Luigetti I Ruggero Maggi I Mauro Magni I Elena Marini I Gabi Minedi I Giorgio Moio I Mauro Molinari I Franco Panella I Filippo Panseca I Enzo Patti I Lamberto Pignotti I RCBz I Gian Paolo Roffi I Paolo Scirpa I Ernesto Terlizzi I Reid Wood I Rolando Zucchini.

    Dopo la mostra “Carte, cartapecore, scartoffie e pinzillacchere” del 2017 presentata all’Archivio di Stato di Salerno con l’esposizione di antiche pergamene, scritture e documenti originali in un insolito viaggio dentro il passato e il ventre dell’Archivio, a distanza di 7 anni viene presentato nel Salone dell’Archivio di Stato di Salerno un secondo evento dal titolo: “UNIVERSI POSSIBILI, carte, documenti e pagine sparse” a cura di Sandro Bongiani che comprende l’utilizzo di undici documenti già presentati nella precedente mostra per essere ora utilizzati come base di lavoro da 43 importanti artisti italiani e stranieri, diversi per età e linguaggio espressivo, invitati a intervenire, ognuno con il proprio vissuto e visione poetica a realizzare l’opera “unica” per questo evento collettivo a Salerno.

    “Universi possibili” è una mostra collettiva pensata espressamente per l’Archivio di Salerno, vuole ribadire prima di tutto il valore primario del documento storico cartaceo come “materiale essenziale da costruzione” dell’opera nella sua qualità storica e espressiva. Il progetto è stato pensato espressamente come una sorta viaggio a ritroso nel passato, per poi connettersi anche con il presente, integrandosi e vivendo in un corpo e una voce unica. Quello che ne viene fuori dalle opere presentate è la sorprendente capacità degli artisti contemporanei a relazionarsi e dialogare con il passato in un procedere assorto e struggente aggiungendo alla storia il presente e prospettando attraverso la visione un unicum collettivo di “nuovi mondi possibili” di rappresentazione poetica.

    *

    In contemporanea al progetto “Universi possibili” presente nel Salone dell’Archivio di Stato sono visibili nella cappella di San Ludovico adiacente all’Archivio, anche le opere dell’artista Fluxus americana Coco Gordon, con una quindicina di libri tagliati, una serie di opere in metallo in forma di libri-prigione di Giovanni Bonanno creati espressamente per lo spazio della Cappella e le pagine sparse dell’artista Franco Panella a cercare in qualche modo un connubio con il luogo e soprattutto con la memoria di questo importante spazio storico che Umberto Eco definiva come “deposito della memoria” e della vita degli uomini.

    Si ringrazia l’Archivio Storico di Salerno e la Collezione Bongiani Art Museum di Salerno per la collaborazione alla realizzazione di questo importante evento.

    Archivio di Stato di Salerno – Ministero della cultura
    Presentazione dell’evento con Salvatore Amato, Gabriella Taddeo e Sandro Bongiani
    Evento / Salone Archivio di Stato di Salerno:
    “UNIVERSI POSSIBILI / Carte, documenti e pagine sparse”
    Progetto Internazionale con 43 artisti invitati
    Salone dell’Archivio di Stato di Salerno dal 13 dicembre 2024 al 12 gennaio 2025 Vernissage venerdì 13 dicembre 2024 ore 19.00 Piazza Abate Conforti, 7 – 84121 Salerno (SA) Email: [email protected] Tel: (+39) 089 22 50 44 – Fax: (+39) 089 22 66 41
    Evento / Cappella di San Ludovico:
    “UNIVERSI POSSIBILI / Carte, libri d’artista e pagine sparse” Opere di Coco Gordon, Giovanni Bonanno e Franco Panella Cappella di San Ludovico di Salerno dal 13 dicembre 2024 al 12 gennaio 2025 Piazza Abate Conforti, 7 84121 Salerno (SA Email: [email protected] Tel: (+39) 089 22 50 44 – Fax: (+39) 089 22 66 41
    Vernissage della mostra 13 dicembre 2024 ore 19.00 – 22.00
    Orari: lunedì e venerdì 8.00 – 13.30;
    martedì – mercoledì – giovedì: 8.00 – 17.00

    Evento in collaborazione con l’Archivio di Stato di Salerno e la Collezione Bongiani Art Museum.

    #AlessandraAngelini #AndreaBonanno #AnnaBoschi #AntonioBaglivo #ArchivioDiStatoDiSalerno #art #arte #artisti #asemic #BongianiArtMuseum #CarloIacomucci #CarmelaCorsitto #carte #CinziaFarina #CocoGordon #CollezioneBongianiArtMuseum #documenti #ElenaMarini #EnzoPatti #ErnestoTerlizzi #FilippoPanseca #FrancescoAprile #FrancoPanella #GabiMinedi #GabriellaTaddeo #GianPaoloRoffi #GiorgioMoio #GiovanniBonanno #GiovanniFontana #GiovanniLeto #glitch #glitchasemic #JohnMBennett #LambertoPignotti #LucFierens #MarcelloDiotallevi #MarcoGiovenale #MauroMagni #MauroMolinari #MayaLopez #MinisteroDellaCultura #NicolòDAlessandro #OronzoLiuzzi #PabloEchaurren #pagineSparse #PaoloGubinelli #PaoloScirpa #PietroLista #RaffaeleBoemio #RCBz #ReidWood #RolandoZucchini #RosaCuccurullo #RuggeroMaggi #RyosukeCohen #SalvatoreAmato #SandroBongiani #SerseLuigetti #UgoLaPietra #UniversiPossibili #vispo

    #alessandraangelini #andreabonanno #annaboschi #antoniobaglivo #archiviodistatodisalerno #art
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