#riscv64 — Public Fediverse posts
Live and recent posts from across the Fediverse tagged #riscv64, aggregated by home.social.
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It took a long time, but our #riscv64 builder managed to finish building the community packages. At the worst, it had a backlog of more than 800 packages, but it managed to churn along the last couple of weeks.
We had it running on a HiFive P550 for a while. Even though it had faster cores, we had to move it back to the MilkV Pionieer.
We're trying some other riscv64 systems as well, to see if they serve as better builders.
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It took a long time, but our #riscv64 builder managed to finish building the community packages. At the worst, it had a backlog of more than 800 packages, but it managed to churn along the last couple of weeks.
We had it running on a HiFive P550 for a while. Even though it had faster cores, we had to move it back to the MilkV Pionieer.
We're trying some other riscv64 systems as well, to see if they serve as better builders.
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I'm missing EC_fml13v01_20241227_v1.0.17.bin for the #deepcomputing #deepcomputingRiscVMainboard #riscv64
The original links is now 404 (meh, not nice) and I cannot find thie file on github anywhere.
Also filed as https://github.com/DC-DeepComputing/Framework/issues/51
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I'm missing EC_fml13v01_20241227_v1.0.17.bin for the #deepcomputing #deepcomputingRiscVMainboard #riscv64
The original links is now 404 (meh, not nice) and I cannot find thie file on github anywhere.
Also filed as https://github.com/DC-DeepComputing/Framework/issues/51
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This took me quite a bit of time, but I managed to boot postmarketOS on a currently unsupported devboard (commonly available for €25-30 where I live).
Little bit proud, but it's not a proper port yet, I ripped the kernel and other parts of the pre-init bootchain (fip.bin, u-boot, ...) from a pre-made Debian image for that device. I have a (mostly working) APKBUILD for that device's userland though. :)
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This took me quite a bit of time, but I managed to boot postmarketOS on a currently unsupported devboard (commonly available for €25-30 where I live).
Little bit proud, but it's not a proper port yet, I ripped the kernel and other parts of the pre-init bootchain (fip.bin, u-boot, ...) from a pre-made Debian image for that device. I have a (mostly working) APKBUILD for that device's userland though. :)
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The irony: the entire RISC-V base ISA (RV64GC) is beautifully RISC: simple opcodes, fixed 32-bit instructions (+ compressed), load/store architecture, no flags, no implicit state. Then RVV comes along and throws all those principles out the window: global implicit state, microcode-like behavior, variable semantics of the same instruction.
Because vsetvli changes the semantics of all subsequent V-instructions based on the current VLEN configuration. For a JIT compiler in an Emulator and for an Emulator in general, this means having to continuously track the vtype state and react to any changes, a fundamental contradiction to the principle of statically analyzable instructions. It feels like the RISC-V Foundation sacrificed the simplicity and elegance of the RISC principle to create a powerful but extremely complex "super-SIMD" that is difficult to efficiently map in a JIT. A more traditional SIMD extension with fixed vector widths and clearly defined instruction semantics would have been much more JIT-friendly. The upcoming P extension does go in that direction, but it is primarily targeted at embedded and low-power applications rather than high-performance computing.
#riscv #riscv64 #emulation #pasriscv #object_pascal #delphi #free_pascal
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The irony: the entire RISC-V base ISA (RV64GC) is beautifully RISC: simple opcodes, fixed 32-bit instructions (+ compressed), load/store architecture, no flags, no implicit state. Then RVV comes along and throws all those principles out the window: global implicit state, microcode-like behavior, variable semantics of the same instruction.
Because vsetvli changes the semantics of all subsequent V-instructions based on the current VLEN configuration. For a JIT compiler in an Emulator and for an Emulator in general, this means having to continuously track the vtype state and react to any changes, a fundamental contradiction to the principle of statically analyzable instructions. It feels like the RISC-V Foundation sacrificed the simplicity and elegance of the RISC principle to create a powerful but extremely complex "super-SIMD" that is difficult to efficiently map in a JIT. A more traditional SIMD extension with fixed vector widths and clearly defined instruction semantics would have been much more JIT-friendly. The upcoming P extension does go in that direction, but it is primarily targeted at embedded and low-power applications rather than high-performance computing.
#riscv #riscv64 #emulation #pasriscv #object_pascal #delphi #free_pascal
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It's 2026 now and time for an updated blog post for cross-compiling Chromium for RISC-V from scratch.
This blog post is much more simple compared with my previous blog post, because many RISC-V patches have been merged into Chromium mainline.
https://www.kxxt.dev/blog/cross-compile-chromium-for-riscv-2026/
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It's 2026 now and time for an updated blog post for cross-compiling Chromium for RISC-V from scratch.
This blog post is much more simple compared with my previous blog post, because many RISC-V patches have been merged into Chromium mainline.
https://www.kxxt.dev/blog/cross-compile-chromium-for-riscv-2026/
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I have that page about Arm cpu cores and their features.
RISC-V cpus has insane amount of extensions. I wonder when someone will make similar page about their details.
https://gpages.juszkiewicz.com.pl/arm-socs-table/arm-cpu-cores.html
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I have that page about Arm cpu cores and their features.
RISC-V cpus has insane amount of extensions. I wonder when someone will make similar page about their details.
https://gpages.juszkiewicz.com.pl/arm-socs-table/arm-cpu-cores.html
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« Milk-V Titan : Powered by a 2 GHz UR-DP1000 octa-core RISC-V CPU, the Titan mini-ITX motherboard supports up to 64GB DIMM memory and M.2 NVMe storage (PCIe Gen4 x4), and features a PCIe Gen4 x16 slot for a graphics card or other expansion, Gigabit Ethernet, four USB 3.0 ports, a BMC, and more. »
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« Milk-V Titan : Powered by a 2 GHz UR-DP1000 octa-core RISC-V CPU, the Titan mini-ITX motherboard supports up to 64GB DIMM memory and M.2 NVMe storage (PCIe Gen4 x4), and features a PCIe Gen4 x16 slot for a graphics card or other expansion, Gigabit Ethernet, four USB 3.0 ports, a BMC, and more. »
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PasRISCV now has its own local CLI debugger alongside the GDB remote server. It supports breakpoints, single-stepping, register & memory inspection, and allows simultaneous local CLI and remote GDB sessions. A public debugger API enables future graphical debugger frontends.
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PasRISCV now has its own local CLI debugger alongside the GDB remote server. It supports breakpoints, single-stepping, register & memory inspection, and allows simultaneous local CLI and remote GDB sessions. A public debugger API enables future graphical debugger frontends.
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Something is coming...
Yes, it's 4 AM right now. I've been doing this since around 1 AM.
Trust me, once it gets good, I'll properly reveal it.
It does have something to do with the #RISCV hardware I ordered recently.
I'll get somewhere with this, I promise, alright?
It may take longer than the hardware arrival, but I'll get there in the end.
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Something is coming...
Yes, it's 4 AM right now. I've been doing this since around 1 AM.
Trust me, once it gets good, I'll properly reveal it.
It does have something to do with the #RISCV hardware I ordered recently.
I'll get somewhere with this, I promise, alright?
It may take longer than the hardware arrival, but I'll get there in the end.
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#Debian13.0 Ready To Introduce Formal #RISCV Support But Still Bound By Slow Hardware
#Debian's RISC-V ambitions date back a decade when thfirst #RISCV64 port was started for Debian and then after all the work over the years, Debian 13.0 in August will finally debut it as an official architecture. #RV64GC is the current target for Debian RISC-V and using UEFI-based booting as the default. Over seventeen thousand source Debian packages are building for RISC-V with Trixie.
https://www.phoronix.com/news/Debian-13-RISC-V-Ready -
#Debian13.0 Ready To Introduce Formal #RISCV Support But Still Bound By Slow Hardware
#Debian's RISC-V ambitions date back a decade when thfirst #RISCV64 port was started for Debian and then after all the work over the years, Debian 13.0 in August will finally debut it as an official architecture. #RV64GC is the current target for Debian RISC-V and using UEFI-based booting as the default. Over seventeen thousand source Debian packages are building for RISC-V with Trixie.
https://www.phoronix.com/news/Debian-13-RISC-V-Ready -
The #OpenPrinting #CUPS #Snap is now available for #RISCV in the Snap Store!
To build it it just needed to add #riscv64 as supported architecture in the snapcraft.yaml file.
I has taken 2:30 hours (!) to build on my #DeepComputing / #Framework RISC-V board, and the build servers of the Snap Store need the same time to build it.
Thanks to Heinrich Schuchardt (xypron), RISC-V expert at #Canonical, for providing me a kernel which does bridge networking.
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The #OpenPrinting #CUPS #Snap is now available for #RISCV in the Snap Store!
To build it it just needed to add #riscv64 as supported architecture in the snapcraft.yaml file.
I has taken 2:30 hours (!) to build on my #DeepComputing / #Framework RISC-V board, and the build servers of the Snap Store need the same time to build it.
Thanks to Heinrich Schuchardt (xypron), RISC-V expert at #Canonical, for providing me a kernel which does bridge networking.
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Trying to install some python on my RiscV Ubuntu box and I keep running into different low level dependencies as there are no pre-compiled wheel packages.
If I had
1. FTTP
2. A spare Star Five boardI would volunteer some build resource.
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Trying to install some python on my RiscV Ubuntu box and I keep running into different low level dependencies as there are no pre-compiled wheel packages.
If I had
1. FTTP
2. A spare Star Five boardI would volunteer some build resource.
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I really need to setup a crossbuild environment for #pkgsrc ...
Building rust which is a dependency for ansible on the #VisionFive2 is now in its third day of building and I'd like it to be done by Friday ^^'
#riscv #riscv64 #NetBSD #SBC #OpenSource #opensourcehardware #build -
I really need to setup a crossbuild environment for #pkgsrc ...
Building rust which is a dependency for ansible on the #VisionFive2 is now in its third day of building and I'd like it to be done by Friday ^^'
#riscv #riscv64 #NetBSD #SBC #OpenSource #opensourcehardware #build -
Evidence that the wifi dongle is actually working ^^
#NetBSD #pkgsrc #OpenSource #opensourcehardware #SBC #singleboardcomputer #riscv #riscvsbc #riscv64 -
As much as I love source based package management like #pkgsrc on @netbsd ... this has been running for 10 hours and all I want is my weechat instance xD
Yeah the VisionFive 2 isn't exactly fast ^^'
Also USB works with the latest current image for riscv 💪🏻
#netbsd #bsd #OpenSource #opensourcehardware #riscv #riscvsbc #riscv64 -
As much as I love source based package management like #pkgsrc on @netbsd ... this has been running for 10 hours and all I want is my weechat instance xD
Yeah the VisionFive 2 isn't exactly fast ^^'
Also USB works with the latest current image for riscv 💪🏻
#netbsd #bsd #OpenSource #opensourcehardware #riscv #riscvsbc #riscv64 -
I sort of accept that EFI forces a RISC-V 64 bit bootloader to adhere to Windows binary formats, somewhat less why does it need to show that it's not compatible with DOS, but I'm dumbfounded by the fact that I can see int 21h being called in the preamble...
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I sort of accept that EFI forces a RISC-V 64 bit bootloader to adhere to Windows binary formats, somewhat less why does it need to show that it's not compatible with DOS, but I'm dumbfounded by the fact that I can see int 21h being called in the preamble...
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So since the irradium #Crux #Linux derivate on my #VisionFive2 was broken (didn't boot anymore without any errors, just froze) and I never liked this distro anyway I was looking for alternatives... and for some reason the @netbsd generic "qemu" image... just booted and installed out of the box xD
#RISCV #StarFive #riscv64 #SBC #opensource #netbsd #bsd #freedom -
Just booted Parch Linux on #RiscV64 Qemu
unfortunately i don`t have a bare metal hardware to test the image on it so i do the development inside of the Qemu.
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Just booted Parch Linux on #RiscV64 Qemu
unfortunately i don`t have a bare metal hardware to test the image on it so i do the development inside of the Qemu.
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I was able to boot Alpine on hifive permier p550
alpine:~# uname -a
Linux alpine 6.6.67-0-eswin #1-Alpine SMP PREEMPT_DYNAMIC Thu, 26 Dec 2024 14:02:15 +0000 riscv64 LinuxBut I'm not sure if linux-eswin is a good name for the kernel package.
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I was able to boot Alpine on hifive permier p550
alpine:~# uname -a
Linux alpine 6.6.67-0-eswin #1-Alpine SMP PREEMPT_DYNAMIC Thu, 26 Dec 2024 14:02:15 +0000 riscv64 LinuxBut I'm not sure if linux-eswin is a good name for the kernel package.
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The #AlpineLinux linux-lts kernel finally has #riscv64 enabled https://git.alpinelinux.org/aports/commit/?id=d106e5949469
It might work on VisionFive v2, but I have no idea if it actually does.
