#microarchitecture — Public Fediverse posts
Live and recent posts from across the Fediverse tagged #microarchitecture, aggregated by home.social.
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The consumer GPU market isn't in crisis; it's in an undeclared "End of Life" phase. NVIDIA is deliberately starving the AIB supply chain (partners like MSI and Asus) to divert all of TSMC's silicon to AI chips for data centers, where margins are obscene.
MSI just declared 2026 will be a supply nightmare and is cutting production. They're closing the ecosystem. PC gaming and independent builders have become a nuisance for Jensen Huang's balance sheets.
I'm compiling logs and market data for a complete autopsy of this commercial architecture. I'll post the full video on my channel. The era of x86 and affordable consumer hardware is coming to an end under the blows of the CUDA monopoly.
https://www.youtube.com/@Rational-Tech-VeLL
#Hardware #NVIDIA #PCBuild #SysAdmin #TechNews #OpenSource #Microarchitecture #GPU #RationalTech
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Fun issue: a performance regression between two Rust versions, only on dual socket Zen4c, and does not happen on dual socket Zen4, nor single socket socket Zen4c. https://github.com/rust-lang/rust/issues/154516
#RustLang #Bergamo #Genoa #Zen4 #AMD #NUMA #MicroArchitecture
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We're so excited to announce that Dries Vanspauwen, @lesly & Jo Van Bulck received the uASC best paper award for the paper "WeMu: Effective and Scalable Emulation of Microarchitectural Weird Machines"! Congratulations! 🎉
Check it out here: https://uasc.cc/proceedings26/uasc26-vanspauwen.pdf
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"AMD publishes first Zen 6 document detailing ground-up redesign on 2nm process node — brand-new 8-wide CPU core with strong vector capabilities"
Sounds like they're leaning heavily into 'datacenter' with this one.
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Also TIL that CPUs have special hint instructions (called PAUSE on x86) to make spin loops more efficient, which tell the CPU to let other hyperthreads progress instead, and again also improves CPU cache behavior.
Details on PAUSE: https://www.felixcloutier.com/x86/pause
Example from Go runtime: https://go.dev/src/runtime/asm_amd64.s#L803-809 -
The #microarchitecture of #Intel, #AMD, and #VIA #CPU’s - An optimization guide for #assembly #programmers and compiler makers by Agner Fog
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Only one month left to submit your paper for the first submission cycle at uASC 2026!
📅 Submission Deadline: July 15, 2025
👉 https://uasc.cc/ -
📈 Ah, the old "Calculate Throughput with LLVM's Scheduling Model" routine—because nothing screams weekend fun like diving into compiler internals and #microarchitecture performance analysis! 🤓 Just remember, when life gives you throughput, measure it in #IPC and don't forget to bring your inverse throughput for extra giggles. 😂
https://myhsu.xyz/llvm-sched-interval-throughput/ #CalculateThroughput #LLVM #SchedulingModel #CompilerInternals #PerformanceAnalysis #HackerNews #ngated -
Flow Computing aims to boost CPUs with ‘parallel processing units’
https://spectrum.ieee.org/parallel-processing-unit
#ycombinator #computer_architecture #cpu #microarchitecture #parallel_processing -
One #Prime Day this is probably a good time for me #SRE #DevOps #Reliability #Microarchitecture top tip:
Avoid powers of ten: use prime numbers as your magic constants.
All the beginners use powers of ten: “we can accept 10 connections!” “I have a 10 second timeout!” “Limit to 100 seconds of CPU!”
Congrats you read the Baby Tutorial.
Ready to grow up? Analyse the data then pick the nearest prime:
11 connections
19 second timeout
97 seconds of CPUIt makes it way easier to diagnose issues.
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Turns out @cheese is a real 3D person!
Here he sits down with Mike Clark, chief architect of Zen, to talk about AMDs latest microarchitecture, #zen5
#HPC #x86 #microarchitecture #avx512
From: @chipsandcheese
https://techhub.social/@chipsandcheese/112790635587132915 -
AMD Zen 5 Execution Engine Leaked, Features True 512-bit FPU
Giving "Zen 5" a 512-bit FPU meant that AMD also had to scale up the ancillaries [..]. The L1 Data cache has been doubled in bandwidth, and increased in size by 50%. The L1D is now 48 KB in size [..]. FPU MADD latency has been reduced by 1 cycle. Besides the FPU, AMD also increased the number of Integer execution pipes to 10, from 8 on "Zen 4."
https://www.techpowerup.com/321201/amd-zen-5-execution-engine-leaked-features-true-512-bit-fpu
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The Complete #History of the Home Microprocessor:
https://www.youtube.com/watch?v=EJh4BIujpHA
#Tech #CPU #Microarchitecture #x86 #Processor #ARM #PowerPC #68k
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#Zen4c: #AMD’s Response to #Hyperscale ARM & Intel Atom
#Bergamo, AMD’s upcoming 128-core server part sets new heights in #x86 #CPU performance. At the heart of Bergamo is #Zen 4c, a brand-new CPU core variant of their successful #5nm #Zen4 #microarchitecture that enables the push toward more cores per socket. Zen 4c enables Bergamo to fit 1.33x the number of cores in the same #SP5 socket and 360W TDP, with identical L1 and 1MB L2 private caches to Zen 4.
https://www.semianalysis.com/p/zen-4c-amds-response-to-hyperscale -
CW: research review
G. Hu and R. Lee, "Protecting Cache States Against Both Speculative Execution Attacks and Side-channel Attacks"¹
Cache side-channel attacks and speculative execution attacks that leak information through cache states are stealthy and dangerous attacks on hardware that must be mitigated. Unfortunately, defenses proposed for cache side-channel attacks do not mitigate all cache-based speculative execution attacks and vice versa. Since both classes of attacks must be addressed, we propose comprehensive cache architectures to do this.
We show a framework to analyze the security of a secure cache. We identify same-domain speculative execution attacks, and show they evade cache side-channel defenses. We present new hardware security mechanisms that address target attacks and reduce performance overhead. We design two Speculative and Timing Attack Resilient (STAR) caches that defeat both cache side-channel attacks and cache-based speculative execution attacks. These comprehensive defenses have low performance overhead of 6.6% and 8.8%.#arXiv #ResearchPapers #SideChannelAttacks #Microarchitecture #SpeculativeExecution
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¹ https://arxiv.org/abs/2302.00732 -
Really interesting article series on the details of #AMD's #Zen 4 #microarchitecture
AMD’s Zen 4 Part 1: Frontend and Execution Engine
https://chipsandcheese.com/2022/11/05/amds-zen-4-part-1-frontend-and-execution-engine/
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In which we are again in awe of the M1's gigantic ROB in upending throughput expectations in multiplying 64-bit numbers:
https://lemire.me/blog/2021/03/17/apples-m1-processor-and-the-full-128-bit-integer-product/
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Our #hackerspace @chaospott is planning a series of #CTF challenges based on #FreeBSD VMs with custom prepared images to teach about #vulnerabilities and #mitigations in the 64-bit #x86 #microarchitecture, what an #OS has to take care of, and so on. Quite exciting! ✨👩🏻💻✨
