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#microarchitecture — Public Fediverse posts

Live and recent posts from across the Fediverse tagged #microarchitecture, aggregated by home.social.

  1. The consumer GPU market isn't in crisis; it's in an undeclared "End of Life" phase. NVIDIA is deliberately starving the AIB supply chain (partners like MSI and Asus) to divert all of TSMC's silicon to AI chips for data centers, where margins are obscene.

    MSI just declared 2026 will be a supply nightmare and is cutting production. They're closing the ecosystem. PC gaming and independent builders have become a nuisance for Jensen Huang's balance sheets.

    I'm compiling logs and market data for a complete autopsy of this commercial architecture. I'll post the full video on my channel. The era of x86 and affordable consumer hardware is coming to an end under the blows of the CUDA monopoly.

    youtube.com/@Rational-Tech-VeLL

    #Hardware #NVIDIA #PCBuild #SysAdmin #TechNews #OpenSource #Microarchitecture #GPU #RationalTech

  2. The consumer GPU market isn't in crisis; it's in an undeclared "End of Life" phase. NVIDIA is deliberately starving the AIB supply chain (partners like MSI and Asus) to divert all of TSMC's silicon to AI chips for data centers, where margins are obscene.

    MSI just declared 2026 will be a supply nightmare and is cutting production. They're closing the ecosystem. PC gaming and independent builders have become a nuisance for Jensen Huang's balance sheets.

    I'm compiling logs and market data for a complete autopsy of this commercial architecture. I'll post the full video on my channel. The era of x86 and affordable consumer hardware is coming to an end under the blows of the CUDA monopoly.

    youtube.com/@Rational-Tech-VeLL

    #Hardware #NVIDIA #PCBuild #SysAdmin #TechNews #OpenSource #Microarchitecture #GPU #RationalTech

  3. The consumer GPU market isn't in crisis; it's in an undeclared "End of Life" phase. NVIDIA is deliberately starving the AIB supply chain (partners like MSI and Asus) to divert all of TSMC's silicon to AI chips for data centers, where margins are obscene.

    MSI just declared 2026 will be a supply nightmare and is cutting production. They're closing the ecosystem. PC gaming and independent builders have become a nuisance for Jensen Huang's balance sheets.

    I'm compiling logs and market data for a complete autopsy of this commercial architecture. I'll post the full video on my channel. The era of x86 and affordable consumer hardware is coming to an end under the blows of the CUDA monopoly.

    youtube.com/@Rational-Tech-VeLL

    #Hardware #NVIDIA #PCBuild #SysAdmin #TechNews #OpenSource #Microarchitecture #GPU #RationalTech

  4. The consumer GPU market isn't in crisis; it's in an undeclared "End of Life" phase. NVIDIA is deliberately starving the AIB supply chain (partners like MSI and Asus) to divert all of TSMC's silicon to AI chips for data centers, where margins are obscene.

    MSI just declared 2026 will be a supply nightmare and is cutting production. They're closing the ecosystem. PC gaming and independent builders have become a nuisance for Jensen Huang's balance sheets.

    I'm compiling logs and market data for a complete autopsy of this commercial architecture. I'll post the full video on my channel. The era of x86 and affordable consumer hardware is coming to an end under the blows of the CUDA monopoly.

    youtube.com/@Rational-Tech-VeLL

    #Hardware #NVIDIA #PCBuild #SysAdmin #TechNews #OpenSource #Microarchitecture #GPU #RationalTech

  5. The consumer GPU market isn't in crisis; it's in an undeclared "End of Life" phase. NVIDIA is deliberately starving the AIB supply chain (partners like MSI and Asus) to divert all of TSMC's silicon to AI chips for data centers, where margins are obscene.

    MSI just declared 2026 will be a supply nightmare and is cutting production. They're closing the ecosystem. PC gaming and independent builders have become a nuisance for Jensen Huang's balance sheets.

    I'm compiling logs and market data for a complete autopsy of this commercial architecture. I'll post the full video on my channel. The era of x86 and affordable consumer hardware is coming to an end under the blows of the CUDA monopoly.

    youtube.com/@Rational-Tech-VeLL

  6. Fun issue: a performance regression between two Rust versions, only on dual socket Zen4c, and does not happen on dual socket Zen4, nor single socket socket Zen4c. github.com/rust-lang/rust/issu

    #RustLang #Bergamo #Genoa #Zen4 #AMD #NUMA #MicroArchitecture

  7. Fun issue: a performance regression between two Rust versions, only on dual socket Zen4c, and does not happen on dual socket Zen4, nor single socket socket Zen4c. github.com/rust-lang/rust/issu

    #RustLang #Bergamo #Genoa #Zen4 #AMD #NUMA #MicroArchitecture

  8. Fun issue: a performance regression between two Rust versions, only on dual socket Zen4c, and does not happen on dual socket Zen4, nor single socket socket Zen4c. github.com/rust-lang/rust/issu

    #RustLang #Bergamo #Genoa #Zen4 #AMD #NUMA #MicroArchitecture

  9. Fun issue: a performance regression between two Rust versions, only on dual socket Zen4c, and does not happen on dual socket Zen4, nor single socket socket Zen4c. github.com/rust-lang/rust/issu

    #RustLang #Bergamo #Genoa #Zen4 #AMD #NUMA #MicroArchitecture

  10. Fun issue: a performance regression between two Rust versions, only on dual socket Zen4c, and does not happen on dual socket Zen4, nor single socket socket Zen4c. github.com/rust-lang/rust/issu

    #RustLang #Bergamo #Genoa #Zen4 #AMD #NUMA #MicroArchitecture

  11. We're so excited to announce that Dries Vanspauwen, @lesly & Jo Van Bulck received the uASC best paper award for the paper "WeMu: Effective and Scalable Emulation of Microarchitectural Weird Machines"! Congratulations! 🎉

    Check it out here: uasc.cc/proceedings26/uasc26-v

    #uasc26 #microarchitecture #security #conference

  12. We're so excited to announce that Dries Vanspauwen, @lesly & Jo Van Bulck received the uASC best paper award for the paper "WeMu: Effective and Scalable Emulation of Microarchitectural Weird Machines"! Congratulations! 🎉

    Check it out here: uasc.cc/proceedings26/uasc26-v

    #uasc26 #microarchitecture #security #conference

  13. We're so excited to announce that Dries Vanspauwen, @lesly & Jo Van Bulck received the uASC best paper award for the paper "WeMu: Effective and Scalable Emulation of Microarchitectural Weird Machines"! Congratulations! 🎉

    Check it out here: uasc.cc/proceedings26/uasc26-v

    #uasc26 #microarchitecture #security #conference

  14. We're so excited to announce that Dries Vanspauwen, @lesly & Jo Van Bulck received the uASC best paper award for the paper "WeMu: Effective and Scalable Emulation of Microarchitectural Weird Machines"! Congratulations! 🎉

    Check it out here: uasc.cc/proceedings26/uasc26-v

    #uasc26 #microarchitecture #security #conference

  15. We're so excited to announce that Dries Vanspauwen, @lesly & Jo Van Bulck received the uASC best paper award for the paper "WeMu: Effective and Scalable Emulation of Microarchitectural Weird Machines"! Congratulations! 🎉

    Check it out here: uasc.cc/proceedings26/uasc26-v

    #uasc26 #microarchitecture #security #conference

  16. "AMD publishes first Zen 6 document detailing ground-up redesign on 2nm process node — brand-new 8-wide CPU core with strong vector capabilities"

    Sounds like they're leaning heavily into 'datacenter' with this one.

    #AMD #Zen6 #Microarchitecture #CPU

    tomshardware.com/pc-components

  17. "AMD publishes first Zen 6 document detailing ground-up redesign on 2nm process node — brand-new 8-wide CPU core with strong vector capabilities"

    Sounds like they're leaning heavily into 'datacenter' with this one.

    #AMD #Zen6 #Microarchitecture #CPU

    tomshardware.com/pc-components

  18. Also TIL that CPUs have special hint instructions (called PAUSE on x86) to make spin loops more efficient, which tell the CPU to let other hyperthreads progress instead, and again also improves CPU cache behavior.

    Details on PAUSE: felixcloutier.com/x86/pause
    Example from Go runtime: go.dev/src/runtime/asm_amd64.s

    #microarchitecture #golang

  19. Also TIL that CPUs have special hint instructions (called PAUSE on x86) to make spin loops more efficient, which tell the CPU to let other hyperthreads progress instead, and again also improves CPU cache behavior.

    Details on PAUSE: felixcloutier.com/x86/pause
    Example from Go runtime: go.dev/src/runtime/asm_amd64.s

    #microarchitecture #golang

  20. Also TIL that CPUs have special hint instructions (called PAUSE on x86) to make spin loops more efficient, which tell the CPU to let other hyperthreads progress instead, and again also improves CPU cache behavior.

    Details on PAUSE: felixcloutier.com/x86/pause
    Example from Go runtime: go.dev/src/runtime/asm_amd64.s

    #microarchitecture #golang

  21. Also TIL that CPUs have special hint instructions (called PAUSE on x86) to make spin loops more efficient, which tell the CPU to let other hyperthreads progress instead, and again also improves CPU cache behavior.

    Details on PAUSE: felixcloutier.com/x86/pause
    Example from Go runtime: go.dev/src/runtime/asm_amd64.s

    #microarchitecture #golang

  22. Also TIL that CPUs have special hint instructions (called PAUSE on x86) to make spin loops more efficient, which tell the CPU to let other hyperthreads progress instead, and again also improves CPU cache behavior.

    Details on PAUSE: felixcloutier.com/x86/pause
    Example from Go runtime: go.dev/src/runtime/asm_amd64.s

    #microarchitecture #golang

  23. You have less than two weeks left to submit your paper for the final submission cycle at uASC 2026!

    📅 Submission Deadline: November 4, 2025
    👉 uasc.cc

    #microarchitecture #security #conference #uasc26

  24. You have less than two weeks left to submit your paper for the final submission cycle at uASC 2026!

    📅 Submission Deadline: November 4, 2025
    👉 uasc.cc

    #microarchitecture #security #conference #uasc26

  25. You have less than two weeks left to submit your paper for the final submission cycle at uASC 2026!

    📅 Submission Deadline: November 4, 2025
    👉 uasc.cc

    #microarchitecture #security #conference #uasc26

  26. Only one month left to submit your paper for the first submission cycle at uASC 2026!

    📅 Submission Deadline: July 15, 2025
    👉 uasc.cc/

    #microarchitecture #security #conference #uasc26

  27. Only one month left to submit your paper for the first submission cycle at uASC 2026!

    📅 Submission Deadline: July 15, 2025
    👉 uasc.cc/

    #microarchitecture #security #conference #uasc26

  28. Only one month left to submit your paper for the first submission cycle at uASC 2026!

    📅 Submission Deadline: July 15, 2025
    👉 uasc.cc/

    #microarchitecture #security #conference #uasc26

  29. Only one month left to submit your paper for the first submission cycle at uASC 2026!

    📅 Submission Deadline: July 15, 2025
    👉 uasc.cc/

    #microarchitecture #security #conference #uasc26

  30. Only one month left to submit your paper for the first submission cycle at uASC 2026!

    📅 Submission Deadline: July 15, 2025
    👉 uasc.cc/

    #microarchitecture #security #conference #uasc26

  31. SciTech Chronicles. . . . . . . . .April 17th, 2025

    bit.ly/stc041725

    #Donaldjohanson #SwRI #"12.5 light minutes away" #"observation sequence" #raindrops #"plug flow" #10% #"electrically conductive polymer" #"Neurospora crassa" #"Sporosarcina pasteurii" #mineralized #microarchitecture #Hyperadaptor #nickel-based #temperature-insensitive #"sudden or extreme temperature changes" #"high-bed cultivation" #Lidar #disease #pruning

  32. SciTech Chronicles. . . . . . . . .April 17th, 2025

    bit.ly/stc041725

    #Donaldjohanson #SwRI #"12.5 light minutes away" #"observation sequence" #raindrops #"plug flow" #10% #"electrically conductive polymer" #"Neurospora crassa" #"Sporosarcina pasteurii" #mineralized #microarchitecture #Hyperadaptor #nickel-based #temperature-insensitive #"sudden or extreme temperature changes" #"high-bed cultivation" #Lidar #disease #pruning

  33. 📈 Ah, the old "Calculate Throughput with LLVM's Scheduling Model" routine—because nothing screams weekend fun like diving into compiler internals and #microarchitecture performance analysis! 🤓 Just remember, when life gives you throughput, measure it in #IPC and don't forget to bring your inverse throughput for extra giggles. 😂
    myhsu.xyz/llvm-sched-interval- #CalculateThroughput #LLVM #SchedulingModel #CompilerInternals #PerformanceAnalysis #HackerNews #ngated

  34. 📈 Ah, the old "Calculate Throughput with LLVM's Scheduling Model" routine—because nothing screams weekend fun like diving into compiler internals and #microarchitecture performance analysis! 🤓 Just remember, when life gives you throughput, measure it in #IPC and don't forget to bring your inverse throughput for extra giggles. 😂
    myhsu.xyz/llvm-sched-interval- #CalculateThroughput #LLVM #SchedulingModel #CompilerInternals #PerformanceAnalysis #HackerNews #ngated

  35. 📈 Ah, the old "Calculate Throughput with LLVM's Scheduling Model" routine—because nothing screams weekend fun like diving into compiler internals and #microarchitecture performance analysis! 🤓 Just remember, when life gives you throughput, measure it in #IPC and don't forget to bring your inverse throughput for extra giggles. 😂
    myhsu.xyz/llvm-sched-interval- #CalculateThroughput #LLVM #SchedulingModel #CompilerInternals #PerformanceAnalysis #HackerNews #ngated

  36. 📈 Ah, the old "Calculate Throughput with LLVM's Scheduling Model" routine—because nothing screams weekend fun like diving into compiler internals and #microarchitecture performance analysis! 🤓 Just remember, when life gives you throughput, measure it in #IPC and don't forget to bring your inverse throughput for extra giggles. 😂
    myhsu.xyz/llvm-sched-interval- #CalculateThroughput #LLVM #SchedulingModel #CompilerInternals #PerformanceAnalysis #HackerNews #ngated

  37. example: ordering of memory writes.
    on a strongly ordered system, writes are reordered to program order before commiting (actually writing to D$). On a weakly ordered memory system, writes to different locations can happen in different order #uarch #comparch #microarchitecture