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#microarchitecture — Public Fediverse posts

Live and recent posts from across the Fediverse tagged #microarchitecture, aggregated by home.social.

  1. The consumer GPU market isn't in crisis; it's in an undeclared "End of Life" phase. NVIDIA is deliberately starving the AIB supply chain (partners like MSI and Asus) to divert all of TSMC's silicon to AI chips for data centers, where margins are obscene.

    MSI just declared 2026 will be a supply nightmare and is cutting production. They're closing the ecosystem. PC gaming and independent builders have become a nuisance for Jensen Huang's balance sheets.

    I'm compiling logs and market data for a complete autopsy of this commercial architecture. I'll post the full video on my channel. The era of x86 and affordable consumer hardware is coming to an end under the blows of the CUDA monopoly.

    youtube.com/@Rational-Tech-VeLL

    #Hardware #NVIDIA #PCBuild #SysAdmin #TechNews #OpenSource #Microarchitecture #GPU #RationalTech

  2. The consumer GPU market isn't in crisis; it's in an undeclared "End of Life" phase. NVIDIA is deliberately starving the AIB supply chain (partners like MSI and Asus) to divert all of TSMC's silicon to AI chips for data centers, where margins are obscene.

    MSI just declared 2026 will be a supply nightmare and is cutting production. They're closing the ecosystem. PC gaming and independent builders have become a nuisance for Jensen Huang's balance sheets.

    I'm compiling logs and market data for a complete autopsy of this commercial architecture. I'll post the full video on my channel. The era of x86 and affordable consumer hardware is coming to an end under the blows of the CUDA monopoly.

    youtube.com/@Rational-Tech-VeLL

    #Hardware #NVIDIA #PCBuild #SysAdmin #TechNews #OpenSource #Microarchitecture #GPU #RationalTech

  3. The consumer GPU market isn't in crisis; it's in an undeclared "End of Life" phase. NVIDIA is deliberately starving the AIB supply chain (partners like MSI and Asus) to divert all of TSMC's silicon to AI chips for data centers, where margins are obscene.

    MSI just declared 2026 will be a supply nightmare and is cutting production. They're closing the ecosystem. PC gaming and independent builders have become a nuisance for Jensen Huang's balance sheets.

    I'm compiling logs and market data for a complete autopsy of this commercial architecture. I'll post the full video on my channel. The era of x86 and affordable consumer hardware is coming to an end under the blows of the CUDA monopoly.

    youtube.com/@Rational-Tech-VeLL

    #Hardware #NVIDIA #PCBuild #SysAdmin #TechNews #OpenSource #Microarchitecture #GPU #RationalTech

  4. The consumer GPU market isn't in crisis; it's in an undeclared "End of Life" phase. NVIDIA is deliberately starving the AIB supply chain (partners like MSI and Asus) to divert all of TSMC's silicon to AI chips for data centers, where margins are obscene.

    MSI just declared 2026 will be a supply nightmare and is cutting production. They're closing the ecosystem. PC gaming and independent builders have become a nuisance for Jensen Huang's balance sheets.

    I'm compiling logs and market data for a complete autopsy of this commercial architecture. I'll post the full video on my channel. The era of x86 and affordable consumer hardware is coming to an end under the blows of the CUDA monopoly.

    youtube.com/@Rational-Tech-VeLL

    #Hardware #NVIDIA #PCBuild #SysAdmin #TechNews #OpenSource #Microarchitecture #GPU #RationalTech

  5. The consumer GPU market isn't in crisis; it's in an undeclared "End of Life" phase. NVIDIA is deliberately starving the AIB supply chain (partners like MSI and Asus) to divert all of TSMC's silicon to AI chips for data centers, where margins are obscene.

    MSI just declared 2026 will be a supply nightmare and is cutting production. They're closing the ecosystem. PC gaming and independent builders have become a nuisance for Jensen Huang's balance sheets.

    I'm compiling logs and market data for a complete autopsy of this commercial architecture. I'll post the full video on my channel. The era of x86 and affordable consumer hardware is coming to an end under the blows of the CUDA monopoly.

    youtube.com/@Rational-Tech-VeLL

  6. Fun issue: a performance regression between two Rust versions, only on dual socket Zen4c, and does not happen on dual socket Zen4, nor single socket socket Zen4c. github.com/rust-lang/rust/issu

    #RustLang #Bergamo #Genoa #Zen4 #AMD #NUMA #MicroArchitecture

  7. Fun issue: a performance regression between two Rust versions, only on dual socket Zen4c, and does not happen on dual socket Zen4, nor single socket socket Zen4c. github.com/rust-lang/rust/issu

    #RustLang #Bergamo #Genoa #Zen4 #AMD #NUMA #MicroArchitecture

  8. Fun issue: a performance regression between two Rust versions, only on dual socket Zen4c, and does not happen on dual socket Zen4, nor single socket socket Zen4c. github.com/rust-lang/rust/issu

    #RustLang #Bergamo #Genoa #Zen4 #AMD #NUMA #MicroArchitecture

  9. Fun issue: a performance regression between two Rust versions, only on dual socket Zen4c, and does not happen on dual socket Zen4, nor single socket socket Zen4c. github.com/rust-lang/rust/issu

    #RustLang #Bergamo #Genoa #Zen4 #AMD #NUMA #MicroArchitecture

  10. Fun issue: a performance regression between two Rust versions, only on dual socket Zen4c, and does not happen on dual socket Zen4, nor single socket socket Zen4c. github.com/rust-lang/rust/issu

    #RustLang #Bergamo #Genoa #Zen4 #AMD #NUMA #MicroArchitecture

  11. We're so excited to announce that Dries Vanspauwen, @lesly & Jo Van Bulck received the uASC best paper award for the paper "WeMu: Effective and Scalable Emulation of Microarchitectural Weird Machines"! Congratulations! 🎉

    Check it out here: uasc.cc/proceedings26/uasc26-v

    #uasc26 #microarchitecture #security #conference

  12. We're so excited to announce that Dries Vanspauwen, @lesly & Jo Van Bulck received the uASC best paper award for the paper "WeMu: Effective and Scalable Emulation of Microarchitectural Weird Machines"! Congratulations! 🎉

    Check it out here: uasc.cc/proceedings26/uasc26-v

    #uasc26 #microarchitecture #security #conference

  13. We're so excited to announce that Dries Vanspauwen, @lesly & Jo Van Bulck received the uASC best paper award for the paper "WeMu: Effective and Scalable Emulation of Microarchitectural Weird Machines"! Congratulations! 🎉

    Check it out here: uasc.cc/proceedings26/uasc26-v

    #uasc26 #microarchitecture #security #conference

  14. We're so excited to announce that Dries Vanspauwen, @lesly & Jo Van Bulck received the uASC best paper award for the paper "WeMu: Effective and Scalable Emulation of Microarchitectural Weird Machines"! Congratulations! 🎉

    Check it out here: uasc.cc/proceedings26/uasc26-v

    #uasc26 #microarchitecture #security #conference

  15. We're so excited to announce that Dries Vanspauwen, @lesly & Jo Van Bulck received the uASC best paper award for the paper "WeMu: Effective and Scalable Emulation of Microarchitectural Weird Machines"! Congratulations! 🎉

    Check it out here: uasc.cc/proceedings26/uasc26-v

    #uasc26 #microarchitecture #security #conference

  16. "AMD publishes first Zen 6 document detailing ground-up redesign on 2nm process node — brand-new 8-wide CPU core with strong vector capabilities"

    Sounds like they're leaning heavily into 'datacenter' with this one.

    #AMD #Zen6 #Microarchitecture #CPU

    tomshardware.com/pc-components

  17. "AMD publishes first Zen 6 document detailing ground-up redesign on 2nm process node — brand-new 8-wide CPU core with strong vector capabilities"

    Sounds like they're leaning heavily into 'datacenter' with this one.

    #AMD #Zen6 #Microarchitecture #CPU

    tomshardware.com/pc-components

  18. Also TIL that CPUs have special hint instructions (called PAUSE on x86) to make spin loops more efficient, which tell the CPU to let other hyperthreads progress instead, and again also improves CPU cache behavior.

    Details on PAUSE: felixcloutier.com/x86/pause
    Example from Go runtime: go.dev/src/runtime/asm_amd64.s

    #microarchitecture #golang

  19. Also TIL that CPUs have special hint instructions (called PAUSE on x86) to make spin loops more efficient, which tell the CPU to let other hyperthreads progress instead, and again also improves CPU cache behavior.

    Details on PAUSE: felixcloutier.com/x86/pause
    Example from Go runtime: go.dev/src/runtime/asm_amd64.s

    #microarchitecture #golang

  20. Also TIL that CPUs have special hint instructions (called PAUSE on x86) to make spin loops more efficient, which tell the CPU to let other hyperthreads progress instead, and again also improves CPU cache behavior.

    Details on PAUSE: felixcloutier.com/x86/pause
    Example from Go runtime: go.dev/src/runtime/asm_amd64.s

    #microarchitecture #golang

  21. Also TIL that CPUs have special hint instructions (called PAUSE on x86) to make spin loops more efficient, which tell the CPU to let other hyperthreads progress instead, and again also improves CPU cache behavior.

    Details on PAUSE: felixcloutier.com/x86/pause
    Example from Go runtime: go.dev/src/runtime/asm_amd64.s

    #microarchitecture #golang

  22. Also TIL that CPUs have special hint instructions (called PAUSE on x86) to make spin loops more efficient, which tell the CPU to let other hyperthreads progress instead, and again also improves CPU cache behavior.

    Details on PAUSE: felixcloutier.com/x86/pause
    Example from Go runtime: go.dev/src/runtime/asm_amd64.s

    #microarchitecture #golang

  23. You have less than two weeks left to submit your paper for the final submission cycle at uASC 2026!

    📅 Submission Deadline: November 4, 2025
    👉 uasc.cc

    #microarchitecture #security #conference #uasc26

  24. You have less than two weeks left to submit your paper for the final submission cycle at uASC 2026!

    📅 Submission Deadline: November 4, 2025
    👉 uasc.cc

    #microarchitecture #security #conference #uasc26

  25. You have less than two weeks left to submit your paper for the final submission cycle at uASC 2026!

    📅 Submission Deadline: November 4, 2025
    👉 uasc.cc

    #microarchitecture #security #conference #uasc26

  26. AMD Zen 5 Execution Engine Leaked, Features True 512-bit FPU

    Giving "Zen 5" a 512-bit FPU meant that AMD also had to scale up the ancillaries [..]. The L1 Data cache has been doubled in bandwidth, and increased in size by 50%. The L1D is now 48 KB in size [..]. FPU MADD latency has been reduced by 1 cycle. Besides the FPU, AMD also increased the number of Integer execution pipes to 10, from 8 on "Zen 4."

    techpowerup.com/321201/amd-zen

    #AMD #Zen5 #CPU #FPU #AVX512 #Microarchitecture

  27. #Zen4c: #AMD’s Response to #Hyperscale ARM & Intel Atom
    #Bergamo, AMD’s upcoming 128-core server part sets new heights in #x86 #CPU performance. At the heart of Bergamo is #Zen 4c, a brand-new CPU core variant of their successful #5nm #Zen4 #microarchitecture that enables the push toward more cores per socket. Zen 4c enables Bergamo to fit 1.33x the number of cores in the same #SP5 socket and 360W TDP, with identical L1 and 1MB L2 private caches to Zen 4.
    semianalysis.com/p/zen-4c-amds

  28. Only one month left to submit your paper for the first submission cycle at uASC 2026!

    📅 Submission Deadline: July 15, 2025
    👉 uasc.cc/

    #microarchitecture #security #conference #uasc26

  29. Only one month left to submit your paper for the first submission cycle at uASC 2026!

    📅 Submission Deadline: July 15, 2025
    👉 uasc.cc/

    #microarchitecture #security #conference #uasc26

  30. Only one month left to submit your paper for the first submission cycle at uASC 2026!

    📅 Submission Deadline: July 15, 2025
    👉 uasc.cc/

    #microarchitecture #security #conference #uasc26

  31. Only one month left to submit your paper for the first submission cycle at uASC 2026!

    📅 Submission Deadline: July 15, 2025
    👉 uasc.cc/

    #microarchitecture #security #conference #uasc26

  32. Only one month left to submit your paper for the first submission cycle at uASC 2026!

    📅 Submission Deadline: July 15, 2025
    👉 uasc.cc/

    #microarchitecture #security #conference #uasc26

  33. SciTech Chronicles. . . . . . . . .April 17th, 2025

    bit.ly/stc041725

    #Donaldjohanson #SwRI #"12.5 light minutes away" #"observation sequence" #raindrops #"plug flow" #10% #"electrically conductive polymer" #"Neurospora crassa" #"Sporosarcina pasteurii" #mineralized #microarchitecture #Hyperadaptor #nickel-based #temperature-insensitive #"sudden or extreme temperature changes" #"high-bed cultivation" #Lidar #disease #pruning

  34. SciTech Chronicles. . . . . . . . .April 17th, 2025

    bit.ly/stc041725

    #Donaldjohanson #SwRI #"12.5 light minutes away" #"observation sequence" #raindrops #"plug flow" #10% #"electrically conductive polymer" #"Neurospora crassa" #"Sporosarcina pasteurii" #mineralized #microarchitecture #Hyperadaptor #nickel-based #temperature-insensitive #"sudden or extreme temperature changes" #"high-bed cultivation" #Lidar #disease #pruning

  35. 📈 Ah, the old "Calculate Throughput with LLVM's Scheduling Model" routine—because nothing screams weekend fun like diving into compiler internals and #microarchitecture performance analysis! 🤓 Just remember, when life gives you throughput, measure it in #IPC and don't forget to bring your inverse throughput for extra giggles. 😂
    myhsu.xyz/llvm-sched-interval- #CalculateThroughput #LLVM #SchedulingModel #CompilerInternals #PerformanceAnalysis #HackerNews #ngated

  36. 📈 Ah, the old "Calculate Throughput with LLVM's Scheduling Model" routine—because nothing screams weekend fun like diving into compiler internals and #microarchitecture performance analysis! 🤓 Just remember, when life gives you throughput, measure it in #IPC and don't forget to bring your inverse throughput for extra giggles. 😂
    myhsu.xyz/llvm-sched-interval- #CalculateThroughput #LLVM #SchedulingModel #CompilerInternals #PerformanceAnalysis #HackerNews #ngated

  37. 📈 Ah, the old "Calculate Throughput with LLVM's Scheduling Model" routine—because nothing screams weekend fun like diving into compiler internals and #microarchitecture performance analysis! 🤓 Just remember, when life gives you throughput, measure it in #IPC and don't forget to bring your inverse throughput for extra giggles. 😂
    myhsu.xyz/llvm-sched-interval- #CalculateThroughput #LLVM #SchedulingModel #CompilerInternals #PerformanceAnalysis #HackerNews #ngated

  38. 📈 Ah, the old "Calculate Throughput with LLVM's Scheduling Model" routine—because nothing screams weekend fun like diving into compiler internals and #microarchitecture performance analysis! 🤓 Just remember, when life gives you throughput, measure it in #IPC and don't forget to bring your inverse throughput for extra giggles. 😂
    myhsu.xyz/llvm-sched-interval- #CalculateThroughput #LLVM #SchedulingModel #CompilerInternals #PerformanceAnalysis #HackerNews #ngated