#risc5 — Public Fediverse posts

I'm a bit surprised that Niklaus Wirth et al would use Verillog instead of VHDL to implement Oberon RISC5.

Is anyone well-versed enough to try to bring some light on this topic?

I don't have a preference, but with VHDL being so closely related, at least in style, to the Wirth family of languages, it seems at least somewhat interesting that he would choose the language that is less similar to his own.

#FPGA #Wirth #NiklausWirth #Oberon #RISC5 #Algol #Pascal #Modula #VHDL #Verilog