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#risc_v — Public Fediverse posts

Live and recent posts from across the Fediverse tagged #risc_v, aggregated by home.social.

  1. @frameworkcomputer

    As I told earlier here in a longer thread with @zygoon , Yuning Liang, founder of DeepComputing has donated their RISC-V board for Framework laptops to OpenPrinting on the last FOSDEM. Thanks a lot!!

    Now we can test the printing stack on this platform, including making Snaps for RISC-V.

    Printing works so far, by the way.

    And here are my adventures of setting it up:

    openprinting.github.io/OpenPri

    #OpenPrinting #DeepComputing #RISC_V #RISCV #Ubuntu #Snap #FOSDEM #FOSDEM25

  2. Inside SiFive’s P550 Microarchitecture
    🔗 old.chipsandcheese.com/2025/01

    "The P550 is a 3-wide out-of-order core with a 13 stage pipeline. Out-of-order execution lets the core move past a stalled instruction to extract instruction level parallelism. It’s critical for achieving high performance because cache and memory latency can be significant limiters for modern CPUs."

    #RISCV #RISC_V #ComputerArchitecture #CPU #CPUs #Processor #Processors #Hardware #ComputerHardware #Eswin #EC7700X #SiFive #P550