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#risc_v — Public Fediverse posts

Live and recent posts from across the Fediverse tagged #risc_v, aggregated by home.social.

  1. Inside SiFive’s P550 Microarchitecture
    🔗 old.chipsandcheese.com/2025/01

    "The P550 is a 3-wide out-of-order core with a 13 stage pipeline. Out-of-order execution lets the core move past a stalled instruction to extract instruction level parallelism. It’s critical for achieving high performance because cache and memory latency can be significant limiters for modern CPUs."

    #RISCV #RISC_V #ComputerArchitecture #CPU #CPUs #Processor #Processors #Hardware #ComputerHardware #Eswin #EC7700X #SiFive #P550

  2. Got around to porting the #tenstorrent #grayskull e75 to sifive's unmatched rev_b #risc_v devboard.

    The patch should enable both support for non-x86 architectures and riscv support for the grayskull e150.

    The port has rough edges and could definitely benefit from some extra eyes.

    #hpc #supercomputing #ai @risc_v