home.social

Search

1000 results for “craigjb”

  1. @craigjb Who doesn't enjoy 101 #if... #ifndef...? 😆

    Good luck and let us know how it goes.

  2. Long overdue blog post!

    “But what if every button is also a screen?” That’s the question that started a multi-year project to build a custom electronic music production device, the SoundSlab. One glorious day it will be part sequencer, part sampler, part synthesizer, and part slab. Today it’s a never-ending hobby project…

    craigjb.com/2026/01/10/soundsl

  3. It’s a relatively simple example for the SpinalHDL library I've been working on: spiny.

    spinal/Blinky.scala defines the SoC, super short.

    That definition auto-generates a SVD file, which is then fed to svd2rust to create a peripheral access crate (PAC). That gives nice Rusty strucs and methods for accessing all the registers. The rust firmware using it is in fw/src/main.rs.

    github.com/craigjb/spiny/tree/

  4. How do you recruit and train new software engineers? At Made Tech I was responsible for running a regular academy programme, which allowed us to increase diversity and reap many more benefits. In this Making Tech Better podcast episode, I spoke to @craigjbass about how to run a successful academy.

    You can listen here: youtube.com/watch?v=-pMq6GgKQu

    #CSudberyRecordings 

  5. Huh, I haven't had Vivado reduce LUT usage after synthesis like this before—at least not drastically like this.

    This must be the opt_design stage after synthesis? Or does the placement stage really optimize LUT packing like that?

    It's my first timing using “Flow_AreaOptimized_high" and “ExploreArea”.

  6. Nothing like a little BGA reballing practice to get in the mood for bed. These LTM4630Ys are 1.27 mm pitch with 0.75 mm balls. Easy peasy. These 36A DC-DC modules are also $80 each new.

  7. It would definitely make it easier to create smaller versions of the SoundSlab grid too. I like this beast, but being modular has advantages!

    I can manufacture the individual boards cheaper, or even stuff them at home since the boards would fit in my “reflow oven” *cough* toaster oven.

    Also, perhaps someone might want a 4x4 grid for some other fun project.

  8. This lunchtime's crazy idea: what if I split the SoundSlab grid into smaller 4x4 pieces + two 1x8 columns for control on the sides?

    Fitting FFC connectors seemed impossible, but guess what? Vertical FFC connectors exist! A 40 pin vertical FFC connector would fit right between keys on the back.

    The boards would have to be mounted flush next to each other, and there's not really room for board-to-board connectors.

  9. What connectors do people like to use for 12V internal power bussing on their projects? (25-50W ish)

    I've been using these PCIe 12V connectors, but they’re kind of chunky. They're super convenient though since I had a pile of cables in the closet, and buying ready-made cables is cheap.

    There are tons of nice power connector families out there, but often you have to make the cables…

  10. Anyone ever use the standalone generator?
    I

  11. Well that's kind of frustrating. This LiteDRAM DDR2 controller using sim mode (built-in DRAM model) eats the write transaction, eats the read transaction, and then never responds.

    I followed the init_sequence from the generated C code, but I have a hunch more is required.

  12. I see my HDMI RX layout in a new light now that I have a solder-in 4 GHz active differential probe (Lecroy D420-A). The 0402 series caps are pretty small to solder onto (the other passives are the HDMI-to-GTP LR network). The ESD diode array footprint in front of the redriver-retimer is also tempting, but also so small…

  13. It’s my first scope that runs Windows… 7… 😐
    Probably better than Windows 11!

  14. Well, that’s definitely bigger than it looked in the pictures!

  15. I quite like ethernet on FPGAs. It's not that hard to implement, at least this simple case, and a cheap RGMII PHY gives you a gigabit connection with just some ODDRs and IDDRs. There might be a lot more ethernet in my future designs…

  16. It's funny that we get so excited for some LEDs to turn on… but these LEDs mean a lot!

    This is my first time lighting up LEDs by sending an ethernet packet to my soft SoC. All the SpinalHDL, auto SVD generation, auto Rust PAC generation, firmware, and timing constraints worked.

    I've done a bunch of FPGA stuff before, even implementing my own HDMI RX in SpinalHDL without any vendor IP or wrappers on GTP transceivers. But, I've never gotten around to ethernet before now.

  17. Vivado ran for 4h53m overnight for 7,000 SERV cores, and there's room for more!

    Naively, 7000/.83 = 8,433. P&R difficulty increases nonlinearly, so I won't go straight to 8,443. But… how about 8,300? I think I can take second place 😎

    #FPGA #CoreScore #SERV #PointlesslyCompetitive

  18. Vivado ran for 4h53m overnight for 7,000 SERV cores, and there's room for more!

    Naively, 7000/.83 = 8,433. P&R difficulty increases nonlinearly, so I won't go straight to 8,443. But… how about 8,300? I think I can take second place 😎

  19. Vivado ran for 4h53m overnight for 7,000 SERV cores, and there's room for more!

    Naively, 7000/.83 = 8,433. P&R difficulty increases nonlinearly, so I won't go straight to 8,443. But… how about 8,300? I think I can take second place 😎

    #FPGA #CoreScore #SERV #PointlesslyCompetitive

  20. Vivado ran for 4h53m overnight for 7,000 SERV cores, and there's room for more!

    Naively, 7000/.83 = 8,433. P&R difficulty increases nonlinearly, so I won't go straight to 8,443. But… how about 8,300? I think I can take second place 😎

    #FPGA #CoreScore #SERV #PointlesslyCompetitive