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#p550 — Public Fediverse posts

Live and recent posts from across the Fediverse tagged #p550, aggregated by home.social.

  1. A #RISCV Progress Check: Benchmarking #P550 and #C910
    The RISC-V cores fall short of Ar #CortexA73 and well short of Intel’s #Goldmont Plus. Mediatek’s In-Order #Genio1200 hyas higher clock speeds and better DRAM latency than C910 and P550. Its #CortexA55 cores are able to catch C910 and P550 without out-of-order execution.
    #SiFive’s P550 and T-HEAD’s Xuantie C910 are both notable for featuring out-of-order execution on RISC-V. Both are plagued by low clock speeds.
    chipsandcheese.com/p/a-risc-v-

  2. A #RISCV Progress Check: Benchmarking #P550 and #C910
    The RISC-V cores fall short of Ar #CortexA73 and well short of Intel’s #Goldmont Plus. Mediatek’s In-Order #Genio1200 hyas higher clock speeds and better DRAM latency than C910 and P550. Its #CortexA55 cores are able to catch C910 and P550 without out-of-order execution.
    #SiFive’s P550 and T-HEAD’s Xuantie C910 are both notable for featuring out-of-order execution on RISC-V. Both are plagued by low clock speeds.
    chipsandcheese.com/p/a-risc-v-

  3. A Progress Check: Benchmarking and
    The RISC-V cores fall short of Ar and well short of Intel’s Plus. Mediatek’s In-Order hyas higher clock speeds and better DRAM latency than C910 and P550. Its cores are able to catch C910 and P550 without out-of-order execution.
    ’s P550 and T-HEAD’s Xuantie C910 are both notable for featuring out-of-order execution on RISC-V. Both are plagued by low clock speeds.
    chipsandcheese.com/p/a-risc-v-

  4. A #RISCV Progress Check: Benchmarking #P550 and #C910
    The RISC-V cores fall short of Ar #CortexA73 and well short of Intel’s #Goldmont Plus. Mediatek’s In-Order #Genio1200 hyas higher clock speeds and better DRAM latency than C910 and P550. Its #CortexA55 cores are able to catch C910 and P550 without out-of-order execution.
    #SiFive’s P550 and T-HEAD’s Xuantie C910 are both notable for featuring out-of-order execution on RISC-V. Both are plagued by low clock speeds.
    chipsandcheese.com/p/a-risc-v-

  5. A #RISCV Progress Check: Benchmarking #P550 and #C910
    The RISC-V cores fall short of Ar #CortexA73 and well short of Intel’s #Goldmont Plus. Mediatek’s In-Order #Genio1200 hyas higher clock speeds and better DRAM latency than C910 and P550. Its #CortexA55 cores are able to catch C910 and P550 without out-of-order execution.
    #SiFive’s P550 and T-HEAD’s Xuantie C910 are both notable for featuring out-of-order execution on RISC-V. Both are plagued by low clock speeds.
    chipsandcheese.com/p/a-risc-v-

  6. Inside #SiFive’s #P550 #RISCV Microarchitecture
    It doesn’t go head-on against likes of AMD’s Zen 5, Intel’s Lion Cove, or Qualcomm’s Oryon. P550’s out-of-order engine is closer in size to something like Intel’s Core 2 from over 15 yrs ago. Combine that with much lower clock speeds than even what Core 2 ran at, and P550 is really a low power core with modest performance. This core aims for “30% higher performance in less than half the area of a comparable Arm Cortex A75.”
    chipsandcheese.com/p/inside-si

  7. Inside SiFive’s P550 Microarchitecture
    🔗 old.chipsandcheese.com/2025/01

    "The P550 is a 3-wide out-of-order core with a 13 stage pipeline. Out-of-order execution lets the core move past a stalled instruction to extract instruction level parallelism. It’s critical for achieving high performance because cache and memory latency can be significant limiters for modern CPUs."

    #RISCV #RISC_V #ComputerArchitecture #CPU #CPUs #Processor #Processors #Hardware #ComputerHardware #Eswin #EC7700X #SiFive #P550

  8. #SiFive #HiFive Premier #P550 #RISCV Price Lowered to $399, ready to go with #Ubuntu 24.04 LTS Support
    This RISC-V developer board features the SiFive P550 CPU, 128GB eMMC storage, 16GB or 32GB of LPDDR5 memory, PCIe connectivity, M.2 storage support, USB 3, and more.
    phoronix.com/news/HiFive-Premi