#eswin — Public Fediverse posts

Linux 6.19 Release – Main changes, Arm, RISC-V, and MIPS architectures

https://fed.brid.gy/r/https://www.cnx-software.com/2026/02/09/linux-6-19-release-main-changes-arm-risc-v-and-mips-architectures/

Inside SiFive’s P550 Microarchitecture
🔗 https://old.chipsandcheese.com/2025/01/26/inside-sifives-p550-microarchitecture/

"The P550 is a 3-wide out-of-order core with a 13 stage pipeline. Out-of-order execution lets the core move past a stalled instruction to extract instruction level parallelism. It’s critical for achieving high performance because cache and memory latency can be significant limiters for modern CPUs."

#RISCV #RISC_V #ComputerArchitecture #CPU #CPUs #Processor #Processors #Hardware #ComputerHardware #Eswin #EC7700X #SiFive #P550

#SiFive selects a faster #China-made #RISCV #CPU instead of an #Intel chip for its latest board
#HiFivePremierP550 will be first commercial out-of-order RISC-V dev board.#P550 has 16GB of LPDDR5-6400, a 128GB eMMC SSD for "fast bootable" storage. A single PCIe 3.0 x4 interface along with five USB 3.2 Gen 1 ports. The #Eswin #EIC7700 SoC features four P550 cores, 256KB of L2 cache, and 4MB of L3 cache. Superscalar P550 can issue three instructions per cycle per core.
https://www.tomshardware.com/pc-components/cpus/sifive-selects-a-faster-chinese-made-risc-v-cpu-instead-of-an-intel-chip-for-its-latest-development-board