#risc-v — Public Fediverse posts

so I want a RPi-like RISC-V board

(don't care about the RPi form factor, the board can be larger)

PINE64 or Milk-V, or does anyone have another preference?

#RISCV #riscv64

🤣 Oh joy, another #DIY guide that assumes you're a silicon wizard just for getting an emulator to sputter out a #Linux boot screen. 🚀 Spoiler alert: you'll spend more time on #GitHub than you will on actual #emulation, but hey, at least you can brag about your "RISCV rv32ima" knowledge at parties... if you ever get invited! 😜
https://github.com/WerWolv/riscv-emulator #RISCV #Humor #HackerNews #ngated

I will attend the ESA Industry Space Days next week. I would be happy to meet and discuss our #RTEMS, #Linux, #NuttX, communication, #canbus, #SpaceWire, IP cores related work. Some examples

• for RTEMS CAN/CAN FD, there is near to merge Ti AM335x suport, result of this year Ning Zhang #GSoC
• motion control at #PiKRON (used by ESA for #satellite tracking and for LISA ground experiment), and at #CVUT (SaMoCon)
• for rapid prototyping CTU Simulink™ support for Linux and NuttX which can be easily extended for RTEMS and open-source pysimCoder which already target Linux, NuttX and RTEMS (ongoing preparation for Ahmad Hisham’ s thesis)
• the CTU CAN FD IP core is already available on mass produced MCU COTS silicon in addition to multiple FPGA applications including space ones
• RTEMS LwIP port started as our experiment during Premysl Houdek’s thesis and #GSoC is getting traction and was used at docking computer during Artems II mission (by the way, there will be presentation about the mission at #cvutfel by Milan Halousek at Sptember 24) and is used on TMS570 and ESP32C3 RTEMS ports
• our SumInt ADC conversion principle used in our HPLC instruments and tested at #nanoXplore for ESA which can have interesting potential for space silicon
• our NuttX support for IEEE 802.3cg 10BASE−T1S Open Alliance SPI MACPHY can be ported to RTEMS etc.
• I offer support for CAN/CAN FD emulation on #QEMU, #FlexCAN added this year
• lot of our other real-time work for Linux, NuttX and RTEMS, se my university Open Technologies Research Education and Exchange Services topics and theses lists
• we invest lot into #RISCV education at CTU, see our https://comparch.edu.cvut.cz/ pages with #QtRvSim emulator and our HDL education and sometimes even practically used cores and experiments

I arrive to Noordwijk around the lunch time on Tuesday September 15 and stay there to about 2 PM on Friday so there is lot of options to meet.

Little sneak preview #RISCV #SpacemiT #Buildroot

That's great one patch less #bcachefs #RISCV cross-compilation on #NixOS https://github.com/NixOS/nixpkgs/pull/561500

Thank you @JamieMagee

Положил http:// в строку, и ассемблер молча собрал 0 байт

Мой ассемблер резал исходник построчными правилами: срезал комментарий, искал двоеточие, делил по запятым. Я заменил это одним проходом с состоянием и попутно проверил, нельзя ли было обойтись заплатками. Нельзя: вторая заплатка ломает то, что починила первая. Куда делись байты?

https://habr.com/ru/articles/1080490/

#лексер #токенизатор #разбор_текста #ассемблер #RISCV #комментарии #строковые_литералы #регрессия #RV32I

Comitting crimes with LLVM and RISC-V.

More seriously: just exploring whether we could have a similar thing to "expand integer" but for vectors of integer elements.

#llvm #riscv #rvv

So, #OSH is way out of my wheelhouse, though I have plans to acquire a cheap FPGA and start experimenting with it at my earlist fiscal convenience...

but, can anyone tell me what are the biggest difficulties involved in creating an Open Source GPU, similar to #RiscV with CPUs?

I realize this is not simple stuff, but given we've had math coprocessors at least as far back as the 8088, it also doesn't seem especially exotic, technologywise.

Is it strictly a matter of needing a lot more money, because hardware is not software? That seems the likeliest explanation, along with, 50 years of Milton Friedman has drained the academy of brains while all those gratuitous engineers from the war were dying off.

Not my own book this time, but embedded firmware is close to my heart — it's what robots run on under the hood.

My publisher (Packt) has put together the Embedded Firmware Developer Toolkit: 15+ books covering microcontrollers, C/C++, ARM Cortex-M, RTOS, embedded Linux, device drivers, debugging, RISC-V and more — on Humble Bundle now.

👉 https://www.humblebundle.com/books/embedded-firmware-developer-toolkit-packt-books

#Embedded #Firmware #Robotics #RISCV

Freshly updated guide to #RISCV friendly #Linux distros and #BSDs here: https://www.newinlinux.com/these-linux-distributions-support-risc-v/

يدعم CPython الآن بشكل رسمي معمارية RISC-V، وذلك بإضافتها إلى PEP 11. جاء هذا الإنجاز نتيجة لجهود مجتمعية مكثفة، شملت الاختبار على الأجهزة الحقيقية، وإصلاحات خاصة بالمعمارية، ودعم البناء، وتقديم تقارير الأخطاء، ومراجعة التصحيحات. كما ساهم مشروع RISE بتوفير أجهزة RISC-V لـ CPython buildbots وأغراض التصحيح، مما يعزز تبني هذه المعمارية الواعدة في بيئة بايثون.

#CPython #RISCV #Python

@cnlohr no, there isn't. we need to fork 8 bit, maaaaybe disassembly 16 bit #geos and start right there, on #riscv mcus. only technical way to avoid slop is to make project uninteresting from slop masters perspective - "simple and primitive", and easier to comprehend and reason about for homo sapiens. (i am fooling around here obviously, but i feel that the direction, as crazy as it sounds, deserves playful exploration)

Today, I am at the Open Source Hardware Camp 2026 in Hebden Bridge 🚀.

https://oshug.org/event/oshcamp2026

#oshcamp2026 #oshcamp #OpenSource #OpenSourceHardware #RISCV #Engineering

Написал свой ассемблер, чтобы понять, откуда берётся ff010113. Почти половину моей программы он выдумывает

Написал свой ассемблер, чтобы понять, откуда в дизассемблере берётся ff010113. Заодно посчитал, сколько строк моей программы процессор вообще не умеет исполнять, и проверил это на четырёх наборах команд, включая живой ESP32 на столе. На кристалле первая программа серии сломалась: она пишет в UART быстрее, чем провод успевает передавать, и в эмуляторе этого не видно. Что сказала плата?

https://habr.com/ru/articles/1076022/

#RISCV #ассемблер #кодирование_инструкций #псевдоинструкции #RV32I #компоновщик #релокация #bare_metal #QEMU

First Risc-V server! https://chipsandcheese.com/p/sifives-first-server-platform #riscv

Apparently I have not had enough open source hardware, electronics and engineering rabbit holes recently 🤣🙈.

So this weekend I am off to Open Source Hardware Camp 2026 in Hebden Bridge 🚀.

https://oshug.org/event/oshcamp2026

#oshcamp2026 #OpenSourceHardware #OpenSource #RISCV #Engineering

Freecpm is a CP/M inspired operating system that runs on RISC-V platforms.

https://github.com/Mazin-O3/freecpm

#retrocomputing #operatingsystem #cpm #opensource #riscv

@stanfromireland:
“Over the last few months, I’ve been working on improving #CPython’s support for the #RISCV architecture, and I’m thrilled to announce that RISC-V is now officially supported by CPython as a tier 3 platform!

“RISC-V is an open instruction set architecture (ISA). Importantly, unlike proprietary instruction sets (such as x86 and ARM), it is developed as an open standard and can be implemented by anyone.”

https://blog.python.org/2026/08/riscv-now-officially-supported/

#Python

CPython now officially supports #riscv

https://blog.python.org/2026/08/riscv-now-officially-supported/

With the hard work of a number of core team members, especially @stanfromireland RISC-V is now a Tier 3 platform as laid out in PEP 11 https://peps.python.org/pep-0011/