#risc-v — Public Fediverse posts

Apparently I have not had enough open source hardware, electronics and engineering rabbit holes recently 🤣🙈.

So this weekend I am off to Open Source Hardware Camp 2026 in Hebden Bridge 🚀.

https://oshug.org/event/oshcamp2026

#oshcamp2026 #OpenSourceHardware #OpenSource #RISCV #Engineering

Freecpm is a CP/M inspired operating system that runs on RISC-V platforms.

https://github.com/Mazin-O3/freecpm

#retrocomputing #operatingsystem #cpm #opensource #riscv

@stanfromireland:
“Over the last few months, I’ve been working on improving #CPython’s support for the #RISCV architecture, and I’m thrilled to announce that RISC-V is now officially supported by CPython as a tier 3 platform!

“RISC-V is an open instruction set architecture (ISA). Importantly, unlike proprietary instruction sets (such as x86 and ARM), it is developed as an open standard and can be implemented by anyone.”

https://blog.python.org/2026/08/riscv-now-officially-supported/

#Python

CPython now officially supports #riscv

https://blog.python.org/2026/08/riscv-now-officially-supported/

With the hard work of a number of core team members, especially @stanfromireland RISC-V is now a Tier 3 platform as laid out in PEP 11 https://peps.python.org/pep-0011/

If anyone's wondering how things are going with #RiscV

https://www.youtube.com/watch?v=XWJICnlKUts

От Цифровой Логики к Процессору через ПЛИС. Программа годового курса для школьников физматшкол

В картине мира, представляемой школьным образованием, существует “слепое пятно” в области принципов проектирования цифровой электроники, между физикой и программированием. Курсы роботики и ардуино это слепое пятно не закрывают, так как сводятся к программированию готовых чипов и их интеграции с сенсорами и актуаторами, то бишь проектированию систем.

https://habr.com/ru/articles/1071736/

#cmos_4000 #7400 #gowin #altera #xilinx #riscv #обучение_школьников #плис #школа_не_в_замке #verilog_meetup

A little light weekend reading...
#assembly #x86 #riscv #arm #mips

AROS für RISC-V

Nick 'Kalamatee' Andrews hat in den letzten Wochen an der Portierung von AROS auf die RISC-V-Architektur gearbeitet. Nun sind die Builds stabil und enthalten alle aktuellen AROS-Funktionen wie USB 3.0 und Unterstützung für NVIDIA-Treiber bis hin zu Blackwell-GPUs.

https://www.amiga-news.de/de/news/AN-2026-08-00122-DE.html

#AROS #RISCV #retrocomputing

AROS for RISC-V

Nick 'Kalamatee' Andrews has been working on porting AROS to the RISC-V architecture over the past few weeks. The builds are now stable and include all the latest AROS features, such as USB 3.0 and support for NVIDIA drivers, right up to Blackwell GPUs.

https://www.amiga-news.de/en/news/AN-2026-08-00122-EN.html

#AROS #retrocomputing #RISCV

New preprint: Porting and Benchmarking Chapel on Emerging RISC-V Hardware: an HPC Viability Study

https://arxiv.org/abs/2608.14799

#riscv #chapel #hpc

“A Third World Embedded Engineer Responds to ‘RISC-V: They Should Have Known Better’”, Armstrong Subero, RV Embedded (https://rvembedded.com/blog_post/12/).

Via HN: https://news.ycombinator.com/item?id=49321717

On Lobsters: https://lobste.rs/s/zeqgd4/third_world_embedded_engineer_responds

#RISCV #CPU #Embedded #Hardware #ISA

#Luanti made its way to the #T2Linux stand, running on #RISCV

RISC-V: They Should Have Known Better

https://dmitry.gr/?r=06.%20Thoughts&proj=12.%20RV

#RISCV #embedded #ISA

@csepp On the other hand, the #RiscV specification is about 500 pages, whereas the #ARM one is FIFTEEN THOUSAND PAGES. I'll put up with a lot for not having even to prune out the parts of that mountain that I don't think I'll need to read.

Interesting (if a bit sweary) critique of #RISCV . Quoting from the very end of it:
"Before you get your megaphone to shout about "openness", please note that the openness of the RISC-V spec is not relevant here at all, because an open spec does not magically materialize a well-designed out-of-order core for you for free. And if someone were to design a good out-of-order core, they would not be giving it away for free."
https://dmitry.gr/?r=06.%20Thoughts&proj=12.%20RV

🥱 Ah, yet another illuminating #manifesto on why #RISCV is apparently the #engineering equivalent of pineapple on pizza. Many words, much eye-rolling—because clearly, the galaxy-brained masses just don’t grasp the transcendent genius of Dmitry's #disdain. 🚀✨
https://dmitry.gr/?r=06.%20Thoughts&proj=12.%20RV #PineappleOnPizza #Dmitry #GalaxyBrained #HackerNews #ngated

😬:

“RISC-V: They Should Have Known Better”, Dmitry GR (https://dmitry.gr/?r=06.%20Thoughts&proj=12.%20RV).

Via HN: https://news.ycombinator.com/item?id=49305492

On Lobsters: https://lobste.rs/s/pu3yzg/risc_v_they_should_have_known_better

#RISCV #RISC #CPU #ISA #ComputerArchitecture #Hardware #InstructionSet #Rants #Critique

Hi, I'm Jenning. I'm solo developing my own operating system, Open Nexus OS: for RISC-V only, written in Rust — a small capability-based microkernel, and its own UI language. It now boots to a real desktop with apps, still QEMU-only for now.

I have a blog for details:
https://open-nexus-os.io/blog/why-another-rust-microkernel-os

Try to post updates from now on.

#introduction #rustlang #riscv #osdev #opensource

Нельзя просто взять и прочитать 64-битный SysTick на CH32V203

Когда я начал работать с CH32V203G6U6 и обнаружил, что там есть 64-битный аппаратный таймер, то подумал: ух, это же отлично, раз таймер аппаратный, то и о чтении/записи заботится сам микроконтроллер. И какое-то время это не вызывало вопросов. А потом…

https://habr.com/ru/articles/1068444/

#wch #embedded #c_language #assembler #riscv #debug #systick