#hifive — Public Fediverse posts
Live and recent posts from across the Fediverse tagged #hifive, aggregated by home.social.
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24th Director’s Cut Awards Announces Nominees
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Porting xv6 to HiFive Unmatched board
https://github.com/eyengin/xv6-riscv-unmatched
#HackerNews #Porting #xv6 #to #HiFive #Unmatched #board #xv6 #HiFiveUnmatched #RISC-V #open-source #programming #embeddeddevelopment
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Winners Of The 46th Blue Dragon Film Awards
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Winners Of The 46th Blue Dragon Film Awards
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Winners Of The 46th Blue Dragon Film Awards
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Winners Of The 46th Blue Dragon Film Awards
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Winners Of The 46th Blue Dragon Film Awards
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We've updated our tor relay build script for #RISCV, building #openssl and #tor from source:
https://code.disobey.net/EmeraldOnion/tor-openssl-riscv/
Notably, to get rid of this tor initialization warning:
> We were built to run on a 64-bit CPU, with OpenSSL 1.0.1 or later, but with a version of OpenSSL that apparently lacks accelerated support for the NIST P-224 and P-256 groups. Building openssl with such support (using the enable-ec_nistp_64_gcc_128 option when configuring it) would make ECDH much faster.With an added openssl configure target and option:
> linux64-riscv64 enable-ec_nistp_64_gcc_128Our #SiFive #HiFive RISC-V 256-bits ECDH performance is synthetically boosted:
From:
> 256 bits ecdh (nistp256) 0.0029s 340.7To:
> 256 bits ecdh (nistp256) 0.0005s 2057.1This is a 6x P-256 handshakes boost, so this should help speed up this Tor exit relay. We are only running one Tor daemon on this hardware to see how well it does.
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#SiFive #HiFive Premier #P550 #RISCV Price Lowered to $399, ready to go with #Ubuntu 24.04 LTS Support
This RISC-V developer board features the SiFive P550 CPU, 128GB eMMC storage, 16GB or 32GB of LPDDR5 memory, PCIe connectivity, M.2 storage support, USB 3, and more.
https://www.phoronix.com/news/HiFive-Premier-P550-Drop