#neorv32 — Public Fediverse posts

YAY, #neorv32 built with a VERY simple memory interface which I've connected to LEDs on my #Alchitry #FPGA board
I can now send data via memory to my own custom blocks (I think).

Next step is to figure out the memory mapping proper.

Geilo, after days of trying to figure out how it works, I finally got a Xilinx axi_uart16550 behind a PCI Express endpoint to work as a practically auto-detected tty on Linux, modifying the 8250_pci driver.

So, now there’s /dev/ttyS4 directly talking to a #neorv32 softcore #riscv MCU on an #FPGA.

Now, to clean-up and understanding what I’ve actually done.

#linux #kernel #module #driver #tinkering

Oh, wow, I am pleased af. I started looking into #neorv32, an #foss RISC-V soft-core MCU (i.e. it’s written in VHDL and can be synthesized onto an FPGA) is working smooth and nicely.
This is so much better an experience than what I’ve had so far with commercial stuff (yes, looking at you Xilinx)!

You go through the docs, find everything, get everything explained with no superfluous BS. The examples work right away. The docs even explain how to set up the gcc toolchain for riscv32 (Ubuntu seems to only come with a riscv64 toolchain).

And there you go: One 100 line VHDL top file (out of which only 22 lines are devoted to the neorv32 soc), some serial terminal (don’t use minicom, just don’t) and one 30 line C example later, I’ve got the blinks! (Bare in mind: I’m absolutely not an embedded dev!)

https://github.com/stnolting/neorv32

Custom RISC-V Processor Built in VHDL - While ARM continues to make inroads into the personal computing market against tra... - https://hackaday.com/2021/08/03/custom-risc-v-processor-built-in-vhdl/ #softwarehacks #opensource #hardware #neorv32 #risc-v #fpga #vhdl #soc