#cocotb — Public Fediverse posts

Presented my experiences using #cocotb professionaly at FPGA Forum in Trondheim two weeks ago.

https://www.linkedin.com/posts/eidsvoll-electronics-as_eidel-at-fpga-forum-2026-eidel-engelsk-activity-7432046803782438912-76yk?utm_source=social_share_send&utm_medium=android_app&rcm=ACoAACZpHL8B95Cn3a9XFUW06rkzrFc7CgvHSps&utm_campaign=copy_link

Isle Verilog modules include #cocotb tests and reference docs. Writing docs is time consuming but worthwhile. It's hard to learn from existing designs without them. #FPGA

Here's a simple example; it could be better, but it's something to build on: https://github.com/projf/isle/blob/main/hardware/gfx/doc/display.md

Isle Verilog modules include #cocotb tests and reference docs. Writing docs is time consuming but worthwhile. It's hard to learn from existing designs without them. #FPGA

Here's a simple example; it could be better, but it's something to build on: https://github.com/projf/isle/blob/main/hardware/gfx/doc/display.md

Isle Verilog modules include #cocotb tests and reference docs. Writing docs is time consuming but worthwhile. It's hard to learn from existing designs without them. #FPGA

Here's a simple example; it could be better, but it's something to build on: https://github.com/projf/isle/blob/main/hardware/gfx/doc/display.md

Isle Verilog modules include #cocotb tests and reference docs. Writing docs is time consuming but worthwhile. It's hard to learn from existing designs without them. #FPGA

Here's a simple example; it could be better, but it's something to build on: https://github.com/projf/isle/blob/main/hardware/gfx/doc/display.md

Isle Verilog modules include #cocotb tests and reference docs. Writing docs is time consuming but worthwhile. It's hard to learn from existing designs without them. #FPGA

Here's a simple example; it could be better, but it's something to build on: https://github.com/projf/isle/blob/main/hardware/gfx/doc/display.md

The search engines are failing me.

Dear Lazy Web:
If I wanted to enumerate the hierarchy of a design at the beginning of a cocotb test bench, how would I do it? (I'm aware of _discover_all(), but can't figure out how to iterate the results to print them.)

Extra credit: How do I get an interactive debugger to break within the cocotb python code if I call cocotb from pytest? It seems to run the pytest code in the debugger, but not the cocotb code.

#fpga #cocotb #lazyweb #python #vhdl #verilog

The search engines are failing me.

Dear Lazy Web:
If I wanted to enumerate the hierarchy of a design at the beginning of a cocotb test bench, how would I do it? (I'm aware of _discover_all(), but can't figure out how to iterate the results to print them.)

Extra credit: How do I get an interactive debugger to break within the cocotb python code if I call cocotb from pytest? It seems to run the pytest code in the debugger, but not the cocotb code.

#fpga #cocotb #lazyweb #python #vhdl #verilog

The search engines are failing me.

Dear Lazy Web:
If I wanted to enumerate the hierarchy of a design at the beginning of a cocotb test bench, how would I do it? (I'm aware of _discover_all(), but can't figure out how to iterate the results to print them.)

Extra credit: How do I get an interactive debugger to break within the cocotb python code if I call cocotb from pytest? It seems to run the pytest code in the debugger, but not the cocotb code.

#fpga #cocotb #lazyweb #python #vhdl #verilog

The search engines are failing me.

Dear Lazy Web:
If I wanted to enumerate the hierarchy of a design at the beginning of a cocotb test bench, how would I do it? (I'm aware of _discover_all(), but can't figure out how to iterate the results to print them.)

Extra credit: How do I get an interactive debugger to break within the cocotb python code if I call cocotb from pytest? It seems to run the pytest code in the debugger, but not the cocotb code.

#fpga #cocotb #lazyweb #python #vhdl #verilog

The search engines are failing me.

Dear Lazy Web:
If I wanted to enumerate the hierarchy of a design at the beginning of a cocotb test bench, how would I do it? (I'm aware of _discover_all(), but can't figure out how to iterate the results to print them.)

Extra credit: How do I get an interactive debugger to break within the cocotb python code if I call cocotb from pytest? It seems to run the pytest code in the debugger, but not the cocotb code.

#fpga #cocotb #lazyweb #python #vhdl #verilog

@Tathar I would like to see a good one too. I'm all my years doing #vhdl and #verilog for a living the best test benches I ever have seen have just read in golden vectors and wrote out result vectors so they could be checked by an external script. We now use #cocotb and I'm starting to like it. I don't feel an hdl is a good match for testbench work. Maybe for a fixture layer connecting hdl blocks. But testbenches are not hardware. Why would we expect an hdl would do well for it?

@Tathar I would like to see a good one too. I'm all my years doing #vhdl and #verilog for a living the best test benches I ever have seen have just read in golden vectors and wrote out result vectors so they could be checked by an external script. We now use #cocotb and I'm starting to like it. I don't feel an hdl is a good match for testbench work. Maybe for a fixture layer connecting hdl blocks. But testbenches are not hardware. Why would we expect an hdl would do well for it?

@Tathar I would like to see a good one too. I'm all my years doing #vhdl and #verilog for a living the best test benches I ever have seen have just read in golden vectors and wrote out result vectors so they could be checked by an external script. We now use #cocotb and I'm starting to like it. I don't feel an hdl is a good match for testbench work. Maybe for a fixture layer connecting hdl blocks. But testbenches are not hardware. Why would we expect an hdl would do well for it?

@Tathar I would like to see a good one too. I'm all my years doing #vhdl and #verilog for a living the best test benches I ever have seen have just read in golden vectors and wrote out result vectors so they could be checked by an external script. We now use #cocotb and I'm starting to like it. I don't feel an hdl is a good match for testbench work. Maybe for a fixture layer connecting hdl blocks. But testbenches are not hardware. Why would we expect an hdl would do well for it?

Implementing HDL verification using #UVM is annoying and tedious. So #cocotb seems to be the right choice. #FPGA #Python #systemverilog #VHDL

Implementing HDL verification using #UVM is annoying and tedious. So #cocotb seems to be the right choice. #FPGA #Python #systemverilog #VHDL

Implementing HDL verification using #UVM is annoying and tedious. So #cocotb seems to be the right choice. #FPGA #Python #systemverilog #VHDL

Implementing HDL verification using #UVM is annoying and tedious. So #cocotb seems to be the right choice. #FPGA #Python #systemverilog #VHDL

Implementing HDL verification using #UVM is annoying and tedious. So #cocotb seems to be the right choice. #FPGA #Python #systemverilog #VHDL

@remi Yeah my whole group gave up on mathworks (and Microsoft). We do everything in python now with boost c++ for some bits (on linux). No more dealing with license servers is great. We stimulate on a cluster of machines now and never worry about running out of licenses. It's great. Now when we can get rid of #modelsim we will be ~100% #foss tool chain. #ghdl and or #cvc with #cocotb is close but not quite. Xilinx #vivado encrypted ip cores are a problem that can only be avoided by saying no...

@remi Yeah my whole group gave up on mathworks (and Microsoft). We do everything in python now with boost c++ for some bits (on linux). No more dealing with license servers is great. We stimulate on a cluster of machines now and never worry about running out of licenses. It's great. Now when we can get rid of #modelsim we will be ~100% #foss tool chain. #ghdl and or #cvc with #cocotb is close but not quite. Xilinx #vivado encrypted ip cores are a problem that can only be avoided by saying no...

@remi Yeah my whole group gave up on mathworks (and Microsoft). We do everything in python now with boost c++ for some bits (on linux). No more dealing with license servers is great. We stimulate on a cluster of machines now and never worry about running out of licenses. It's great. Now when we can get rid of #modelsim we will be ~100% #foss tool chain. #ghdl and or #cvc with #cocotb is close but not quite. Xilinx #vivado encrypted ip cores are a problem that can only be avoided by saying no...

@remi Yeah my whole group gave up on mathworks (and Microsoft). We do everything in python now with boost c++ for some bits (on linux). No more dealing with license servers is great. We stimulate on a cluster of machines now and never worry about running out of licenses. It's great. Now when we can get rid of #modelsim we will be ~100% #foss tool chain. #ghdl and or #cvc with #cocotb is close but not quite. Xilinx #vivado encrypted ip cores are a problem that can only be avoided by saying no...

I have a nominally working simulation of a PI controller for the quadrature current in my scratch designed #fpga motor controller. Simulated in #ghdl and #cocotb. And the #xilinx ISE build fits! So I'm back to looking at the blown up hardware. Just pulled the scratch designed motor controller out of the Ice Cream Truck... I don't see a blown FET yet, but I saw a flash and pop the last time I worked on it, so I know it's in there somewhere. Race is on May 20th in #chicago Come out and help me!

I have a nominally working simulation of a PI controller for the quadrature current in my scratch designed #fpga motor controller. Simulated in #ghdl and #cocotb. And the #xilinx ISE build fits! So I'm back to looking at the blown up hardware. Just pulled the scratch designed motor controller out of the Ice Cream Truck... I don't see a blown FET yet, but I saw a flash and pop the last time I worked on it, so I know it's in there somewhere. Race is on May 20th in #chicago Come out and help me!

I have a nominally working simulation of a PI controller for the quadrature current in my scratch designed #fpga motor controller. Simulated in #ghdl and #cocotb. And the #xilinx ISE build fits! So I'm back to looking at the blown up hardware. Just pulled the scratch designed motor controller out of the Ice Cream Truck... I don't see a blown FET yet, but I saw a flash and pop the last time I worked on it, so I know it's in there somewhere. Race is on May 20th in #chicago Come out and help me!

I have a nominally working simulation of a PI controller for the quadrature current in my scratch designed #fpga motor controller. Simulated in #ghdl and #cocotb. And the #xilinx ISE build fits! So I'm back to looking at the blown up hardware. Just pulled the scratch designed motor controller out of the Ice Cream Truck... I don't see a blown FET yet, but I saw a flash and pop the last time I worked on it, so I know it's in there somewhere. Race is on May 20th in #chicago Come out and help me!

Yay, my #riscv implementation in spade is now far along that I can run ISA tests.

#cocotb makes it really simple to generate test cases from the compiled elf files in https://github.com/riscv-software-src/riscv-tests

Yay, my #riscv implementation in spade is now far along that I can run ISA tests.

#cocotb makes it really simple to generate test cases from the compiled elf files in https://github.com/riscv-software-src/riscv-tests

Yay, my #riscv implementation in spade is now far along that I can run ISA tests.

#cocotb makes it really simple to generate test cases from the compiled elf files in https://github.com/riscv-software-src/riscv-tests

Yay, my #riscv implementation in spade is now far along that I can run ISA tests.

#cocotb makes it really simple to generate test cases from the compiled elf files in https://github.com/riscv-software-src/riscv-tests

Yay, my #riscv implementation in spade is now far along that I can run ISA tests.

#cocotb makes it really simple to generate test cases from the compiled elf files in https://github.com/riscv-software-src/riscv-tests