Search

1000 results for “pipelinec”

1. 

   PipelineC @pipelinec · 2026-05-15 · 14:22 UTC

   The StreamSoC demo is a fun music visualizer and video feedback experiment.
   But also is a reference for how easy PipelineC makes it to design your own SoC.
   Happy to help anyone give their own project a try!

   https://github.com/JulianKemmerer/PipelineC/wiki/Example:-StreamSoC

2. 

   PipelineC @pipelinec · 2026-05-15 · 14:21 UTC

   A SoC in C? StreamSoC shows how to move from embedded C software to custom PipelineC hardware for doing things like realtime streaming data processing.

   https://youtu.be/dzF3okigyog

3. 

   PipelineC @pipelinec · 2026-03-28 · 02:05 UTC

   Fun in the frequency domain 🤓 Camera pointed at it's own display also showing audio FFT for cool glitchy visualizer effect. Video processing all done in PipelineC hardware. And how?

   https://github.com/JulianKemmerer/PipelineC/wiki/Example:-Video-Pipelines

   #hardware #fpga #dsp #rtl #hdl #hls #verilog #vhdl #pipelinec

   #hardware #fpga #dsp #rtl #hdl #hls
4. 

   PipelineC @[email protected] · 2026-03-28 · 02:05 UTC

   Fun in the frequency domain 🤓 Camera pointed at it's own display also showing audio FFT for cool glitchy visualizer effect. Video processing all done in PipelineC hardware. And how?

   https://github.com/JulianKemmerer/PipelineC/wiki/Example:-Video-Pipelines

   #hardware #fpga #dsp #rtl #hdl #hls #verilog #vhdl #pipelinec

   #hardware #fpga #dsp #rtl #hdl #hls
5. 

   PipelineC @[email protected] · 2026-03-28 · 02:05 UTC

   Fun in the frequency domain 🤓 Camera pointed at it's own display also showing audio FFT for cool glitchy visualizer effect. Video processing all done in PipelineC hardware. And how?

   https://github.com/JulianKemmerer/PipelineC/wiki/Example:-Video-Pipelines

   #hardware #fpga #dsp #rtl #hdl #hls #verilog #vhdl #pipelinec

   #pipelinec #vhdl #verilog #hls #hdl #rtl
6. 

   PipelineC @[email protected] · 2026-03-28 · 02:05 UTC

   Fun in the frequency domain 🤓 Camera pointed at it's own display also showing audio FFT for cool glitchy visualizer effect. Video processing all done in PipelineC hardware. And how?

   https://github.com/JulianKemmerer/PipelineC/wiki/Example:-Video-Pipelines

   #hardware #fpga #dsp #rtl #hdl #hls #verilog #vhdl #pipelinec

   #hardware #fpga #dsp #rtl #hdl #hls
7. 

   PipelineC @[email protected] · 2026-03-28 · 02:04 UTC

   Fun in the frequency domain 🤓 Camera pointed at it's own display also showing audio FFT for cool glitchy visualizer effect. Video processing all done in PipelineC hardware. And how? github.com/JulianKemmer... #hardware #fpga #dsp #rtl #hdl #hls #verilog #vhdl #pipelinec

   #hardware #fpga #dsp #rtl #hdl #hls
8. 

   PipelineC @[email protected] · 2026-03-13 · 19:20 UTC

   @nlnetlabs.bsky.social NLnet Foundation funded open source WireGuard router in FPGA. Featuring PipelineC for cryptography blocks 🤓 github.com/JulianKemmer... #hardware #fpga #rtl #hdl #hls #verilog #vhdl #cryptography #wireguard #pipelinec

   #hardware #fpga #rtl #hdl #hls #verilog
9. 

   PipelineC @[email protected] · 2026-03-13 · 19:20 UTC

   @nlnetlabs.bsky.social NLnet Foundation funded open source WireGuard router in FPGA. Featuring PipelineC for cryptography blocks 🤓 github.com/JulianKemmer... #hardware #fpga #rtl #hdl #hls #verilog #vhdl #cryptography #wireguard #pipelinec

   #hardware #fpga #rtl #hdl #hls #verilog
10. 

    PipelineC @[email protected] · 2026-03-13 · 19:20 UTC

    @nlnetlabs.bsky.social NLnet Foundation funded open source WireGuard router in FPGA. Featuring PipelineC for cryptography blocks 🤓 github.com/JulianKemmer... #hardware #fpga #rtl #hdl #hls #verilog #vhdl #cryptography #wireguard #pipelinec

    #hardware #fpga #rtl #hdl #hls #verilog
11. 

    PipelineC @[email protected] · 2026-03-13 · 19:20 UTC

    @nlnetlabs.bsky.social NLnet Foundation funded open source WireGuard router in FPGA. Featuring PipelineC for cryptography blocks 🤓 github.com/JulianKemmer... #hardware #fpga #rtl #hdl #hls #verilog #vhdl #cryptography #wireguard #pipelinec

    #hardware #fpga #rtl #hdl #hls #verilog
12. 

    PipelineC @[email protected] · 2026-03-13 · 19:20 UTC

    @nlnet NLnet Foundation funded open source WireGuard router in FPGA. Featuring PipelineC for cryptography blocks 🤓

    https://github.com/JulianKemmerer/PipelineC/wiki/Example:-ChaCha20%E2%80%90Poly1305-for-WireGuard

    #hardware #fpga #rtl #hdl #hls #verilog #vhdl #cryptography #wireguard #pipelinec

    #hardware #fpga #rtl #hdl #hls #verilog
13. 

    PipelineC @pipelinec · 2026-03-13 · 19:20 UTC

    @nlnet NLnet Foundation funded open source WireGuard router in FPGA. Featuring PipelineC for cryptography blocks 🤓

    https://github.com/JulianKemmerer/PipelineC/wiki/Example:-ChaCha20%E2%80%90Poly1305-for-WireGuard

    #hardware #fpga #rtl #hdl #hls #verilog #vhdl #cryptography #wireguard #pipelinec

    #hardware #fpga #rtl #hdl #hls #verilog
14. 

    PipelineC @[email protected] · 2026-03-13 · 19:20 UTC

    @nlnet NLnet Foundation funded open source WireGuard router in FPGA. Featuring PipelineC for cryptography blocks 🤓

    https://github.com/JulianKemmerer/PipelineC/wiki/Example:-ChaCha20%E2%80%90Poly1305-for-WireGuard

    #hardware #fpga #rtl #hdl #hls #verilog #vhdl #cryptography #wireguard #pipelinec

    #hardware #fpga #rtl #hdl #hls #verilog
15. 

    PipelineC @[email protected] · 2026-03-13 · 19:20 UTC

    @nlnet NLnet Foundation funded open source WireGuard router in FPGA. Featuring PipelineC for cryptography blocks 🤓

    https://github.com/JulianKemmerer/PipelineC/wiki/Example:-ChaCha20%E2%80%90Poly1305-for-WireGuard

    #hardware #fpga #rtl #hdl #hls #verilog #vhdl #cryptography #wireguard #pipelinec

    #pipelinec #wireguard #cryptography #vhdl #verilog #hls
16. 

    PipelineC @[email protected] · 2026-03-13 · 19:20 UTC

    @nlnet NLnet Foundation funded open source WireGuard router in FPGA. Featuring PipelineC for cryptography blocks 🤓

    https://github.com/JulianKemmerer/PipelineC/wiki/Example:-ChaCha20%E2%80%90Poly1305-for-WireGuard

    #hardware #fpga #rtl #hdl #hls #verilog #vhdl #cryptography #wireguard #pipelinec

    #hardware #fpga #rtl #hdl #hls #verilog
17. 

    PipelineC @[email protected] · 2026-03-10 · 18:46 UTC

    PipelineC holds the throughput lead on Latchup.app. For now! How does your design stack up against a pipelining tool? Far too time consuming and fun of a site 🤓 Look forward to seeing competing solutions.

    https://github.com/JulianKemmerer/PipelineC/wiki/Example:-Latchup-Solutions

    #fpga #asic #rtl #hdl #verilog #vhdl #hls #eda

    #fpga #asic #rtl #hdl #verilog #vhdl
18. 

    PipelineC @pipelinec · 2026-03-10 · 18:46 UTC

    PipelineC holds the throughput lead on Latchup.app. For now! How does your design stack up against a pipelining tool? Far too time consuming and fun of a site 🤓 Look forward to seeing competing solutions.

    https://github.com/JulianKemmerer/PipelineC/wiki/Example:-Latchup-Solutions

    #fpga #asic #rtl #hdl #verilog #vhdl #hls #eda

    #fpga #asic #rtl #hdl #verilog #vhdl
19. 

    PipelineC @[email protected] · 2026-03-10 · 18:46 UTC

    PipelineC holds the throughput lead on Latchup.app. For now! How does your design stack up against a pipelining tool? Far too time consuming and fun of a site 🤓 Look forward to seeing competing solutions.

    https://github.com/JulianKemmerer/PipelineC/wiki/Example:-Latchup-Solutions

    #fpga #asic #rtl #hdl #verilog #vhdl #hls #eda

    #fpga #asic #rtl #hdl #verilog #vhdl
20. 

    PipelineC @[email protected] · 2026-03-10 · 18:46 UTC

    PipelineC holds the throughput lead on Latchup.app. For now! How does your design stack up against a pipelining tool? Far too time consuming and fun of a site 🤓 Look forward to seeing competing solutions.

    https://github.com/JulianKemmerer/PipelineC/wiki/Example:-Latchup-Solutions

    #fpga #asic #rtl #hdl #verilog #vhdl #hls #eda

    #eda #hls #vhdl #verilog #hdl #rtl
21. 

    PipelineC @[email protected] · 2026-03-10 · 18:46 UTC

    PipelineC holds the throughput lead on Latchup.app. For now! How does your design stack up against a pipelining tool? Far too time consuming and fun of a site 🤓 Look forward to seeing competing solutions.

    https://github.com/JulianKemmerer/PipelineC/wiki/Example:-Latchup-Solutions

    #fpga #asic #rtl #hdl #verilog #vhdl #hls #eda

    #fpga #asic #rtl #hdl #verilog #vhdl
22. 

    PipelineC @pipelinec · 2026-02-13 · 21:50 UTC

    Easy: draw_rect_t struct shared between embedded C software and PipelineC hardware. Mem mapped registers enqueue into command FIFO. Small hardware FSM reads from cmd FIFO does simple iteration to draw a rect of pixels.

    https://github.com/JulianKemmerer/PipelineC/tree/master/examples/stream_soc/gpu

    #hardware #fpga #rtl #hls #hdl #graphics #gpu #cpu

    #hardware #fpga #rtl #hls #hdl #graphics
23. 

    PipelineC @pipelinec · 2026-02-13 · 21:47 UTC

    Is a hardware FSM that draws rectangles to a frame buffer a GPU? Well whatever you call it, it's no longer the CPU pushing pixels in the PipelineC StreamSoC design. Now it sends 'draw rectangle' commands to hardware. And how? #hardware #fpga #rtl #hls #hdl #graphics #gpu #cpu

    #hardware #fpga #rtl #hls #hdl #graphics
24. 

    PipelineC @pipelinec · 2026-02-12 · 17:13 UTC

    Check out PipelineC #HDL Advent of FPGA #hardware solutions: high perf, deeply pipelined, multiple #FPGA platforms, 10's Gbit per sec throughput, easily scales: variable latency off chip mem, faster off chip IO and more resources.

    https://github.com/JulianKemmerer/PipelineC/wiki/Example:-Advent-of-Code-2025

    #rtl #hls #verilog #vhdl #asic #eda

    #hdl #hardware #fpga #rtl #hls #verilog
25. 

    PipelineC @pipelinec · 2026-01-01 · 19:56 UTC

    Advent of Code Day 7: very simple design, good intro to #pipelinec. processing all ~hundreds of elements of an entire line each cycle. ~600 million to ~5.3 billion tachyon beams splitting per second. 😎

    https://github.com/JulianKemmerer/PipelineC/blob/master/examples/aof25/day7.c

    #aoc25 #fpga #hardware #verilog #vhdl #hdl #rtl #hls #asic #eda

    #pipelinec #aoc25 #fpga #hardware #verilog #vhdl
26. 

    PipelineC @[email protected] · 2026-01-01 · 19:56 UTC

    Advent of Code Day 7: very simple design, good intro to #pipelinec. processing all ~hundreds of elements of an entire line each cycle. ~600 million to ~5.3 billion tachyon beams splitting per second. 😎

    https://github.com/JulianKemmerer/PipelineC/blob/master/examples/aof25/day7.c

    #aoc25 #fpga #hardware #verilog #vhdl #hdl #rtl #hls #asic #eda

    #pipelinec #aoc25 #fpga #hardware #verilog #vhdl
27. 

    PipelineC @[email protected] · 2026-01-01 · 19:56 UTC

    Advent of Code Day 7: very simple design, good intro to #pipelinec. processing all ~hundreds of elements of an entire line each cycle. ~600 million to ~5.3 billion tachyon beams splitting per second. 😎

    https://github.com/JulianKemmerer/PipelineC/blob/master/examples/aof25/day7.c

    #aoc25 #fpga #hardware #verilog #vhdl #hdl #rtl #hls #asic #eda

    #eda #asic #hls #rtl #hdl #vhdl
28. 

    PipelineC @[email protected] · 2026-01-01 · 19:56 UTC

    Advent of Code Day 7: very simple design, good intro to #pipelinec. processing all ~hundreds of elements of an entire line each cycle. ~600 million to ~5.3 billion tachyon beams splitting per second. 😎

    https://github.com/JulianKemmerer/PipelineC/blob/master/examples/aof25/day7.c

    #aoc25 #fpga #hardware #verilog #vhdl #hdl #rtl #hls #asic #eda

    #pipelinec #aoc25 #fpga #hardware #verilog #vhdl
29. 

    PipelineC @[email protected] · 2026-01-01 · 19:56 UTC

    Advent of Code Day 7: very simple design, good intro to #pipelinec. processing all ~hundreds of elements of an entire line each cycle. ~600 million to ~5.3 billion tachyon beams splitting per second. 😎 github.com/JulianKemmer... #aoc25 #fpga #hardware #verilog #vhdl #hdl #rtl #hls #asic #eda
    
    github.com/JulianKemmerer...

    #pipelinec #aoc25 #fpga #hardware #verilog #vhdl
30. 

    PipelineC @[email protected] · 2026-01-01 · 19:56 UTC

    Advent of Code Day 7: very simple design, good intro to #pipelinec. processing all ~hundreds of elements of an entire line each cycle. ~600 million to ~5.3 billion tachyon beams splitting per second. 😎 github.com/JulianKemmer... #aoc25 #fpga #hardware #verilog #vhdl #hdl #rtl #hls #asic #eda
    
    github.com/JulianKemmerer...

    #pipelinec #aoc25 #fpga #hardware #verilog #vhdl