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42 results for “yosyshq”

1. 

   YosysHQ @yosyshq · 2025-09-29 · 10:54 UTC

   Our next #YUG will be with Matt Young, talking about triple modular redundancy.

   Join us at 18:00 CET / 22:30 IST / 09:00 PT on Thursday 9th October.

   Sign up to our mailing list to get a reminder before the event: https://blog.yosyshq.com/newsletter/

   #yug
2. 

   YosysHQ @yosyshq · 2025-09-18 · 15:29 UTC

   We are #hiring! Both tech and admin positions available!

   https://www.yosyshq.com/jobs

   #hire #fedihire

   #hiring #hire #fedihire
3. 

   YosysHQ @yosyshq · 2024-02-19 · 11:49 UTC

   Want to try simulating #ASIC logic gates with #kicad It’s never been easier thanks to​​​​​​ Aki Van Ness (https://chaos.social/@lethalbit)! Check the latest #yosyshq blog post here:

   https://blog.yosyshq.com/p/sky130-kicad-spice/

   #asic #yosyshq #kicad
4. 

   YosysHQ @yosyshq · 2023-12-04 · 16:05 UTC

   All the plugins!

   Come along to #YUG 4 on Thursday December 7th at 09:00 PT / 18:00 CET / 22:30 IST

   This month we’ll be looking at the Yosys plugin system, some of your favorite plugins and not one but two special guest presentations from Martin Povišer and Gabriel Gouvine. <accounts in linkedin/twitter/etc>

   To get reminded on the day, join our newsletter https://www.yosyshq.com/newsletter

   See you there!

   #yug
5. 

   YosysHQ @yosyshq · 2023-09-04 · 15:24 UTC

   yosys users group - meet-up #002

   September 7th at 18:00 CEST.

   We'll start with a demo of our new formal equivalence checker targetting the #OpenLane #ASIC flow. Bring your own design to follow along!

   Afterwards we'll have time for your questions and suggestions.
   Feel free to bring a friend!

   Use this link to join:

   https://meet.jit.si/NoisyAssembliesExpressEach

   The YosysHQ team will be present and are looking forward to meeting you!

   #yosys #fpga #meetup

   #openlane #asic #yosys #fpga #meetup
6. 

   YosysHQ @[email protected] · 2023-09-04 · 15:24 UTC

   yosys users group - meet-up #002

   September 7th at 18:00 CEST.

   We'll start with a demo of our new formal equivalence checker targetting the #OpenLane #ASIC flow. Bring your own design to follow along!

   Afterwards we'll have time for your questions and suggestions.
   Feel free to bring a friend!

   Use this link to join:

   https://meet.jit.si/NoisyAssembliesExpressEach

   The YosysHQ team will be present and are looking forward to meeting you!

   #yosys #fpga #meetup

   #openlane #asic #yosys #fpga #meetup
7. 

   YosysHQ @[email protected] · 2023-09-04 · 15:24 UTC

   yosys users group - meet-up #002

   September 7th at 18:00 CEST.

   We'll start with a demo of our new formal equivalence checker targetting the #OpenLane #ASIC flow. Bring your own design to follow along!

   Afterwards we'll have time for your questions and suggestions.
   Feel free to bring a friend!

   Use this link to join:

   https://meet.jit.si/NoisyAssembliesExpressEach

   The YosysHQ team will be present and are looking forward to meeting you!

   #yosys #fpga #meetup

   #openlane #asic #yosys #fpga #meetup
8. 

   YosysHQ @[email protected] · 2023-09-04 · 15:24 UTC

   yosys users group - meet-up #002

   September 7th at 18:00 CEST.

   We'll start with a demo of our new formal equivalence checker targetting the #OpenLane #ASIC flow. Bring your own design to follow along!

   Afterwards we'll have time for your questions and suggestions.
   Feel free to bring a friend!

   Use this link to join:

   https://meet.jit.si/NoisyAssembliesExpressEach

   The YosysHQ team will be present and are looking forward to meeting you!

   #yosys #fpga #meetup

   #meetup #fpga #yosys #asic #openlane
9. 

   YosysHQ @[email protected] · 2023-09-04 · 15:24 UTC

   yosys users group - meet-up #002

   September 7th at 18:00 CEST.

   We'll start with a demo of our new formal equivalence checker targetting the #OpenLane #ASIC flow. Bring your own design to follow along!

   Afterwards we'll have time for your questions and suggestions.
   Feel free to bring a friend!

   Use this link to join:

   https://meet.jit.si/NoisyAssembliesExpressEach

   The YosysHQ team will be present and are looking forward to meeting you!

   #yosys #fpga #meetup

   #openlane #asic #yosys #fpga #meetup
10. 

    YosysHQ @yosyshq · 2022-12-19 · 15:41 UTC

    We just published our first #communityspotlight

    Tbengy by Prasad Pandit is a Python Tool for SV/UVM Testbench Generation and RTL Synthesis.

    Prasad is looking for feedback from experienced users in the hardware and software domains.

    https://blog.yosyshq.com/p/community-spotlight-tbengy/

    #communityspotlight
11. 

    Flux @[email protected] · 2026-05-09 · 11:42 UTC

    Have you upgraded your @yosyshq yosys recently? #FPGA

    0.49 (Jan 2025): TRELLIS_COMB: 4357
    0.64 (May 2026): TRELLIS_COMB: 3682

    15% LUT saving with no change in my Verilog design. 👏

    #fpga
12. 

    Flux @[email protected] · 2026-05-09 · 11:42 UTC

    Have you upgraded your @yosyshq yosys recently? #FPGA

    0.49 (Jan 2025): TRELLIS_COMB: 4357
    0.64 (May 2026): TRELLIS_COMB: 3682

    15% LUT saving with no change in my Verilog design. 👏

    #fpga
13. 

    Flux @[email protected] · 2026-05-09 · 11:42 UTC

    Have you upgraded your @yosyshq yosys recently? #FPGA

    0.49 (Jan 2025): TRELLIS_COMB: 4357
    0.64 (May 2026): TRELLIS_COMB: 3682

    15% LUT saving with no change in my Verilog design. 👏

    #fpga
14. 

    Flux @[email protected] · 2026-05-09 · 11:42 UTC

    Have you upgraded your @yosyshq yosys recently? #FPGA

    0.49 (Jan 2025): TRELLIS_COMB: 4357
    0.64 (May 2026): TRELLIS_COMB: 3682

    15% LUT saving with no change in my Verilog design. 👏

    #fpga
15. 

    Flux @[email protected] · 2026-05-09 · 11:42 UTC

    Have you upgraded your @yosyshq yosys recently? #FPGA

    0.49 (Jan 2025): TRELLIS_COMB: 4357
    0.64 (May 2026): TRELLIS_COMB: 3682

    15% LUT saving with no change in my Verilog design. 👏

    #fpga
16. 

    iPostHuman @[email protected] · 2023-01-22 · 15:37 UTC

    After Hours Engineering:

    Welcome to a new journey exploring Systems on a Chip (SoC)s. In the series I'll focus mainly on two--possibly 4 SBCs--from Lone Dynamic's Machdyne range of boards: Schoko, Eis and Konfekt (not shown in video), and possibly the BlackiceEdge.

    https://youtu.be/KwU_U5LCJcc

    #fpga, #YosysHQ, #SoC, #SystemVerilog, #Machdyne, #RISC-V
    .
    🍺🍕📺

    #fpga #yosyshq #soc #systemverilog #machdyne #risc
17. 

    plaes @[email protected] · 2025-10-07 · 19:35 UTC

    One step closer to UNIX v1 using open source toolchain: https://github.com/YosysHQ/yosys/pull/5411

    #pipdp11 #yosys #gowin #fpga #retrocomputing

    #pipdp11 #yosys #gowin #fpga #retrocomputing
18. 

    plaes @[email protected] · 2025-10-07 · 19:35 UTC

    One step closer to UNIX v1 using open source toolchain: https://github.com/YosysHQ/yosys/pull/5411

    #pipdp11 #yosys #gowin #fpga #retrocomputing

    #pipdp11 #yosys #gowin #fpga #retrocomputing
19. 

    plaes @[email protected] · 2025-10-07 · 19:35 UTC

    One step closer to UNIX v1 using open source toolchain: https://github.com/YosysHQ/yosys/pull/5411

    #pipdp11 #yosys #gowin #fpga #retrocomputing

    #pipdp11 #yosys #gowin #fpga #retrocomputing
20. 

    plaes @[email protected] · 2025-10-07 · 19:35 UTC

    One step closer to UNIX v1 using open source toolchain: https://github.com/YosysHQ/yosys/pull/5411

    #pipdp11 #yosys #gowin #fpga #retrocomputing

    #retrocomputing #fpga #gowin #yosys #pipdp11
21. 

    plaes @[email protected] · 2025-10-07 · 19:35 UTC

    One step closer to UNIX v1 using open source toolchain: https://github.com/YosysHQ/yosys/pull/5411

    #pipdp11 #yosys #gowin #fpga #retrocomputing

    #pipdp11 #yosys #gowin #fpga #retrocomputing
22. 

    iPostHuman @[email protected] · 2022-12-30 · 14:14 UTC

    After Hours Engineering, Episode 20 just posted! Final episode!

    https://youtu.be/DnlRsO3_0Cw

    Source code: https://github.com/wdevore/RangerRisc...

    Description:
    This is the "last" episode of the RISC-V series. In it we add a PLL and reintroduce interrupts via CSRs.
    At the end I discuss future "potential" series that involve FPGAs.

    Using the BlackiceEdge from #folknology

    #fpga, #YosysHQ, #IceStorm, #RISC-V
    .
    🍺🍕📺

    #folknology #fpga #yosyshq #icestorm #risc
23. 

    iPostHuman @[email protected] · 2022-12-12 · 15:08 UTC

    After Hours Engineering, Episode 19 just posted!

    In this episode we FINALLY synthesize the RISC-V RangerRisc softcore CPU!

    https://youtu.be/n80-B5BAXP8

    Using the BlackiceEdge from #folknology

    #fpga, #YosysHQ, #IceStorm, #RISC-V
    .
    🍺🍕📺

    #folknology #fpga #yosyshq #icestorm #risc
24. 

    iPostHuman @[email protected] · 2022-11-25 · 13:36 UTC

    After Hours Engineering, Episode 18 just posted!

    In this episode we learn about UART via simulating and synthesizing.

    https://youtu.be/5uUvWfJpWrE

    Using the BlackiceEdge from #folknology

    #fpga, #YosysHQ, #IceStorm, #RISC-V
    .
    🍺🍕📺

    #folknology #fpga #yosyshq #icestorm #risc
25. 

    iPostHuman @[email protected] · 2022-11-11 · 15:41 UTC

    After Hours Engineering, Episode 17 just posted!

    In this episode we learn about SPI and synthesize a SPI Slave that pretends to be an MCP23S17 IO Expander and by that I mean a trivial pattern matcher.

    https://youtu.be/0oNpulbLews

    Using the BlackiceEdge from #folknology

    #fpga, #YosysHQ, #IceStorm, #RISC-V
    .
    🍺🍕📺

    #folknology #fpga #yosyshq #icestorm #risc
26. 

    Olimex @[email protected] · 2026-05-01 · 08:31 UTC

    Cologne Chip continues to push the FPGA ecosystem forward with support for free and open-source toolchain. By releasing a fully open-source toolchain, YosysHQ establish Cologne Chip as a leading supporter of transparent FPGA development. https://colognechip.com/programmable-logic/gatemate/toolchain/ #FPGA #OpenSource #GateMate #EDA

    EDIT: as per @infosecdj note CologneChip did not release the toolchain. It is run by @yosyshq

    #fpga #opensource #gatemate #eda
27. 

    Olimex @[email protected] · 2026-05-01 · 08:31 UTC

    Cologne Chip continues to push the FPGA ecosystem forward with support for free and open-source toolchain. By releasing a fully open-source toolchain, YosysHQ establish Cologne Chip as a leading supporter of transparent FPGA development. https://colognechip.com/programmable-logic/gatemate/toolchain/ #FPGA #OpenSource #GateMate #EDA

    EDIT: as per @infosecdj note CologneChip did not release the toolchain. It is run by @yosyshq

    #fpga #opensource #gatemate #eda
28. 

    Olimex @[email protected] · 2026-05-01 · 08:31 UTC

    Cologne Chip continues to push the FPGA ecosystem forward with support for free and open-source toolchain. By releasing a fully open-source toolchain, YosysHQ establish Cologne Chip as a leading supporter of transparent FPGA development. https://colognechip.com/programmable-logic/gatemate/toolchain/ #FPGA #OpenSource #GateMate #EDA

    EDIT: as per @infosecdj note CologneChip did not release the toolchain. It is run by @yosyshq

    #fpga #opensource #gatemate #eda
29. 

    Olimex @[email protected] · 2026-05-01 · 08:31 UTC

    Cologne Chip continues to push the FPGA ecosystem forward with support for free and open-source toolchain. By releasing a fully open-source toolchain, YosysHQ establish Cologne Chip as a leading supporter of transparent FPGA development. https://colognechip.com/programmable-logic/gatemate/toolchain/ #FPGA #OpenSource #GateMate #EDA

    EDIT: as per @infosecdj note CologneChip did not release the toolchain. It is run by @yosyshq

    #eda #gatemate #opensource #fpga
30. 

    Olimex @[email protected] · 2026-05-01 · 08:31 UTC

    Cologne Chip continues to push the FPGA ecosystem forward with support for free and open-source toolchain. By releasing a fully open-source toolchain, YosysHQ establish Cologne Chip as a leading supporter of transparent FPGA development. https://colognechip.com/programmable-logic/gatemate/toolchain/ #FPGA #OpenSource #GateMate #EDA

    EDIT: as per @infosecdj note CologneChip did not release the toolchain. It is run by @yosyshq

    #fpga #opensource #gatemate #eda